source: mainline/uspace/drv/bus/usb/xhci/hc.h

Last change on this file was 8300c72, checked in by Jiri Svoboda <jiri@…>, 4 months ago

Quiesce devices before proceeding with shutdown.

Only implemented for e1k, uhci and xhci.

  • Property mode set to 100644
File size: 4.5 KB
RevLine 
[5cbccd4]1/*
[8300c72]2 * Copyright (c) 2025 Jiri Svoboda
[e0a5d4c]3 * Copyright (c) 2018 Ondrej Hlavaty, Jan Hrach, Jaroslav Jindrak, Petr Manek
[5cbccd4]4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup drvusbxhci
31 * @{
32 */
33/** @file
34 * @brief The host controller data bookkeeping.
35 */
36
[115f25b]37#ifndef XHCI_HC_H
38#define XHCI_HC_H
39
[74b852b]40#include <fibril_synch.h>
[36795edf]41#include <member.h>
[e4d7363]42#include <usb/host/usb_transfer_batch.h>
[73a5857]43#include <usb/host/utility.h>
[5cbccd4]44#include "hw_struct/regs.h"
[cb89430]45#include "hw_struct/context.h"
[fd9f4ffe]46#include "scratchpad.h"
[cb89430]47#include "trb_ring.h"
[2cf28b9]48
[d32d51d]49#include "rh.h"
[889146e]50#include "commands.h"
[41924f30]51#include "bus.h"
[5cbccd4]52
[889146e]53typedef struct xhci_command xhci_cmd_t;
54
[5cbccd4]55typedef struct xhci_hc {
[32fb6bce]56 /** Common HC device header */
57 hc_device_t base;
58
[91ca111]59 /* MMIO range */
60 addr_range_t mmio_range;
61
62 /* Mapped register sets */
[20eaa82]63 void *reg_base;
[5cbccd4]64 xhci_cap_regs_t *cap_regs;
65 xhci_op_regs_t *op_regs;
[62ba2cbe]66 xhci_rt_regs_t *rt_regs;
67 xhci_doorbell_t *db_arry;
[91ca111]68 xhci_extcap_t *xecp; /**< First extended capability */
69 xhci_legsup_t *legsup; /**< Legacy support capability */
[cb89430]70
[91ca111]71 /* Structures in allocated memory */
[cb89430]72 xhci_event_ring_t event_ring;
[73e5b62]73 uint64_t *dcbaa;
[b80c1ab]74 dma_buffer_t dcbaa_dma;
75 dma_buffer_t scratchpad_array;
[cb89430]76
[889146e]77 /* Command ring management */
78 xhci_cmd_ring_t cr;
79
[2c0564c]80 /* Buffer for events */
81 xhci_sw_ring_t sw_ring;
82
[73a5857]83 /** Event handling fibril */
84 joinable_fibril_t *event_worker;
[2c0564c]85
[07c08ea]86 /* Root hub emulation */
[d32d51d]87 xhci_rh_t rh;
88
[41924f30]89 /* Bus bookkeeping */
90 xhci_bus_t bus;
91
[f3baab1]92 /* Fibril that is currently hanling events */
93 fid_t event_handler;
94
[91ca111]95 /* Cached capabilities */
[cb89430]96 unsigned max_slots;
97 bool ac64;
[7ec7b7e]98 bool csz;
[ae3a941]99 uint64_t wrap_time; /**< The last time when mfindex wrap happened */
100 uint64_t wrap_count; /**< Amount of mfindex wraps HC has done */
101 unsigned ist; /**< IST in microframes */
[110d795]102
[f668d60]103 /** Port speed mapping */
104 xhci_port_speed_t speeds [16];
[5cbccd4]105} xhci_hc_t;
106
[32fb6bce]107static inline xhci_hc_t *bus_to_hc(bus_t *bus)
108{
109 assert(bus);
110 return member_to_inst(bus, xhci_hc_t, bus);
111}
112
[0206d35]113typedef struct xhci_endpoint xhci_endpoint_t;
114typedef struct xhci_device xhci_device_t;
115
[45457265]116extern errno_t hc_init_mmio(xhci_hc_t *, const hw_res_list_parsed_t *);
117extern errno_t hc_init_memory(xhci_hc_t *, ddf_dev_t *);
118extern errno_t hc_claim(xhci_hc_t *, ddf_dev_t *);
119extern errno_t hc_irq_code_gen(irq_code_t *, xhci_hc_t *, const hw_res_list_parsed_t *, int *);
120extern errno_t hc_start(xhci_hc_t *);
[3dd80f8]121extern void hc_fini(xhci_hc_t *);
[8300c72]122extern errno_t hc_quiesce(xhci_hc_t *);
[3dd80f8]123
124extern void hc_ring_doorbell(xhci_hc_t *, unsigned, unsigned);
125extern void hc_ring_ep_doorbell(xhci_endpoint_t *, uint32_t);
126extern unsigned hc_speed_to_psiv(usb_speed_t);
127
[45457265]128extern errno_t hc_enable_slot(xhci_device_t *);
129extern errno_t hc_disable_slot(xhci_device_t *);
130extern errno_t hc_address_device(xhci_device_t *);
131extern errno_t hc_configure_device(xhci_device_t *);
132extern errno_t hc_deconfigure_device(xhci_device_t *);
133extern errno_t hc_add_endpoint(xhci_endpoint_t *);
134extern errno_t hc_drop_endpoint(xhci_endpoint_t *);
135extern errno_t hc_update_endpoint(xhci_endpoint_t *);
136extern errno_t hc_stop_endpoint(xhci_endpoint_t *);
137extern errno_t hc_reset_endpoint(xhci_endpoint_t *);
138extern errno_t hc_reset_ring(xhci_endpoint_t *, uint32_t);
139
140extern errno_t hc_status(bus_t *, uint32_t *);
[3dd80f8]141extern void hc_interrupt(bus_t *, uint32_t);
[32fb6bce]142
[115f25b]143#endif
144
[5cbccd4]145/**
146 * @}
147 */
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