1 | /*
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2 | * Copyright (c) 2025 Jiri Svoboda
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3 | * Copyright (c) 2018 Ondrej Hlavaty, Jan Hrach, Jaroslav Jindrak, Petr Manek
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4 | * All rights reserved.
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5 | *
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6 | * Redistribution and use in source and binary forms, with or without
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7 | * modification, are permitted provided that the following conditions
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8 | * are met:
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9 | *
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10 | * - Redistributions of source code must retain the above copyright
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11 | * notice, this list of conditions and the following disclaimer.
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12 | * - Redistributions in binary form must reproduce the above copyright
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13 | * notice, this list of conditions and the following disclaimer in the
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14 | * documentation and/or other materials provided with the distribution.
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15 | * - The name of the author may not be used to endorse or promote products
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16 | * derived from this software without specific prior written permission.
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17 | *
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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28 | */
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29 |
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30 | /** @addtogroup drvusbxhci
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31 | * @{
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32 | */
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33 | /** @file
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34 | * @brief The host controller data bookkeeping.
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35 | */
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36 |
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37 | #ifndef XHCI_HC_H
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38 | #define XHCI_HC_H
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39 |
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40 | #include <fibril_synch.h>
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41 | #include <member.h>
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42 | #include <usb/host/usb_transfer_batch.h>
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43 | #include <usb/host/utility.h>
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44 | #include "hw_struct/regs.h"
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45 | #include "hw_struct/context.h"
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46 | #include "scratchpad.h"
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47 | #include "trb_ring.h"
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48 |
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49 | #include "rh.h"
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50 | #include "commands.h"
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51 | #include "bus.h"
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52 |
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53 | typedef struct xhci_command xhci_cmd_t;
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54 |
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55 | typedef struct xhci_hc {
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56 | /** Common HC device header */
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57 | hc_device_t base;
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58 |
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59 | /* MMIO range */
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60 | addr_range_t mmio_range;
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61 |
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62 | /* Mapped register sets */
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63 | void *reg_base;
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64 | xhci_cap_regs_t *cap_regs;
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65 | xhci_op_regs_t *op_regs;
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66 | xhci_rt_regs_t *rt_regs;
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67 | xhci_doorbell_t *db_arry;
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68 | xhci_extcap_t *xecp; /**< First extended capability */
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69 | xhci_legsup_t *legsup; /**< Legacy support capability */
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70 |
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71 | /* Structures in allocated memory */
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72 | xhci_event_ring_t event_ring;
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73 | uint64_t *dcbaa;
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74 | dma_buffer_t dcbaa_dma;
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75 | dma_buffer_t scratchpad_array;
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76 |
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77 | /* Command ring management */
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78 | xhci_cmd_ring_t cr;
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79 |
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80 | /* Buffer for events */
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81 | xhci_sw_ring_t sw_ring;
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82 |
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83 | /** Event handling fibril */
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84 | joinable_fibril_t *event_worker;
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85 |
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86 | /* Root hub emulation */
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87 | xhci_rh_t rh;
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88 |
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89 | /* Bus bookkeeping */
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90 | xhci_bus_t bus;
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91 |
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92 | /* Fibril that is currently hanling events */
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93 | fid_t event_handler;
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94 |
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95 | /* Cached capabilities */
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96 | unsigned max_slots;
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97 | bool ac64;
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98 | bool csz;
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99 | uint64_t wrap_time; /**< The last time when mfindex wrap happened */
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100 | uint64_t wrap_count; /**< Amount of mfindex wraps HC has done */
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101 | unsigned ist; /**< IST in microframes */
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102 |
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103 | /** Port speed mapping */
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104 | xhci_port_speed_t speeds [16];
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105 | } xhci_hc_t;
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106 |
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107 | static inline xhci_hc_t *bus_to_hc(bus_t *bus)
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108 | {
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109 | assert(bus);
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110 | return member_to_inst(bus, xhci_hc_t, bus);
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111 | }
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112 |
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113 | typedef struct xhci_endpoint xhci_endpoint_t;
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114 | typedef struct xhci_device xhci_device_t;
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115 |
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116 | extern errno_t hc_init_mmio(xhci_hc_t *, const hw_res_list_parsed_t *);
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117 | extern errno_t hc_init_memory(xhci_hc_t *, ddf_dev_t *);
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118 | extern errno_t hc_claim(xhci_hc_t *, ddf_dev_t *);
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119 | extern errno_t hc_irq_code_gen(irq_code_t *, xhci_hc_t *, const hw_res_list_parsed_t *, int *);
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120 | extern errno_t hc_start(xhci_hc_t *);
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121 | extern void hc_fini(xhci_hc_t *);
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122 | extern errno_t hc_quiesce(xhci_hc_t *);
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123 |
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124 | extern void hc_ring_doorbell(xhci_hc_t *, unsigned, unsigned);
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125 | extern void hc_ring_ep_doorbell(xhci_endpoint_t *, uint32_t);
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126 | extern unsigned hc_speed_to_psiv(usb_speed_t);
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127 |
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128 | extern errno_t hc_enable_slot(xhci_device_t *);
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129 | extern errno_t hc_disable_slot(xhci_device_t *);
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130 | extern errno_t hc_address_device(xhci_device_t *);
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131 | extern errno_t hc_configure_device(xhci_device_t *);
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132 | extern errno_t hc_deconfigure_device(xhci_device_t *);
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133 | extern errno_t hc_add_endpoint(xhci_endpoint_t *);
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134 | extern errno_t hc_drop_endpoint(xhci_endpoint_t *);
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135 | extern errno_t hc_update_endpoint(xhci_endpoint_t *);
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136 | extern errno_t hc_stop_endpoint(xhci_endpoint_t *);
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137 | extern errno_t hc_reset_endpoint(xhci_endpoint_t *);
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138 | extern errno_t hc_reset_ring(xhci_endpoint_t *, uint32_t);
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139 |
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140 | extern errno_t hc_status(bus_t *, uint32_t *);
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141 | extern void hc_interrupt(bus_t *, uint32_t);
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142 |
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143 | #endif
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144 |
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145 | /**
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146 | * @}
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147 | */
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