source: mainline/uspace/drv/bus/usb/xhci/hc.c@ fd9f4ffe

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since fd9f4ffe was fd9f4ffe, checked in by Jaroslav Jindrak <dzejrou@…>, 8 years ago

The xHC now properly gets the physical addresses (with correct endianity) of its scratchpad buffers.
  • Property mode set to 100644
File size: 11.7 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "hw_struct/trb.h"
43#include "commands.h"
44
45static const irq_cmd_t irq_commands[] = {
46 {
47 .cmd = CMD_PIO_READ_32,
48 .dstarg = 1,
49 .addr = NULL
50 },
51 {
52 .cmd = CMD_AND,
53 .srcarg = 1,
54 .dstarg = 2,
55 .value = 0
56 },
57 {
58 .cmd = CMD_PREDICATE,
59 .srcarg = 2,
60 .value = 2
61 },
62 {
63 .cmd = CMD_PIO_WRITE_A_32,
64 .srcarg = 1,
65 .addr = NULL
66 },
67 {
68 .cmd = CMD_ACCEPT
69 }
70};
71
72/**
73 * Default USB Speed ID mapping: Table 157
74 */
75#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
76#define PORT_SPEED(psie, psim) { \
77 .rx_bps = PSI_TO_BPS(psie, psim), \
78 .tx_bps = PSI_TO_BPS(psie, psim) \
79}
80static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 12);
81static const xhci_port_speed_t ps_default_low = PORT_SPEED(1, 1500);
82static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 480);
83static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 5);
84
85/**
86 * Walk the list of extended capabilities.
87 */
88static int hc_parse_ec(xhci_hc_t *hc)
89{
90 unsigned psic, major;
91
92 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
93 xhci_dump_extcap(ec);
94 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
95 case XHCI_EC_USB_LEGACY:
96 assert(hc->legsup == NULL);
97 hc->legsup = (xhci_legsup_t *) ec;
98 break;
99 case XHCI_EC_SUPPORTED_PROTOCOL:
100 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
101 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
102
103 // "Implied" speed
104 if (psic == 0) {
105 /*
106 * According to section 7.2.2.1.2, only USB 2.0
107 * and USB 3.0 can have psic == 0. So we
108 * blindly assume the name == "USB " and minor
109 * == 0.
110 */
111 if (major == 2) {
112 hc->speeds[1] = ps_default_full;
113 hc->speeds[2] = ps_default_low;
114 hc->speeds[3] = ps_default_high;
115 } else if (major == 3) {
116 hc->speeds[4] = ps_default_super;
117 } else {
118 return EINVAL;
119 }
120
121 usb_log_debug2("Implied speed of USB %u set up.", major);
122 } else {
123 for (unsigned i = 0; i < psic; i++) {
124 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
125 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
126 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
127 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
128 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
129
130 uint64_t bps = PSI_TO_BPS(psie, psim);
131
132 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
133 hc->speeds[psiv].rx_bps = bps;
134 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
135 hc->speeds[psiv].tx_bps = bps;
136 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, hc->speeds[psiv].rx_bps, hc->speeds[psiv].tx_bps);
137 }
138 }
139 }
140 }
141 }
142 return EOK;
143}
144
145int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
146{
147 int err;
148
149 if (hw_res->mem_ranges.count != 1) {
150 usb_log_error("Unexpected MMIO area, bailing out.");
151 return EINVAL;
152 }
153
154 hc->mmio_range = hw_res->mem_ranges.ranges[0];
155
156 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
157 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
158
159 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
160 return EOVERFLOW;
161
162 void *base;
163 if ((err = pio_enable_range(&hc->mmio_range, &base)))
164 return err;
165
166 hc->base = base;
167 hc->cap_regs = (xhci_cap_regs_t *) base;
168 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
169 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
170 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
171
172 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
173 if (xec_offset > 0)
174 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
175
176 usb_log_debug2("Initialized MMIO reg areas:");
177 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
178 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
179 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
180 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
181
182 xhci_dump_cap_regs(hc->cap_regs);
183
184 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
185 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
186
187 if ((err = hc_parse_ec(hc))) {
188 pio_disable(hc->base, RNGSZ(hc->mmio_range));
189 return err;
190 }
191
192 return EOK;
193}
194
195int hc_init_memory(xhci_hc_t *hc)
196{
197 int err;
198
199 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(xhci_device_ctx_t*));
200 if (!hc->dcbaa)
201 return ENOMEM;
202
203 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
204 goto err_dcbaa;
205
206 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
207 goto err_cmd_ring;
208
209 if ((err = xhci_scratchpad_alloc(hc)))
210 goto err_event_ring;
211
212 return EOK;
213
214err_event_ring:
215 xhci_event_ring_fini(&hc->event_ring);
216err_cmd_ring:
217 xhci_trb_ring_fini(&hc->command_ring);
218err_dcbaa:
219 free32(hc->dcbaa);
220 return err;
221}
222
223
224/**
225 * Generates code to accept interrupts. The xHCI is designed primarily for
226 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
227 * (except 0) are disabled.
228 */
229int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
230{
231 assert(code);
232 assert(hw_res);
233
234 if (hw_res->irqs.count != 1) {
235 usb_log_info("Unexpected HW resources to enable interrupts.");
236 return EINVAL;
237 }
238
239 code->ranges = malloc(sizeof(irq_pio_range_t));
240 if (code->ranges == NULL)
241 return ENOMEM;
242
243 code->cmds = malloc(sizeof(irq_commands));
244 if (code->cmds == NULL) {
245 free(code->ranges);
246 return ENOMEM;
247 }
248
249 code->rangecount = 1;
250 code->ranges[0] = (irq_pio_range_t) {
251 .base = RNGABS(hc->mmio_range),
252 .size = RNGSZ(hc->mmio_range),
253 };
254
255 code->cmdcount = ARRAY_SIZE(irq_commands);
256 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
257
258 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
259 code->cmds[0].addr = intr0_iman;
260 code->cmds[3].addr = intr0_iman;
261 code->cmds[1].value = host2xhci(32, 1);
262
263 return hw_res->irqs.irqs[0];
264}
265
266int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
267{
268 /* No legacy support capability, the controller is solely for us */
269 if (!hc->legsup)
270 return EOK;
271
272 /*
273 * TODO: Implement handoff from BIOS, section 4.22.1
274 * QEMU does not support this, so we have to test on real HW.
275 */
276 return ENOTSUP;
277}
278
279static int hc_reset(xhci_hc_t *hc)
280{
281 /* Stop the HC: set R/S to 0 */
282 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
283
284 /* Wait 16 ms until the HC is halted */
285 async_usleep(16000);
286 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
287
288 /* Reset */
289 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
290
291 /* Wait until the reset is complete */
292 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
293 async_usleep(1000);
294
295 return EOK;
296}
297
298/**
299 * Initialize the HC: section 4.2
300 */
301int hc_start(xhci_hc_t *hc, bool irq)
302{
303 int err;
304
305 if ((err = hc_reset(hc)))
306 return err;
307
308 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
309 async_usleep(1000);
310
311 uint64_t dcbaaptr = addr_to_phys(hc->event_ring.erst);
312 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
313 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
314 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
315
316 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
317 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
318 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
319
320 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
321 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
322 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
323 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erstptr));
324 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erstptr));
325 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
326 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
327
328 // TODO: Setup scratchpad buffers
329
330 if (irq) {
331 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
332 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
333 }
334
335 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
336
337 return EOK;
338}
339
340int hc_status(xhci_hc_t *hc, uint32_t *status)
341{
342 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
343 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
344
345 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
346 return EOK;
347}
348
349int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
350{
351 xhci_dump_state(hc);
352 xhci_send_no_op_command(hc);
353 async_usleep(1000);
354 xhci_dump_state(hc);
355
356 xhci_dump_trb(hc->event_ring.dequeue_trb);
357 return EOK;
358}
359
360static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
361{
362 int err;
363 xhci_trb_t trb;
364
365 err = xhci_event_ring_dequeue(event_ring, &trb);;
366
367 switch (err) {
368 case EOK:
369 usb_log_debug2("Dequeued from event ring.");
370 xhci_dump_trb(&trb);
371 break;
372
373 case ENOENT:
374 usb_log_debug2("Event ring finished.");
375 break;
376
377 default:
378 usb_log_warning("Error while accessing event ring: %s", str_error(err));
379 }
380
381 /* Update the ERDP to make room in the ring */
382 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
383 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erstptr));
384 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erstptr));
385}
386
387void hc_interrupt(xhci_hc_t *hc, uint32_t status)
388{
389 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
390 usb_log_error("Host controller error occured. Bad things gonna happen...");
391 }
392
393 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
394 usb_log_debug2("Event interrupt.");
395
396 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
397
398 if (XHCI_REG_RD(intr0, XHCI_INTR_IP)) {
399 XHCI_REG_SET(intr0, XHCI_INTR_IP, 1);
400 hc_run_event_ring(hc, &hc->event_ring, intr0);
401 }
402 }
403
404 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
405 usb_log_error("Port change detected. Not implemented yet!");
406 }
407
408 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
409 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
410 }
411}
412
413static void hc_dcbaa_fini(xhci_hc_t *hc)
414{
415 xhci_scratchpad_free(hc);
416
417 /* Idx 0 already deallocated by xhci_scratchpad_free. */
418 for (unsigned i = 1; i < hc->max_slots + 1; ++i) {
419 if (hc->dcbaa[i] != NULL) {
420 free32(hc->dcbaa[i]);
421 hc->dcbaa[i] = NULL;
422 }
423 }
424
425 free32(hc->dcbaa);
426}
427
428void hc_fini(xhci_hc_t *hc)
429{
430 xhci_trb_ring_fini(&hc->command_ring);
431 xhci_event_ring_fini(&hc->event_ring);
432 hc_dcbaa_fini(hc);
433 pio_disable(hc->base, RNGSZ(hc->mmio_range));
434 usb_log_info("HC(%p): Finalized.", hc);
435}
436
437
438
439/**
440 * @}
441 */
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