source: mainline/uspace/drv/bus/usb/xhci/hc.c@ d0db4a0

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d0db4a0 was 41924f30, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

WIP usbhost refactoring

This commit replaces callbacks with more systematic virtual-like inheritance-like solution. Currently breaks build of HelenOS, but both xhci and usbhost are buildable. More refactoring follows…
  • Property mode set to 100644
File size: 17.1 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "commands.h"
45#include "transfers.h"
46#include "trb_ring.h"
47
48/**
49 * Default USB Speed ID mapping: Table 157
50 */
51#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
52#define PORT_SPEED(mjr, psie, psim) { \
53 .name = "USB ", \
54 .major = mjr, \
55 .minor = 0, \
56 .rx_bps = PSI_TO_BPS(psie, psim), \
57 .tx_bps = PSI_TO_BPS(psie, psim) \
58}
59static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 2, 12);
60static const xhci_port_speed_t ps_default_low = PORT_SPEED(2, 1, 1500);
61static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 2, 480);
62static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 3, 5);
63
64/**
65 * Walk the list of extended capabilities.
66 */
67static int hc_parse_ec(xhci_hc_t *hc)
68{
69 unsigned psic, major, minor;
70 xhci_sp_name_t name;
71
72 xhci_port_speed_t *speeds = hc->rh.speeds;
73
74 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
75 xhci_dump_extcap(ec);
76 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
77 case XHCI_EC_USB_LEGACY:
78 assert(hc->legsup == NULL);
79 hc->legsup = (xhci_legsup_t *) ec;
80 break;
81 case XHCI_EC_SUPPORTED_PROTOCOL:
82 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
83 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
84 minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
85 name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
86
87 if (name.packed != xhci_name_usb.packed) {
88 /**
89 * The detection of such protocol would work,
90 * but the rest of the implementation is made
91 * for the USB protocol only.
92 */
93 usb_log_error("Unknown protocol %.4s.", name.str);
94 return ENOTSUP;
95 }
96
97 // "Implied" speed
98 if (psic == 0) {
99 assert(minor == 0);
100
101 if (major == 2) {
102 speeds[1] = ps_default_full;
103 speeds[2] = ps_default_low;
104 speeds[3] = ps_default_high;
105 } else if (major == 3) {
106 speeds[4] = ps_default_super;
107 } else {
108 return EINVAL;
109 }
110
111 usb_log_debug2("Implied speed of USB %u.0 set up.", major);
112 } else {
113 for (unsigned i = 0; i < psic; i++) {
114 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
115 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
116 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
117 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
118 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
119
120 speeds[psiv].major = major;
121 speeds[psiv].minor = minor;
122 str_ncpy(speeds[psiv].name, 4, name.str, 4);
123
124 uint64_t bps = PSI_TO_BPS(psie, psim);
125
126 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
127 speeds[psiv].rx_bps = bps;
128 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
129 speeds[psiv].tx_bps = bps;
130 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, speeds[psiv].rx_bps, speeds[psiv].tx_bps);
131 }
132 }
133 }
134 }
135 }
136 return EOK;
137}
138
139int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
140{
141 int err;
142
143 if (hw_res->mem_ranges.count != 1) {
144 usb_log_error("Unexpected MMIO area, bailing out.");
145 return EINVAL;
146 }
147
148 hc->mmio_range = hw_res->mem_ranges.ranges[0];
149
150 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
151 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
152
153 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
154 return EOVERFLOW;
155
156 void *base;
157 if ((err = pio_enable_range(&hc->mmio_range, &base)))
158 return err;
159
160 hc->base = base;
161 hc->cap_regs = (xhci_cap_regs_t *) base;
162 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
163 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
164 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
165
166 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
167 if (xec_offset > 0)
168 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
169
170 usb_log_debug2("Initialized MMIO reg areas:");
171 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
172 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
173 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
174 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
175
176 xhci_dump_cap_regs(hc->cap_regs);
177
178 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
179 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
180
181 if ((err = hc_parse_ec(hc))) {
182 pio_disable(hc->base, RNGSZ(hc->mmio_range));
183 return err;
184 }
185
186 return EOK;
187}
188
189int hc_init_memory(xhci_hc_t *hc)
190{
191 int err;
192
193 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(uint64_t));
194 if (!hc->dcbaa)
195 return ENOMEM;
196
197 hc->dcbaa_virt = malloc((1 + hc->max_slots) * sizeof(xhci_virt_device_ctx_t));
198 if (!hc->dcbaa_virt) {
199 err = ENOMEM;
200 goto err_dcbaa;
201 }
202
203 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
204 goto err_dcbaa_virt;
205
206 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
207 goto err_cmd_ring;
208
209 if ((err = xhci_scratchpad_alloc(hc)))
210 goto err_event_ring;
211
212 if ((err = xhci_init_commands(hc)))
213 goto err_scratch;
214
215 if ((err = xhci_rh_init(&hc->rh, hc)))
216 goto err_cmd;
217
218 return EOK;
219
220err_cmd:
221 xhci_fini_commands(hc);
222err_scratch:
223 xhci_scratchpad_free(hc);
224err_event_ring:
225 xhci_event_ring_fini(&hc->event_ring);
226err_cmd_ring:
227 xhci_trb_ring_fini(&hc->command_ring);
228err_dcbaa_virt:
229 free32(hc->dcbaa_virt);
230err_dcbaa:
231 free32(hc->dcbaa);
232 return err;
233}
234
235/*
236 * Pseudocode:
237 * ip = read(intr[0].iman)
238 * if (ip) {
239 * status = read(usbsts)
240 * assert status
241 * assert ip
242 * accept (passing status)
243 * }
244 * decline
245 */
246static const irq_cmd_t irq_commands[] = {
247 {
248 .cmd = CMD_PIO_READ_32,
249 .dstarg = 3,
250 .addr = NULL /* intr[0].iman */
251 },
252 {
253 .cmd = CMD_AND,
254 .srcarg = 3,
255 .dstarg = 4,
256 .value = 0 /* host2xhci(32, 1) */
257 },
258 {
259 .cmd = CMD_PREDICATE,
260 .srcarg = 4,
261 .value = 5
262 },
263 {
264 .cmd = CMD_PIO_READ_32,
265 .dstarg = 1,
266 .addr = NULL /* usbsts */
267 },
268 {
269 .cmd = CMD_AND,
270 .srcarg = 1,
271 .dstarg = 2,
272 .value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
273 },
274 {
275 .cmd = CMD_PIO_WRITE_A_32,
276 .srcarg = 2,
277 .addr = NULL /* usbsts */
278 },
279 {
280 .cmd = CMD_PIO_WRITE_A_32,
281 .srcarg = 3,
282 .addr = NULL /* intr[0].iman */
283 },
284 {
285 .cmd = CMD_ACCEPT
286 },
287 {
288 .cmd = CMD_DECLINE
289 }
290};
291
292
293/**
294 * Generates code to accept interrupts. The xHCI is designed primarily for
295 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
296 * (except 0) are disabled.
297 */
298int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
299{
300 assert(code);
301 assert(hw_res);
302
303 if (hw_res->irqs.count != 1) {
304 usb_log_info("Unexpected HW resources to enable interrupts.");
305 return EINVAL;
306 }
307
308 code->ranges = malloc(sizeof(irq_pio_range_t));
309 if (code->ranges == NULL)
310 return ENOMEM;
311
312 code->cmds = malloc(sizeof(irq_commands));
313 if (code->cmds == NULL) {
314 free(code->ranges);
315 return ENOMEM;
316 }
317
318 code->rangecount = 1;
319 code->ranges[0] = (irq_pio_range_t) {
320 .base = RNGABS(hc->mmio_range),
321 .size = RNGSZ(hc->mmio_range),
322 };
323
324 code->cmdcount = ARRAY_SIZE(irq_commands);
325 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
326
327 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
328 void *usbsts = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) + offsetof(xhci_op_regs_t, usbsts);
329 code->cmds[0].addr = intr0_iman;
330 code->cmds[1].value = host2xhci(32, 1);
331 code->cmds[3].addr = usbsts;
332 code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
333 code->cmds[5].addr = usbsts;
334 code->cmds[6].addr = intr0_iman;
335
336 return hw_res->irqs.irqs[0];
337}
338
339int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
340{
341 /* No legacy support capability, the controller is solely for us */
342 if (!hc->legsup)
343 return EOK;
344
345 /* Section 4.22.1 */
346 /* TODO: Test this with USB3-aware BIOS */
347 usb_log_debug2("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
348 XHCI_REG_WR(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
349 for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
350 usb_log_debug2("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
351 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
352 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
353 if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
354 assert(XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1);
355 return EOK;
356 }
357 async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
358 }
359 usb_log_error("BIOS did not release XHCI legacy hold!\n");
360
361 return ENOTSUP;
362}
363
364static int hc_reset(xhci_hc_t *hc)
365{
366 /* Stop the HC: set R/S to 0 */
367 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
368
369 /* Wait 16 ms until the HC is halted */
370 async_usleep(16000);
371 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
372
373 /* Reset */
374 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
375
376 /* Wait until the reset is complete */
377 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
378 async_usleep(1000);
379
380 return EOK;
381}
382
383/**
384 * Initialize the HC: section 4.2
385 */
386int hc_start(xhci_hc_t *hc, bool irq)
387{
388 int err;
389
390 if ((err = hc_reset(hc)))
391 return err;
392
393 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
394 async_usleep(1000);
395
396 uint64_t dcbaaptr = addr_to_phys(hc->dcbaa);
397 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
398 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
399 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
400
401 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
402 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
403 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
404
405 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
406 uint64_t erdp = hc->event_ring.dequeue_ptr;
407 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
408 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
409 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
410 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
411 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
412 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
413
414 if (irq) {
415 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
416 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
417 }
418
419 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
420
421 return EOK;
422}
423
424/**
425 * Used only when polling. Shall supplement the irq_commands.
426 */
427int hc_status(xhci_hc_t *hc, uint32_t *status)
428{
429 int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
430 if (ip) {
431 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
432 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
433 XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
434
435 /* interrupt handler expects status from irq_commands, which is
436 * in xhci order. */
437 *status = host2xhci(32, *status);
438 }
439
440 usb_log_debug2("HC(%p): Polled status: %x", hc, *status);
441 return EOK;
442}
443
444int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
445{
446 assert(batch);
447
448 /* Check for root hub communication */
449 if (batch->ep->target.address == xhci_rh_get_address(&hc->rh)) {
450 usb_log_debug("XHCI root hub request.\n");
451 return xhci_rh_schedule(&hc->rh, batch);
452 }
453
454 usb_log_debug2("EP(%d:%d) started %s transfer of size %lu.",
455 batch->ep->target.address, batch->ep->target.endpoint,
456 usb_str_transfer_type(batch->ep->transfer_type),
457 batch->buffer_size);
458
459 if (!batch->ep->target.address) {
460 usb_log_error("Attempted to schedule transfer to address 0.");
461 return EINVAL;
462 }
463
464 switch (batch->ep->transfer_type) {
465 case USB_TRANSFER_CONTROL:
466 return xhci_schedule_control_transfer(hc, batch);
467 case USB_TRANSFER_ISOCHRONOUS:
468 /* TODO: Implement me. */
469 break;
470 case USB_TRANSFER_BULK:
471 return xhci_schedule_bulk_transfer(hc, batch);
472 case USB_TRANSFER_INTERRUPT:
473 /* TODO: Implement me. */
474 break;
475 }
476
477 return EOK;
478}
479
480typedef int (*event_handler) (xhci_hc_t *, xhci_trb_t *trb);
481
482static event_handler event_handlers [] = {
483 [XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
484 [XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT] = &xhci_handle_port_status_change_event,
485 [XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
486};
487
488static int hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb, xhci_interrupter_regs_t *intr)
489{
490 unsigned type = TRB_TYPE(*trb);
491 if (type >= ARRAY_SIZE(event_handlers) || !event_handlers[type])
492 return ENOTSUP;
493
494 return event_handlers[type](hc, trb);
495}
496
497static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
498{
499 int err;
500 ssize_t size = 16;
501 xhci_trb_t *queue = malloc(sizeof(xhci_trb_t) * size);
502 if (!queue) {
503 usb_log_error("Not enough memory to run the event ring.");
504 return;
505 }
506
507 xhci_trb_t *head = queue;
508
509 while ((err = xhci_event_ring_dequeue(event_ring, head)) != ENOENT) {
510 if (err != EOK) {
511 usb_log_warning("Error while accessing event ring: %s", str_error(err));
512 break;
513 }
514
515 usb_log_debug2("Dequeued trb from event ring: %s", xhci_trb_str_type(TRB_TYPE(*head)));
516 head++;
517
518 /* Expand the array if needed. */
519 if (head - queue >= size) {
520 size *= 2;
521 xhci_trb_t *new_queue = realloc(queue, size);
522 if (new_queue == NULL)
523 break; /* Will process only those TRBs we have memory for. */
524
525 head = new_queue + (head - queue);
526 }
527 }
528
529 /* Update the ERDP to make room in the ring. */
530 usb_log_debug2("Copying from ring finished, updating ERDP.");
531 hc->event_ring.dequeue_ptr = host2xhci(64, addr_to_phys(hc->event_ring.dequeue_trb));
532 uint64_t erdp = hc->event_ring.dequeue_ptr;
533 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
534 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
535 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
536
537 /* Handle all of the collected events if possible. */
538 if (head == queue)
539 usb_log_warning("No events to be handled!");
540
541 for (xhci_trb_t *tail = queue; tail != head; tail++) {
542 if ((err = hc_handle_event(hc, tail, intr)) != EOK) {
543 usb_log_error("Failed to handle event: %s", str_error(err));
544 }
545 }
546
547 free(queue);
548 usb_log_debug2("Event ring run finished.");
549}
550
551void hc_interrupt(xhci_hc_t *hc, uint32_t status)
552{
553 status = xhci2host(32, status);
554
555 /* TODO: Figure out how root hub interrupts work. */
556 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
557 usb_log_debug2("Root hub interrupt.");
558 xhci_rh_interrupt(&hc->rh);
559
560 status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
561 }
562
563 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
564 usb_log_error("Host controller error occured. Bad things gonna happen...");
565 status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
566 }
567
568 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
569 usb_log_debug2("Event interrupt, running the event ring.");
570 hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
571 status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
572 }
573
574 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
575 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
576 status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
577 }
578
579 if (status) {
580 usb_log_error("Non-zero status after interrupt handling (%08x) - missing something?", status);
581 }
582}
583
584static void hc_dcbaa_fini(xhci_hc_t *hc)
585{
586 xhci_trb_ring_t* trb_ring;
587 xhci_scratchpad_free(hc);
588
589 /* Idx 0 already deallocated by xhci_scratchpad_free. */
590 for (unsigned i = 1; i < hc->max_slots + 1; ++i) {
591 if (hc->dcbaa_virt[i].dev_ctx) {
592 free32(hc->dcbaa_virt[i].dev_ctx);
593 hc->dcbaa_virt[i].dev_ctx = NULL;
594 }
595
596 for (unsigned i = 0; i < XHCI_EP_COUNT; ++i) {
597 trb_ring = hc->dcbaa_virt[i].trs[i];
598 if (trb_ring) {
599 hc->dcbaa_virt[i].trs[i] = NULL;
600 xhci_trb_ring_fini(trb_ring);
601 free32(trb_ring);
602 }
603 }
604 }
605
606 free32(hc->dcbaa);
607 free32(hc->dcbaa_virt);
608}
609
610void hc_fini(xhci_hc_t *hc)
611{
612 xhci_trb_ring_fini(&hc->command_ring);
613 xhci_event_ring_fini(&hc->event_ring);
614 hc_dcbaa_fini(hc);
615 xhci_fini_commands(hc);
616 xhci_rh_fini(&hc->rh);
617 pio_disable(hc->base, RNGSZ(hc->mmio_range));
618 usb_log_info("HC(%p): Finalized.", hc);
619}
620
621int hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
622{
623 assert(hc);
624 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
625 pio_write_32(&hc->db_arry[doorbell], v);
626 return EOK;
627}
628
629/**
630 * @}
631 */
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