source: mainline/uspace/drv/bus/usb/xhci/hc.c@ c46c356

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c46c356 was c46c356, checked in by Jaroslav Jindrak <dzejrou@…>, 8 years ago

Added command list deallocation during hc finalization.
  • Property mode set to 100644
File size: 13.4 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "commands.h"
45
46static const irq_cmd_t irq_commands[] = {
47 {
48 .cmd = CMD_PIO_READ_32,
49 .dstarg = 1,
50 .addr = NULL
51 },
52 {
53 .cmd = CMD_AND,
54 .srcarg = 1,
55 .dstarg = 2,
56 .value = 0
57 },
58 {
59 .cmd = CMD_PREDICATE,
60 .srcarg = 2,
61 .value = 2
62 },
63 {
64 .cmd = CMD_PIO_WRITE_A_32,
65 .srcarg = 1,
66 .addr = NULL
67 },
68 {
69 .cmd = CMD_ACCEPT
70 }
71};
72
73/**
74 * Default USB Speed ID mapping: Table 157
75 */
76#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
77#define PORT_SPEED(psie, psim) { \
78 .rx_bps = PSI_TO_BPS(psie, psim), \
79 .tx_bps = PSI_TO_BPS(psie, psim) \
80}
81static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 12);
82static const xhci_port_speed_t ps_default_low = PORT_SPEED(1, 1500);
83static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 480);
84static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 5);
85
86/**
87 * Walk the list of extended capabilities.
88 */
89static int hc_parse_ec(xhci_hc_t *hc)
90{
91 unsigned psic, major;
92
93 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
94 xhci_dump_extcap(ec);
95 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
96 case XHCI_EC_USB_LEGACY:
97 assert(hc->legsup == NULL);
98 hc->legsup = (xhci_legsup_t *) ec;
99 break;
100 case XHCI_EC_SUPPORTED_PROTOCOL:
101 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
102 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
103
104 // "Implied" speed
105 if (psic == 0) {
106 /*
107 * According to section 7.2.2.1.2, only USB 2.0
108 * and USB 3.0 can have psic == 0. So we
109 * blindly assume the name == "USB " and minor
110 * == 0.
111 */
112 if (major == 2) {
113 hc->speeds[1] = ps_default_full;
114 hc->speeds[2] = ps_default_low;
115 hc->speeds[3] = ps_default_high;
116 } else if (major == 3) {
117 hc->speeds[4] = ps_default_super;
118 } else {
119 return EINVAL;
120 }
121
122 usb_log_debug2("Implied speed of USB %u set up.", major);
123 } else {
124 for (unsigned i = 0; i < psic; i++) {
125 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
126 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
127 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
128 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
129 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
130
131 uint64_t bps = PSI_TO_BPS(psie, psim);
132
133 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
134 hc->speeds[psiv].rx_bps = bps;
135 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
136 hc->speeds[psiv].tx_bps = bps;
137 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, hc->speeds[psiv].rx_bps, hc->speeds[psiv].tx_bps);
138 }
139 }
140 }
141 }
142 }
143 return EOK;
144}
145
146int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
147{
148 int err;
149
150 if (hw_res->mem_ranges.count != 1) {
151 usb_log_error("Unexpected MMIO area, bailing out.");
152 return EINVAL;
153 }
154
155 hc->mmio_range = hw_res->mem_ranges.ranges[0];
156
157 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
158 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
159
160 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
161 return EOVERFLOW;
162
163 void *base;
164 if ((err = pio_enable_range(&hc->mmio_range, &base)))
165 return err;
166
167 hc->base = base;
168 hc->cap_regs = (xhci_cap_regs_t *) base;
169 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
170 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
171 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
172
173 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
174 if (xec_offset > 0)
175 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
176
177 usb_log_debug2("Initialized MMIO reg areas:");
178 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
179 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
180 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
181 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
182
183 xhci_dump_cap_regs(hc->cap_regs);
184
185 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
186 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
187
188 if ((err = hc_parse_ec(hc))) {
189 pio_disable(hc->base, RNGSZ(hc->mmio_range));
190 return err;
191 }
192
193 return EOK;
194}
195
196int hc_init_memory(xhci_hc_t *hc)
197{
198 int err;
199
200 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(xhci_device_ctx_t*));
201 if (!hc->dcbaa)
202 return ENOMEM;
203
204 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
205 goto err_dcbaa;
206
207 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
208 goto err_cmd_ring;
209
210 if ((err = xhci_scratchpad_alloc(hc)))
211 goto err_event_ring;
212
213 if ((err = xhci_init_commands(hc)))
214 goto err_event_ring;
215
216 return EOK;
217
218err_event_ring:
219 xhci_event_ring_fini(&hc->event_ring);
220err_cmd_ring:
221 xhci_trb_ring_fini(&hc->command_ring);
222err_dcbaa:
223 free32(hc->dcbaa);
224 return err;
225}
226
227
228/**
229 * Generates code to accept interrupts. The xHCI is designed primarily for
230 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
231 * (except 0) are disabled.
232 */
233int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
234{
235 assert(code);
236 assert(hw_res);
237
238 if (hw_res->irqs.count != 1) {
239 usb_log_info("Unexpected HW resources to enable interrupts.");
240 return EINVAL;
241 }
242
243 code->ranges = malloc(sizeof(irq_pio_range_t));
244 if (code->ranges == NULL)
245 return ENOMEM;
246
247 code->cmds = malloc(sizeof(irq_commands));
248 if (code->cmds == NULL) {
249 free(code->ranges);
250 return ENOMEM;
251 }
252
253 code->rangecount = 1;
254 code->ranges[0] = (irq_pio_range_t) {
255 .base = RNGABS(hc->mmio_range),
256 .size = RNGSZ(hc->mmio_range),
257 };
258
259 code->cmdcount = ARRAY_SIZE(irq_commands);
260 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
261
262 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
263 code->cmds[0].addr = intr0_iman;
264 code->cmds[3].addr = intr0_iman;
265 code->cmds[1].value = host2xhci(32, 1);
266
267 return hw_res->irqs.irqs[0];
268}
269
270int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
271{
272 /* No legacy support capability, the controller is solely for us */
273 if (!hc->legsup)
274 return EOK;
275
276 /*
277 * TODO: Implement handoff from BIOS, section 4.22.1
278 * QEMU does not support this, so we have to test on real HW.
279 */
280 return ENOTSUP;
281}
282
283static int hc_reset(xhci_hc_t *hc)
284{
285 /* Stop the HC: set R/S to 0 */
286 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
287
288 /* Wait 16 ms until the HC is halted */
289 async_usleep(16000);
290 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
291
292 /* Reset */
293 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
294
295 /* Wait until the reset is complete */
296 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
297 async_usleep(1000);
298
299 return EOK;
300}
301
302/**
303 * Initialize the HC: section 4.2
304 */
305int hc_start(xhci_hc_t *hc, bool irq)
306{
307 int err;
308
309 if ((err = hc_reset(hc)))
310 return err;
311
312 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
313 async_usleep(1000);
314
315 uint64_t dcbaaptr = addr_to_phys(hc->dcbaa);
316 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
317 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
318 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
319
320 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
321 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
322 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
323
324 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
325 uint64_t erdp = hc->event_ring.dequeue_ptr;
326 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
327 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
328 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
329 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
330 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
331 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
332
333 // TODO: Setup scratchpad buffers
334
335 if (irq) {
336 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
337 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
338 }
339
340 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
341
342 return EOK;
343}
344
345int hc_status(xhci_hc_t *hc, uint32_t *status)
346{
347 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
348 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
349
350 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
351 return EOK;
352}
353
354int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
355{
356 // TODO: This function currently contains cmd ring testing
357 // stuff, remove it.
358 xhci_cmd_t *cmd = xhci_alloc_command();
359 xhci_dump_state(hc);
360 xhci_send_no_op_command(hc, cmd);
361 xhci_wait_for_command(cmd, 1000000);
362 xhci_free_command(cmd);
363
364 xhci_dump_state(hc);
365
366 for (int i = 0; i < 10; ++i) {
367 xhci_cmd_t *cmd2 = xhci_alloc_command();
368 xhci_send_enable_slot_command(hc, cmd2);
369 xhci_wait_for_command(cmd2, 1000000);
370 usb_log_error("Enabled slot ID: %u.", cmd2->slot_id);
371 xhci_free_command(cmd2);
372 }
373
374
375 xhci_dump_trb(hc->event_ring.dequeue_trb);
376 return EOK;
377}
378
379static void hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb)
380{
381 usb_log_debug2("TRB event encountered.");
382 switch (TRB_TYPE(*trb)) {
383 case XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT:
384 xhci_handle_command_completion(hc, trb);
385 break;
386 case XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT:
387 xhci_handle_port_status_change_event(hc, trb);
388 break;
389 default:
390 usb_log_debug2("Event type handling not implemented.");
391 break;
392 }
393}
394
395static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
396{
397 int err;
398 xhci_trb_t trb;
399
400 err = xhci_event_ring_dequeue(event_ring, &trb);;
401
402 while (err != ENOENT) {
403 if (err == EOK) {
404 usb_log_debug2("Dequeued from event ring.");
405 xhci_dump_trb(&trb);
406
407 hc_handle_event(hc, &trb);
408 } else {
409 usb_log_warning("Error while accessing event ring: %s", str_error(err));
410 break;
411 }
412
413 err = xhci_event_ring_dequeue(event_ring, &trb);;
414 }
415 usb_log_debug2("Event ring processing finished.");
416
417 /* Update the ERDP to make room in the ring */
418 hc->event_ring.dequeue_ptr = host2xhci(64, addr_to_phys(hc->event_ring.dequeue_trb));
419 uint64_t erdp = hc->event_ring.dequeue_ptr;
420 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
421 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
422 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
423}
424
425void hc_interrupt(xhci_hc_t *hc, uint32_t status)
426{
427 /**
428 * TODO: This is a temporary workaround, when an event interrupt
429 * happens, status has the value of 3, which is equal to
430 * XHCI_REG_SHIFT(XHCI_OP_EINT), intstead to the correct
431 * XHCI_REG_MASK(XHCI_OP_EINT), which has the value of 8 (1 << 3).
432 * This is how e.g. FreeBSD does it.
433 */
434 status = hc->op_regs->usbsts;
435
436 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
437 usb_log_error("Host controller error occured. Bad things gonna happen...");
438 }
439
440 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
441 usb_log_debug2("Event interrupt.");
442
443 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
444
445 /**
446 * EINT has to be cleared before IP, but we also need to
447 * handle the event before clearing EINT.
448 */
449 uint32_t ip = XHCI_REG_RD(intr0, XHCI_INTR_IP);
450
451 if (ip | 1) { // TODO: IP is being cleared right after it is set by the xHC.
452 hc_run_event_ring(hc, &hc->event_ring, intr0);
453 }
454
455 XHCI_REG_SET(hc->op_regs, XHCI_OP_EINT, 1);
456
457 if (ip) {
458 XHCI_REG_SET(intr0, XHCI_INTR_IP, 1);
459 }
460 }
461
462 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
463 usb_log_error("Port change detected. Not implemented yet!");
464 }
465
466 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
467 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
468 }
469}
470
471static void hc_dcbaa_fini(xhci_hc_t *hc)
472{
473 xhci_scratchpad_free(hc);
474
475 /* Idx 0 already deallocated by xhci_scratchpad_free. */
476 for (unsigned i = 1; i < hc->max_slots + 1; ++i) {
477 if (hc->dcbaa[i] != NULL) {
478 free32(hc->dcbaa[i]);
479 hc->dcbaa[i] = NULL;
480 }
481 }
482
483 free32(hc->dcbaa);
484}
485
486void hc_fini(xhci_hc_t *hc)
487{
488 xhci_trb_ring_fini(&hc->command_ring);
489 xhci_event_ring_fini(&hc->event_ring);
490 hc_dcbaa_fini(hc);
491 xhci_fini_commands(hc);
492 pio_disable(hc->base, RNGSZ(hc->mmio_range));
493 usb_log_info("HC(%p): Finalized.", hc);
494}
495
496
497
498/**
499 * @}
500 */
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