source: mainline/uspace/drv/bus/usb/xhci/hc.c@ c33c40e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c33c40e was c33c40e, checked in by Petr Manek <petr.manek@…>, 8 years ago

Fixed infinite loop bug. Support non-zero address for RH.
  • Property mode set to 100644
File size: 14.5 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "commands.h"
45
46static const irq_cmd_t irq_commands[] = {
47 {
48 .cmd = CMD_PIO_READ_32,
49 .dstarg = 1,
50 .addr = NULL
51 },
52 {
53 .cmd = CMD_AND,
54 .srcarg = 1,
55 .dstarg = 2,
56 .value = 0
57 },
58 {
59 .cmd = CMD_PREDICATE,
60 .srcarg = 2,
61 .value = 2
62 },
63 {
64 .cmd = CMD_PIO_WRITE_A_32,
65 .srcarg = 1,
66 .addr = NULL
67 },
68 {
69 .cmd = CMD_ACCEPT
70 }
71};
72
73/**
74 * Default USB Speed ID mapping: Table 157
75 */
76#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
77#define PORT_SPEED(psie, psim) { \
78 .rx_bps = PSI_TO_BPS(psie, psim), \
79 .tx_bps = PSI_TO_BPS(psie, psim) \
80}
81static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 12);
82static const xhci_port_speed_t ps_default_low = PORT_SPEED(1, 1500);
83static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 480);
84static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 5);
85
86/**
87 * Walk the list of extended capabilities.
88 */
89static int hc_parse_ec(xhci_hc_t *hc)
90{
91 unsigned psic, major;
92
93 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
94 xhci_dump_extcap(ec);
95 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
96 case XHCI_EC_USB_LEGACY:
97 assert(hc->legsup == NULL);
98 hc->legsup = (xhci_legsup_t *) ec;
99 break;
100 case XHCI_EC_SUPPORTED_PROTOCOL:
101 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
102 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
103
104 // "Implied" speed
105 if (psic == 0) {
106 /*
107 * According to section 7.2.2.1.2, only USB 2.0
108 * and USB 3.0 can have psic == 0. So we
109 * blindly assume the name == "USB " and minor
110 * == 0.
111 */
112 if (major == 2) {
113 hc->speeds[1] = ps_default_full;
114 hc->speeds[2] = ps_default_low;
115 hc->speeds[3] = ps_default_high;
116 } else if (major == 3) {
117 hc->speeds[4] = ps_default_super;
118 } else {
119 return EINVAL;
120 }
121
122 usb_log_debug2("Implied speed of USB %u set up.", major);
123 } else {
124 for (unsigned i = 0; i < psic; i++) {
125 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
126 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
127 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
128 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
129 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
130
131 uint64_t bps = PSI_TO_BPS(psie, psim);
132
133 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
134 hc->speeds[psiv].rx_bps = bps;
135 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
136 hc->speeds[psiv].tx_bps = bps;
137 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, hc->speeds[psiv].rx_bps, hc->speeds[psiv].tx_bps);
138 }
139 }
140 }
141 }
142 }
143 return EOK;
144}
145
146int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
147{
148 int err;
149
150 if (hw_res->mem_ranges.count != 1) {
151 usb_log_error("Unexpected MMIO area, bailing out.");
152 return EINVAL;
153 }
154
155 hc->mmio_range = hw_res->mem_ranges.ranges[0];
156
157 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
158 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
159
160 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
161 return EOVERFLOW;
162
163 void *base;
164 if ((err = pio_enable_range(&hc->mmio_range, &base)))
165 return err;
166
167 hc->base = base;
168 hc->cap_regs = (xhci_cap_regs_t *) base;
169 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
170 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
171 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
172
173 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
174 if (xec_offset > 0)
175 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
176
177 usb_log_debug2("Initialized MMIO reg areas:");
178 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
179 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
180 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
181 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
182
183 xhci_dump_cap_regs(hc->cap_regs);
184
185 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
186 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
187
188 if ((err = hc_parse_ec(hc))) {
189 pio_disable(hc->base, RNGSZ(hc->mmio_range));
190 return err;
191 }
192
193 return EOK;
194}
195
196int hc_init_memory(xhci_hc_t *hc)
197{
198 int err;
199
200 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(uint64_t));
201 if (!hc->dcbaa)
202 return ENOMEM;
203
204 hc->dcbaa_virt = malloc32((1 + hc->max_slots) * sizeof(xhci_device_ctx_t*));
205 if (!hc->dcbaa_virt) {
206 err = ENOMEM;
207 goto err_dcbaa;
208 }
209
210 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
211 goto err_dcbaa_virt;
212
213 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
214 goto err_cmd_ring;
215
216 if ((err = xhci_scratchpad_alloc(hc)))
217 goto err_event_ring;
218
219 if ((err = xhci_init_commands(hc)))
220 goto err_event_ring;
221
222 if ((err = xhci_rh_init(&hc->rh)))
223 goto err_rh;
224
225 return EOK;
226
227err_rh:
228 xhci_rh_fini(&hc->rh);
229err_event_ring:
230 xhci_event_ring_fini(&hc->event_ring);
231err_cmd_ring:
232 xhci_trb_ring_fini(&hc->command_ring);
233err_dcbaa_virt:
234 free32(hc->dcbaa_virt);
235err_dcbaa:
236 free32(hc->dcbaa);
237 return err;
238}
239
240
241/**
242 * Generates code to accept interrupts. The xHCI is designed primarily for
243 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
244 * (except 0) are disabled.
245 */
246int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
247{
248 assert(code);
249 assert(hw_res);
250
251 if (hw_res->irqs.count != 1) {
252 usb_log_info("Unexpected HW resources to enable interrupts.");
253 return EINVAL;
254 }
255
256 code->ranges = malloc(sizeof(irq_pio_range_t));
257 if (code->ranges == NULL)
258 return ENOMEM;
259
260 code->cmds = malloc(sizeof(irq_commands));
261 if (code->cmds == NULL) {
262 free(code->ranges);
263 return ENOMEM;
264 }
265
266 code->rangecount = 1;
267 code->ranges[0] = (irq_pio_range_t) {
268 .base = RNGABS(hc->mmio_range),
269 .size = RNGSZ(hc->mmio_range),
270 };
271
272 code->cmdcount = ARRAY_SIZE(irq_commands);
273 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
274
275 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
276 code->cmds[0].addr = intr0_iman;
277 code->cmds[3].addr = intr0_iman;
278 code->cmds[1].value = host2xhci(32, 1);
279
280 return hw_res->irqs.irqs[0];
281}
282
283int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
284{
285 /* No legacy support capability, the controller is solely for us */
286 if (!hc->legsup)
287 return EOK;
288
289 /*
290 * TODO: Implement handoff from BIOS, section 4.22.1
291 * QEMU does not support this, so we have to test on real HW.
292 */
293 return ENOTSUP;
294}
295
296static int hc_reset(xhci_hc_t *hc)
297{
298 /* Stop the HC: set R/S to 0 */
299 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
300
301 /* Wait 16 ms until the HC is halted */
302 async_usleep(16000);
303 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
304
305 /* Reset */
306 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
307
308 /* Wait until the reset is complete */
309 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
310 async_usleep(1000);
311
312 return EOK;
313}
314
315/**
316 * Initialize the HC: section 4.2
317 */
318int hc_start(xhci_hc_t *hc, bool irq)
319{
320 int err;
321
322 if ((err = hc_reset(hc)))
323 return err;
324
325 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
326 async_usleep(1000);
327
328 uint64_t dcbaaptr = addr_to_phys(hc->dcbaa);
329 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
330 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
331 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
332
333 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
334 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
335 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
336
337 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
338 uint64_t erdp = hc->event_ring.dequeue_ptr;
339 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
340 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
341 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
342 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
343 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
344 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
345
346 if (irq) {
347 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
348 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
349 }
350
351 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
352
353 return EOK;
354}
355
356int hc_status(xhci_hc_t *hc, uint32_t *status)
357{
358 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
359 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
360
361 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
362 return EOK;
363}
364
365int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
366{
367 assert(batch);
368
369 /* Check for root hub communication */
370 if (batch->ep->address == xhci_rh_get_address(&hc->rh)) {
371 usb_log_debug("XHCI root hub request.\n");
372 return xhci_rh_schedule(&hc->rh, batch);
373 }
374
375 usb_log_debug2("EP(%d:%d) started %s transfer of size %lu.",
376 batch->ep->address, batch->ep->endpoint,
377 usb_str_transfer_type(batch->ep->transfer_type),
378 batch->buffer_size);
379
380 switch (batch->ep->transfer_type) {
381 case USB_TRANSFER_CONTROL:
382 /* TODO: Send setup stage TRB. */
383 /* TODO: Optionally, send data stage TRB followed by zero or
384 more normal TRB's. */
385 /* TODO: Send status stage TRB. */
386 /* TODO: Ring the appropriate doorbell. */
387 break;
388 case USB_TRANSFER_ISOCHRONOUS:
389 /* TODO: Implement me. */
390 break;
391 case USB_TRANSFER_BULK:
392 /* TODO: Implement me. */
393 break;
394 case USB_TRANSFER_INTERRUPT:
395 /* TODO: Implement me. */
396 break;
397 }
398
399 return EOK;
400}
401
402static void hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb)
403{
404 usb_log_debug2("TRB event encountered.");
405 switch (TRB_TYPE(*trb)) {
406 case XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT:
407 xhci_handle_command_completion(hc, trb);
408 break;
409 case XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT:
410 xhci_handle_port_status_change_event(hc, trb);
411 break;
412 default:
413 usb_log_debug2("Event type handling not implemented.");
414 break;
415 }
416}
417
418static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
419{
420 int err;
421 xhci_trb_t trb;
422
423 err = xhci_event_ring_dequeue(event_ring, &trb);;
424
425 while (err != ENOENT) {
426 if (err == EOK) {
427 usb_log_debug2("Dequeued trb from event ring: %s",
428 xhci_trb_str_type(TRB_TYPE(trb)));
429
430 hc_handle_event(hc, &trb);
431 } else {
432 usb_log_warning("Error while accessing event ring: %s", str_error(err));
433 break;
434 }
435
436 err = xhci_event_ring_dequeue(event_ring, &trb);;
437 }
438 usb_log_debug2("Event ring processing finished.");
439
440 /* Update the ERDP to make room in the ring */
441 hc->event_ring.dequeue_ptr = host2xhci(64, addr_to_phys(hc->event_ring.dequeue_trb));
442 uint64_t erdp = hc->event_ring.dequeue_ptr;
443 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
444 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
445 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
446}
447
448void hc_interrupt(xhci_hc_t *hc, uint32_t status)
449{
450 /**
451 * TODO: This is a temporary workaround, when an event interrupt
452 * happens, status has the value of 3, which is equal to
453 * XHCI_REG_SHIFT(XHCI_OP_EINT), intstead to the correct
454 * XHCI_REG_MASK(XHCI_OP_EINT), which has the value of 8 (1 << 3).
455 * This is how e.g. FreeBSD does it.
456 */
457 status = hc->op_regs->usbsts;
458
459 /* TODO: Figure out how root hub interrupts work. */
460 if (status | XHCI_REG_MASK(XHCI_OP_PCD)) {
461 usb_log_debug2("Root hub interrupt.");
462 xhci_rh_interrupt(&hc->rh);
463 }
464
465 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
466 usb_log_error("Host controller error occured. Bad things gonna happen...");
467 }
468
469 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
470 usb_log_debug2("Event interrupt.");
471
472 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
473
474 /**
475 * EINT has to be cleared before IP, but we also need to
476 * handle the event before clearing EINT.
477 */
478 uint32_t ip = XHCI_REG_RD(intr0, XHCI_INTR_IP);
479
480 if (ip | 1) { // TODO: IP is being cleared right after it is set by the xHC.
481 hc_run_event_ring(hc, &hc->event_ring, intr0);
482 }
483
484 XHCI_REG_SET(hc->op_regs, XHCI_OP_EINT, 1);
485
486 if (ip) {
487 XHCI_REG_SET(intr0, XHCI_INTR_IP, 1);
488 }
489 }
490
491 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
492 usb_log_error("Port change detected. Not implemented yet!");
493 }
494
495 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
496 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
497 }
498}
499
500static void hc_dcbaa_fini(xhci_hc_t *hc)
501{
502 xhci_trb_ring_t* trb_ring;
503 xhci_scratchpad_free(hc);
504
505 /* Idx 0 already deallocated by xhci_scratchpad_free. */
506 for (unsigned i = 1; i < hc->max_slots + 1; ++i) {
507 if (hc->dcbaa_virt[i]) {
508 if (hc->dcbaa_virt[i]->dev_ctx)
509 free32(hc->dcbaa_virt[i]->dev_ctx);
510
511 for (unsigned i = 0; i < XHCI_EP_COUNT; ++i) {
512 trb_ring = hc->dcbaa_virt[i]->trs[i];
513 if (trb_ring) {
514 xhci_trb_ring_fini(trb_ring);
515 free32(trb_ring);
516 }
517 }
518
519 free32(hc->dcbaa_virt[i]);
520 hc->dcbaa_virt[i] = NULL;
521 }
522 }
523
524 free32(hc->dcbaa);
525 free32(hc->dcbaa_virt);
526}
527
528void hc_fini(xhci_hc_t *hc)
529{
530 xhci_trb_ring_fini(&hc->command_ring);
531 xhci_event_ring_fini(&hc->event_ring);
532 hc_dcbaa_fini(hc);
533 xhci_fini_commands(hc);
534 xhci_rh_fini(&hc->rh);
535 pio_disable(hc->base, RNGSZ(hc->mmio_range));
536 usb_log_info("HC(%p): Finalized.", hc);
537}
538
539
540
541/**
542 * @}
543 */
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