source: mainline/uspace/drv/bus/usb/xhci/hc.c@ ba2fc2c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ba2fc2c was 32fb6bce, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

usbhost: refactoring

This commit moves interrupt, status and schedule to bus
operations. Then the purpose of hcd_t is better defined, and split into
hc_driver_t and hc_device_t. hc_driver_t is used to wrap driver
implementation by the library (similar to how usb_driver_t is used to
wrap usb device drivers). hc_device_t is used as a parent for hc_t
inside drivers, and is allocated inside the DDF device node.

To support these changes, some local identifiers were renamed, some
functions were moved and/or renamed and their arguments changed. The
most notable one being hcd_send_batch → bus_device_send_batch.
  • Property mode set to 100644
File size: 21.8 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/endpoint.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "hw_struct/context.h"
45#include "endpoint.h"
46#include "transfers.h"
47#include "trb_ring.h"
48
49/**
50 * Default USB Speed ID mapping: Table 157
51 */
52#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53#define PORT_SPEED(usb, mjr, psie, psim) { \
54 .name = "USB ", \
55 .major = mjr, \
56 .minor = 0, \
57 .usb_speed = USB_SPEED_##usb, \
58 .rx_bps = PSI_TO_BPS(psie, psim), \
59 .tx_bps = PSI_TO_BPS(psie, psim) \
60}
61static const xhci_port_speed_t ps_default_full = PORT_SPEED(FULL, 2, 2, 12);
62static const xhci_port_speed_t ps_default_low = PORT_SPEED(LOW, 2, 1, 1500);
63static const xhci_port_speed_t ps_default_high = PORT_SPEED(HIGH, 2, 2, 480);
64static const xhci_port_speed_t ps_default_super = PORT_SPEED(SUPER, 3, 3, 5);
65
66/**
67 * Walk the list of extended capabilities.
68 */
69static int hc_parse_ec(xhci_hc_t *hc)
70{
71 unsigned psic, major, minor;
72 xhci_sp_name_t name;
73
74 xhci_port_speed_t *speeds = hc->speeds;
75
76 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
77 xhci_dump_extcap(ec);
78 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
79 case XHCI_EC_USB_LEGACY:
80 assert(hc->legsup == NULL);
81 hc->legsup = (xhci_legsup_t *) ec;
82 break;
83 case XHCI_EC_SUPPORTED_PROTOCOL:
84 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
85 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
86 minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
87 name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
88
89 if (name.packed != xhci_name_usb.packed) {
90 /**
91 * The detection of such protocol would work,
92 * but the rest of the implementation is made
93 * for the USB protocol only.
94 */
95 usb_log_error("Unknown protocol %.4s.", name.str);
96 return ENOTSUP;
97 }
98
99 // "Implied" speed
100 if (psic == 0) {
101 assert(minor == 0);
102
103 if (major == 2) {
104 speeds[1] = ps_default_full;
105 speeds[2] = ps_default_low;
106 speeds[3] = ps_default_high;
107
108 hc->speed_to_psiv[USB_SPEED_FULL] = 1;
109 hc->speed_to_psiv[USB_SPEED_LOW] = 2;
110 hc->speed_to_psiv[USB_SPEED_HIGH] = 3;
111 } else if (major == 3) {
112 speeds[4] = ps_default_super;
113 hc->speed_to_psiv[USB_SPEED_SUPER] = 4;
114 } else {
115 return EINVAL;
116 }
117
118 usb_log_debug2("Implied speed of USB %u.0 set up.", major);
119 } else {
120 for (unsigned i = 0; i < psic; i++) {
121 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
122 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
123 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
124 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
125 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
126
127 speeds[psiv].major = major;
128 speeds[psiv].minor = minor;
129 str_ncpy(speeds[psiv].name, 4, name.str, 4);
130 speeds[psiv].usb_speed = USB_SPEED_MAX;
131
132 uint64_t bps = PSI_TO_BPS(psie, psim);
133
134 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
135 speeds[psiv].rx_bps = bps;
136 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
137 speeds[psiv].tx_bps = bps;
138 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, speeds[psiv].rx_bps, speeds[psiv].tx_bps);
139 }
140 }
141 }
142 }
143 }
144 return EOK;
145}
146
147int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
148{
149 int err;
150
151 if (hw_res->mem_ranges.count != 1) {
152 usb_log_error("Unexpected MMIO area, bailing out.");
153 return EINVAL;
154 }
155
156 hc->mmio_range = hw_res->mem_ranges.ranges[0];
157
158 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
159 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
160
161 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
162 return EOVERFLOW;
163
164 void *base;
165 if ((err = pio_enable_range(&hc->mmio_range, &base)))
166 return err;
167
168 hc->reg_base = base;
169 hc->cap_regs = (xhci_cap_regs_t *) base;
170 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
171 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
172 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
173
174 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
175 if (xec_offset > 0)
176 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
177
178 usb_log_debug2("Initialized MMIO reg areas:");
179 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
180 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
181 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
182 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
183
184 xhci_dump_cap_regs(hc->cap_regs);
185
186 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
187 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
188
189 if ((err = hc_parse_ec(hc))) {
190 pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
191 return err;
192 }
193
194 return EOK;
195}
196
197int hc_init_memory(xhci_hc_t *hc, ddf_dev_t *device)
198{
199 int err;
200
201 if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
202 return ENOMEM;
203 hc->dcbaa = hc->dcbaa_dma.virt;
204
205 if ((err = xhci_event_ring_init(&hc->event_ring)))
206 goto err_dcbaa;
207
208 if ((err = xhci_scratchpad_alloc(hc)))
209 goto err_event_ring;
210
211 if ((err = xhci_init_commands(hc)))
212 goto err_scratch;
213
214 if ((err = xhci_bus_init(&hc->bus, hc)))
215 goto err_cmd;
216
217 if ((err = xhci_rh_init(&hc->rh, hc, device)))
218 goto err_bus;
219
220 return EOK;
221
222err_bus:
223 xhci_bus_fini(&hc->bus);
224err_cmd:
225 xhci_fini_commands(hc);
226err_scratch:
227 xhci_scratchpad_free(hc);
228err_event_ring:
229 xhci_event_ring_fini(&hc->event_ring);
230err_dcbaa:
231 hc->dcbaa = NULL;
232 dma_buffer_free(&hc->dcbaa_dma);
233 return err;
234}
235
236/*
237 * Pseudocode:
238 * ip = read(intr[0].iman)
239 * if (ip) {
240 * status = read(usbsts)
241 * assert status
242 * assert ip
243 * accept (passing status)
244 * }
245 * decline
246 */
247static const irq_cmd_t irq_commands[] = {
248 {
249 .cmd = CMD_PIO_READ_32,
250 .dstarg = 3,
251 .addr = NULL /* intr[0].iman */
252 },
253 {
254 .cmd = CMD_AND,
255 .srcarg = 3,
256 .dstarg = 4,
257 .value = 0 /* host2xhci(32, 1) */
258 },
259 {
260 .cmd = CMD_PREDICATE,
261 .srcarg = 4,
262 .value = 5
263 },
264 {
265 .cmd = CMD_PIO_READ_32,
266 .dstarg = 1,
267 .addr = NULL /* usbsts */
268 },
269 {
270 .cmd = CMD_AND,
271 .srcarg = 1,
272 .dstarg = 2,
273 .value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
274 },
275 {
276 .cmd = CMD_PIO_WRITE_A_32,
277 .srcarg = 2,
278 .addr = NULL /* usbsts */
279 },
280 {
281 .cmd = CMD_PIO_WRITE_A_32,
282 .srcarg = 3,
283 .addr = NULL /* intr[0].iman */
284 },
285 {
286 .cmd = CMD_ACCEPT
287 },
288 {
289 .cmd = CMD_DECLINE
290 }
291};
292
293
294/**
295 * Generates code to accept interrupts. The xHCI is designed primarily for
296 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
297 * (except 0) are disabled.
298 */
299int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
300{
301 assert(code);
302 assert(hw_res);
303
304 if (hw_res->irqs.count != 1) {
305 usb_log_info("Unexpected HW resources to enable interrupts.");
306 return EINVAL;
307 }
308
309 code->ranges = malloc(sizeof(irq_pio_range_t));
310 if (code->ranges == NULL)
311 return ENOMEM;
312
313 code->cmds = malloc(sizeof(irq_commands));
314 if (code->cmds == NULL) {
315 free(code->ranges);
316 return ENOMEM;
317 }
318
319 code->rangecount = 1;
320 code->ranges[0] = (irq_pio_range_t) {
321 .base = RNGABS(hc->mmio_range),
322 .size = RNGSZ(hc->mmio_range),
323 };
324
325 code->cmdcount = ARRAY_SIZE(irq_commands);
326 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
327
328 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
329 void *usbsts = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) + offsetof(xhci_op_regs_t, usbsts);
330 code->cmds[0].addr = intr0_iman;
331 code->cmds[1].value = host2xhci(32, 1);
332 code->cmds[3].addr = usbsts;
333 code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
334 code->cmds[5].addr = usbsts;
335 code->cmds[6].addr = intr0_iman;
336
337 return hw_res->irqs.irqs[0];
338}
339
340int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
341{
342 /* No legacy support capability, the controller is solely for us */
343 if (!hc->legsup)
344 return EOK;
345
346 /* Section 4.22.1 */
347 /* TODO: Test this with USB3-aware BIOS */
348 usb_log_debug2("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
349 XHCI_REG_WR(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
350 for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
351 usb_log_debug2("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
352 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
353 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
354 if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
355 assert(XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1);
356 return EOK;
357 }
358 async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
359 }
360 usb_log_error("BIOS did not release XHCI legacy hold!\n");
361
362 return ENOTSUP;
363}
364
365static int hc_reset(xhci_hc_t *hc)
366{
367 /* Stop the HC: set R/S to 0 */
368 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
369
370 /* Wait 16 ms until the HC is halted */
371 async_usleep(16000);
372 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
373
374 /* Reset */
375 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
376
377 /* Wait until the reset is complete */
378 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
379 async_usleep(1000);
380
381 return EOK;
382}
383
384/**
385 * Initialize the HC: section 4.2
386 */
387int hc_start(xhci_hc_t *hc, bool irq)
388{
389 int err;
390
391 if ((err = hc_reset(hc)))
392 return err;
393
394 // FIXME: Waiting forever.
395 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
396 async_usleep(1000);
397
398 uint64_t dcbaaptr = hc->dcbaa_dma.phys;
399 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
400 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
401 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
402
403 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->cr.trb_ring);
404 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
405 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
406
407 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
408 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
409 uint64_t erdp = hc->event_ring.dequeue_ptr;
410 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
411 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
412 uint64_t erstptr = hc->event_ring.erst.phys;
413 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
414 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
415
416 if (irq) {
417 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
418 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
419 }
420
421 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
422
423 /* The reset changed status of all ports, and SW originated reason does
424 * not cause an interrupt.
425 */
426 xhci_rh_handle_port_change(&hc->rh);
427
428 return EOK;
429}
430
431/**
432 * Used only when polling. Shall supplement the irq_commands.
433 */
434int hc_status(bus_t *bus, uint32_t *status)
435{
436 xhci_hc_t *hc = bus_to_hc(bus);
437 int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
438 if (ip) {
439 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
440 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
441 XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
442
443 /* interrupt handler expects status from irq_commands, which is
444 * in xhci order. */
445 *status = host2xhci(32, *status);
446 }
447
448 usb_log_debug2("HC(%p): Polled status: %x", hc, *status);
449 return EOK;
450}
451
452int hc_schedule(usb_transfer_batch_t *batch)
453{
454 assert(batch);
455 xhci_hc_t *hc = bus_to_hc(endpoint_get_bus(batch->ep));
456
457 if (!batch->target.address) {
458 usb_log_error("Attempted to schedule transfer to address 0.");
459 return EINVAL;
460 }
461
462 return xhci_transfer_schedule(hc, batch);
463}
464
465typedef int (*event_handler) (xhci_hc_t *, xhci_trb_t *trb);
466
467static event_handler event_handlers [] = {
468 [XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
469 [XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT] = &xhci_rh_handle_port_status_change_event,
470 [XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
471};
472
473static int hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb, xhci_interrupter_regs_t *intr)
474{
475 unsigned type = TRB_TYPE(*trb);
476 if (type >= ARRAY_SIZE(event_handlers) || !event_handlers[type])
477 return ENOTSUP;
478
479 return event_handlers[type](hc, trb);
480}
481
482static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
483{
484 int err;
485 ssize_t size = 16;
486 xhci_trb_t *queue = malloc(sizeof(xhci_trb_t) * size);
487 if (!queue) {
488 usb_log_error("Not enough memory to run the event ring.");
489 return;
490 }
491
492 xhci_trb_t *head = queue;
493
494 while ((err = xhci_event_ring_dequeue(event_ring, head)) != ENOENT) {
495 if (err != EOK) {
496 usb_log_warning("Error while accessing event ring: %s", str_error(err));
497 break;
498 }
499
500 usb_log_debug2("Dequeued trb from event ring: %s", xhci_trb_str_type(TRB_TYPE(*head)));
501 head++;
502
503 /* Expand the array if needed. */
504 if (head - queue >= size) {
505 size *= 2;
506 xhci_trb_t *new_queue = realloc(queue, size);
507 if (new_queue == NULL)
508 break; /* Will process only those TRBs we have memory for. */
509
510 head = new_queue + (head - queue);
511 }
512 }
513
514 /* Update the ERDP to make room in the ring. */
515 usb_log_debug2("Copying from ring finished, updating ERDP.");
516 uint64_t erdp = hc->event_ring.dequeue_ptr;
517 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
518 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
519 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
520
521 /* Handle all of the collected events if possible. */
522 if (head == queue)
523 usb_log_warning("No events to be handled!");
524
525 for (xhci_trb_t *tail = queue; tail != head; tail++) {
526 if ((err = hc_handle_event(hc, tail, intr)) != EOK) {
527 usb_log_error("Failed to handle event: %s", str_error(err));
528 }
529 }
530
531 free(queue);
532 usb_log_debug2("Event ring run finished.");
533}
534
535void hc_interrupt(bus_t *bus, uint32_t status)
536{
537 xhci_hc_t *hc = bus_to_hc(bus);
538 status = xhci2host(32, status);
539
540 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
541 usb_log_debug2("Root hub interrupt.");
542 xhci_rh_handle_port_change(&hc->rh);
543 status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
544 }
545
546 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
547 usb_log_error("Host controller error occured. Bad things gonna happen...");
548 status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
549 }
550
551 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
552 usb_log_debug2("Event interrupt, running the event ring.");
553 hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
554 status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
555 }
556
557 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
558 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
559 status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
560 }
561
562 if (status) {
563 usb_log_error("Non-zero status after interrupt handling (%08x) - missing something?", status);
564 }
565}
566
567static void hc_dcbaa_fini(xhci_hc_t *hc)
568{
569 xhci_scratchpad_free(hc);
570 dma_buffer_free(&hc->dcbaa_dma);
571}
572
573void hc_fini(xhci_hc_t *hc)
574{
575 xhci_bus_fini(&hc->bus);
576 xhci_event_ring_fini(&hc->event_ring);
577 hc_dcbaa_fini(hc);
578 xhci_fini_commands(hc);
579 xhci_rh_fini(&hc->rh);
580 pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
581 usb_log_info("HC(%p): Finalized.", hc);
582}
583
584int hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
585{
586 assert(hc);
587 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
588 pio_write_32(&hc->db_arry[doorbell], v);
589 usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
590 return EOK;
591}
592
593int hc_enable_slot(xhci_hc_t *hc, uint32_t *slot_id)
594{
595 assert(hc);
596
597 int err;
598 xhci_cmd_t cmd;
599 xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
600
601 if ((err = xhci_cmd_sync(hc, &cmd))) {
602 goto end;
603 }
604
605 if (slot_id) {
606 *slot_id = cmd.slot_id;
607 }
608
609end:
610 xhci_cmd_fini(&cmd);
611 return err;
612}
613
614int hc_disable_slot(xhci_hc_t *hc, xhci_device_t *dev)
615{
616 int err;
617 assert(hc);
618
619 if ((err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = dev->slot_id))) {
620 return err;
621 }
622
623 /* Free the device context. */
624 hc->dcbaa[dev->slot_id] = 0;
625 dma_buffer_free(&dev->dev_ctx);
626
627 /* Mark the slot as invalid. */
628 dev->slot_id = 0;
629
630 return EOK;
631}
632
633static int create_configure_ep_input_ctx(dma_buffer_t *dma_buf)
634{
635 const int err = dma_buffer_alloc(dma_buf, sizeof(xhci_input_ctx_t));
636 if (err)
637 return err;
638
639 xhci_input_ctx_t *ictx = dma_buf->virt;
640 memset(ictx, 0, sizeof(xhci_input_ctx_t));
641
642 // Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
643 XHCI_INPUT_CTRL_CTX_ADD_SET(ictx->ctrl_ctx, 0);
644
645 return EOK;
646}
647
648int hc_address_device(xhci_hc_t *hc, xhci_device_t *dev, xhci_endpoint_t *ep0)
649{
650 int err = ENOMEM;
651
652 /* Although we have the precise PSIV value on devices of tier 1,
653 * we have to rely on reverse mapping on others. */
654 if (!hc->speed_to_psiv[dev->base.speed]) {
655 usb_log_error("Device reported an USB speed that cannot be mapped to HC port speed.");
656 return EINVAL;
657 }
658
659 /* Setup and register device context */
660 if (dma_buffer_alloc(&dev->dev_ctx, sizeof(xhci_device_ctx_t)))
661 goto err;
662 memset(dev->dev_ctx.virt, 0, sizeof(xhci_device_ctx_t));
663
664 hc->dcbaa[dev->slot_id] = host2xhci(64, dev->dev_ctx.phys);
665
666 /* Issue configure endpoint command (sec 4.3.5). */
667 dma_buffer_t ictx_dma_buf;
668 if ((err = create_configure_ep_input_ctx(&ictx_dma_buf))) {
669 goto err_dev_ctx;
670 }
671 xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
672
673 /* Initialize slot_ctx according to section 4.3.3 point 3. */
674 XHCI_SLOT_ROOT_HUB_PORT_SET(ictx->slot_ctx, dev->rh_port);
675 XHCI_SLOT_CTX_ENTRIES_SET(ictx->slot_ctx, 1);
676 XHCI_SLOT_ROUTE_STRING_SET(ictx->slot_ctx, dev->route_str);
677 XHCI_SLOT_SPEED_SET(ictx->slot_ctx, hc->speed_to_psiv[dev->base.speed]);
678
679 /* In a very specific case, we have to set also these. But before that,
680 * we need to refactor how TT is handled in libusbhost. */
681 XHCI_SLOT_TT_HUB_SLOT_ID_SET(ictx->slot_ctx, 0);
682 XHCI_SLOT_TT_HUB_PORT_SET(ictx->slot_ctx, 0);
683 XHCI_SLOT_MTT_SET(ictx->slot_ctx, 0);
684
685 /* Copy endpoint 0 context and set A1 flag. */
686 XHCI_INPUT_CTRL_CTX_ADD_SET(ictx->ctrl_ctx, 1);
687 xhci_setup_endpoint_context(ep0, &ictx->endpoint_ctx[0]);
688
689 /* Issue Address Device command. */
690 if ((err = xhci_cmd_sync_inline(hc, ADDRESS_DEVICE, .slot_id = dev->slot_id, .input_ctx = ictx_dma_buf))) {
691 goto err_dev_ctx;
692 }
693
694 xhci_device_ctx_t *dev_ctx = dev->dev_ctx.virt;
695 dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(dev_ctx->slot_ctx);
696 usb_log_debug2("Obtained USB address: %d.\n", dev->base.address);
697
698 /* From now on, the device is officially online, yay! */
699 fibril_mutex_lock(&dev->base.guard);
700 dev->online = true;
701 fibril_mutex_unlock(&dev->base.guard);
702
703 return EOK;
704
705err_dev_ctx:
706 hc->dcbaa[dev->slot_id] = 0;
707 dma_buffer_free(&dev->dev_ctx);
708err:
709 return err;
710}
711
712int hc_configure_device(xhci_hc_t *hc, uint32_t slot_id)
713{
714 /* Issue configure endpoint command (sec 4.3.5). */
715 dma_buffer_t ictx_dma_buf;
716 const int err = create_configure_ep_input_ctx(&ictx_dma_buf);
717 if (err)
718 return err;
719
720 // TODO: Set slot context and other flags. (probably forgot a lot of 'em)
721
722 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, .slot_id = slot_id, .input_ctx = ictx_dma_buf);
723}
724
725int hc_deconfigure_device(xhci_hc_t *hc, uint32_t slot_id)
726{
727 /* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
728 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, .slot_id = slot_id, .deconfigure = true);
729}
730
731int hc_add_endpoint(xhci_hc_t *hc, uint32_t slot_id, uint8_t ep_idx, xhci_ep_ctx_t *ep_ctx)
732{
733 /* Issue configure endpoint command (sec 4.3.5). */
734 dma_buffer_t ictx_dma_buf;
735 const int err = create_configure_ep_input_ctx(&ictx_dma_buf);
736 if (err)
737 return err;
738
739 xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
740 XHCI_INPUT_CTRL_CTX_ADD_SET(ictx->ctrl_ctx, ep_idx + 1); /* Preceded by slot ctx */
741 memcpy(&ictx->endpoint_ctx[ep_idx], ep_ctx, sizeof(xhci_ep_ctx_t));
742 // TODO: Set slot context and other flags. (probably forgot a lot of 'em)
743
744 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, .slot_id = slot_id, .input_ctx = ictx_dma_buf);
745}
746
747int hc_drop_endpoint(xhci_hc_t *hc, uint32_t slot_id, uint8_t ep_idx)
748{
749 /* Issue configure endpoint command (sec 4.3.5). */
750 dma_buffer_t ictx_dma_buf;
751 const int err = create_configure_ep_input_ctx(&ictx_dma_buf);
752 if (err)
753 return err;
754
755 xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
756 XHCI_INPUT_CTRL_CTX_DROP_SET(ictx->ctrl_ctx, ep_idx + 1); /* Preceded by slot ctx */
757 // TODO: Set slot context and other flags. (probably forgot a lot of 'em)
758
759 return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, .slot_id = slot_id, .input_ctx = ictx_dma_buf);
760}
761
762int hc_update_endpoint(xhci_hc_t *hc, uint32_t slot_id, uint8_t ep_idx, xhci_ep_ctx_t *ep_ctx)
763{
764 dma_buffer_t ictx_dma_buf;
765 const int err = dma_buffer_alloc(&ictx_dma_buf, sizeof(xhci_input_ctx_t));
766 if (err)
767 return err;
768
769 xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
770 memset(ictx, 0, sizeof(xhci_input_ctx_t));
771
772 XHCI_INPUT_CTRL_CTX_ADD_SET(ictx->ctrl_ctx, ep_idx + 1);
773 memcpy(&ictx->endpoint_ctx[ep_idx], ep_ctx, sizeof(xhci_ep_ctx_t));
774
775 return xhci_cmd_sync_inline(hc, EVALUATE_CONTEXT, .slot_id = slot_id, .input_ctx = ictx_dma_buf);
776}
777
778/**
779 * @}
780 */
Note: See TracBrowser for help on using the repository browser.