source: mainline/uspace/drv/bus/usb/xhci/hc.c@ ab5a0830

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ab5a0830 was ab5a0830, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

Handle interrupts correctly

Now, irq_commands asserts all flags in usbsts, then asserts IP, and passes
usbsts as status to the handler. The previous weird behavior was becouse
status_hook is only called when in polling mode, which we didn't notice.
  • Property mode set to 100644
File size: 15.5 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "commands.h"
45
46/**
47 * Default USB Speed ID mapping: Table 157
48 */
49#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
50#define PORT_SPEED(psie, psim) { \
51 .rx_bps = PSI_TO_BPS(psie, psim), \
52 .tx_bps = PSI_TO_BPS(psie, psim) \
53}
54static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 12);
55static const xhci_port_speed_t ps_default_low = PORT_SPEED(1, 1500);
56static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 480);
57static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 5);
58
59/**
60 * Walk the list of extended capabilities.
61 */
62static int hc_parse_ec(xhci_hc_t *hc)
63{
64 unsigned psic, major;
65
66 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
67 xhci_dump_extcap(ec);
68 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
69 case XHCI_EC_USB_LEGACY:
70 assert(hc->legsup == NULL);
71 hc->legsup = (xhci_legsup_t *) ec;
72 break;
73 case XHCI_EC_SUPPORTED_PROTOCOL:
74 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
75 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
76
77 // "Implied" speed
78 if (psic == 0) {
79 /*
80 * According to section 7.2.2.1.2, only USB 2.0
81 * and USB 3.0 can have psic == 0. So we
82 * blindly assume the name == "USB " and minor
83 * == 0.
84 */
85 if (major == 2) {
86 hc->speeds[1] = ps_default_full;
87 hc->speeds[2] = ps_default_low;
88 hc->speeds[3] = ps_default_high;
89 } else if (major == 3) {
90 hc->speeds[4] = ps_default_super;
91 } else {
92 return EINVAL;
93 }
94
95 usb_log_debug2("Implied speed of USB %u set up.", major);
96 } else {
97 for (unsigned i = 0; i < psic; i++) {
98 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
99 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
100 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
101 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
102 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
103
104 uint64_t bps = PSI_TO_BPS(psie, psim);
105
106 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
107 hc->speeds[psiv].rx_bps = bps;
108 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
109 hc->speeds[psiv].tx_bps = bps;
110 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, hc->speeds[psiv].rx_bps, hc->speeds[psiv].tx_bps);
111 }
112 }
113 }
114 }
115 }
116 return EOK;
117}
118
119int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
120{
121 int err;
122
123 if (hw_res->mem_ranges.count != 1) {
124 usb_log_error("Unexpected MMIO area, bailing out.");
125 return EINVAL;
126 }
127
128 hc->mmio_range = hw_res->mem_ranges.ranges[0];
129
130 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
131 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
132
133 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
134 return EOVERFLOW;
135
136 void *base;
137 if ((err = pio_enable_range(&hc->mmio_range, &base)))
138 return err;
139
140 hc->base = base;
141 hc->cap_regs = (xhci_cap_regs_t *) base;
142 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
143 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
144 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
145
146 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
147 if (xec_offset > 0)
148 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
149
150 usb_log_debug2("Initialized MMIO reg areas:");
151 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
152 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
153 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
154 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
155
156 xhci_dump_cap_regs(hc->cap_regs);
157
158 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
159 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
160
161 if ((err = hc_parse_ec(hc))) {
162 pio_disable(hc->base, RNGSZ(hc->mmio_range));
163 return err;
164 }
165
166 return EOK;
167}
168
169int hc_init_memory(xhci_hc_t *hc)
170{
171 int err;
172
173 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(uint64_t));
174 if (!hc->dcbaa)
175 return ENOMEM;
176
177 hc->dcbaa_virt = malloc32((1 + hc->max_slots) * sizeof(xhci_virt_device_ctx_t));
178 if (!hc->dcbaa_virt) {
179 err = ENOMEM;
180 goto err_dcbaa;
181 }
182
183 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
184 goto err_dcbaa_virt;
185
186 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
187 goto err_cmd_ring;
188
189 if ((err = xhci_scratchpad_alloc(hc)))
190 goto err_event_ring;
191
192 if ((err = xhci_init_commands(hc)))
193 goto err_scratch;
194
195 if ((err = xhci_rh_init(&hc->rh)))
196 goto err_cmd;
197
198 return EOK;
199
200err_cmd:
201 xhci_fini_commands(hc);
202err_scratch:
203 xhci_scratchpad_free(hc);
204err_event_ring:
205 xhci_event_ring_fini(&hc->event_ring);
206err_cmd_ring:
207 xhci_trb_ring_fini(&hc->command_ring);
208err_dcbaa_virt:
209 free32(hc->dcbaa_virt);
210err_dcbaa:
211 free32(hc->dcbaa);
212 return err;
213}
214
215/*
216 * Pseudocode:
217 * ip = read(intr[0].iman)
218 * if (ip) {
219 * status = read(usbsts)
220 * assert status
221 * assert ip
222 * accept (passing status)
223 * }
224 * decline
225 */
226static const irq_cmd_t irq_commands[] = {
227 {
228 .cmd = CMD_PIO_READ_32,
229 .dstarg = 3,
230 .addr = NULL /* intr[0].iman */
231 },
232 {
233 .cmd = CMD_AND,
234 .srcarg = 3,
235 .dstarg = 4,
236 .value = 0 /* host2xhci(32, 1) */
237 },
238 {
239 .cmd = CMD_PREDICATE,
240 .srcarg = 4,
241 .value = 5
242 },
243 {
244 .cmd = CMD_PIO_READ_32,
245 .dstarg = 1,
246 .addr = NULL /* usbsts */
247 },
248 {
249 .cmd = CMD_AND,
250 .srcarg = 1,
251 .dstarg = 2,
252 .value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
253 },
254 {
255 .cmd = CMD_PIO_WRITE_A_32,
256 .srcarg = 2,
257 .addr = NULL /* usbsts */
258 },
259 {
260 .cmd = CMD_PIO_WRITE_A_32,
261 .srcarg = 4,
262 .addr = NULL /* intr[0].iman */
263 },
264 {
265 .cmd = CMD_ACCEPT
266 },
267 {
268 .cmd = CMD_DECLINE
269 }
270};
271
272
273/**
274 * Generates code to accept interrupts. The xHCI is designed primarily for
275 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
276 * (except 0) are disabled.
277 */
278int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
279{
280 assert(code);
281 assert(hw_res);
282
283 if (hw_res->irqs.count != 1) {
284 usb_log_info("Unexpected HW resources to enable interrupts.");
285 return EINVAL;
286 }
287
288 code->ranges = malloc(sizeof(irq_pio_range_t));
289 if (code->ranges == NULL)
290 return ENOMEM;
291
292 code->cmds = malloc(sizeof(irq_commands));
293 if (code->cmds == NULL) {
294 free(code->ranges);
295 return ENOMEM;
296 }
297
298 code->rangecount = 1;
299 code->ranges[0] = (irq_pio_range_t) {
300 .base = RNGABS(hc->mmio_range),
301 .size = RNGSZ(hc->mmio_range),
302 };
303
304 code->cmdcount = ARRAY_SIZE(irq_commands);
305 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
306
307 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
308 void *usbsts = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) + offsetof(xhci_op_regs_t, usbsts);
309 code->cmds[0].addr = intr0_iman;
310 code->cmds[1].value = host2xhci(32, 1);
311 code->cmds[3].addr = usbsts;
312 code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
313 code->cmds[5].addr = usbsts;
314 code->cmds[6].addr = intr0_iman;
315
316 return hw_res->irqs.irqs[0];
317}
318
319int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
320{
321 /* No legacy support capability, the controller is solely for us */
322 if (!hc->legsup)
323 return EOK;
324
325 /*
326 * TODO: Implement handoff from BIOS, section 4.22.1
327 * QEMU does not support this, so we have to test on real HW.
328 */
329 return ENOTSUP;
330}
331
332static int hc_reset(xhci_hc_t *hc)
333{
334 /* Stop the HC: set R/S to 0 */
335 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
336
337 /* Wait 16 ms until the HC is halted */
338 async_usleep(16000);
339 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
340
341 /* Reset */
342 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
343
344 /* Wait until the reset is complete */
345 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
346 async_usleep(1000);
347
348 return EOK;
349}
350
351/**
352 * Initialize the HC: section 4.2
353 */
354int hc_start(xhci_hc_t *hc, bool irq)
355{
356 int err;
357
358 if ((err = hc_reset(hc)))
359 return err;
360
361 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
362 async_usleep(1000);
363
364 uint64_t dcbaaptr = addr_to_phys(hc->dcbaa);
365 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
366 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
367 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
368
369 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
370 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
371 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
372
373 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
374 uint64_t erdp = hc->event_ring.dequeue_ptr;
375 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
376 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
377 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
378 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
379 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
380 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
381
382 if (irq) {
383 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
384 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
385 }
386
387 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
388
389 return EOK;
390}
391
392/**
393 * Used only when polling. Shall supplement the irq_commands.
394 */
395int hc_status(xhci_hc_t *hc, uint32_t *status)
396{
397 int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
398 if (ip) {
399 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
400 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
401 XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
402
403 /* interrupt handler expects status from irq_commands, which is
404 * in xhci order. */
405 *status = host2xhci(32, *status);
406 }
407
408 usb_log_debug2("HC(%p): Polled status: %x", hc, *status);
409 return EOK;
410}
411
412int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
413{
414 assert(batch);
415
416 /* Check for root hub communication */
417 if (batch->ep->address == xhci_rh_get_address(&hc->rh)) {
418 usb_log_debug("XHCI root hub request.\n");
419 return xhci_rh_schedule(&hc->rh, batch);
420 }
421
422 usb_log_debug2("EP(%d:%d) started %s transfer of size %lu.",
423 batch->ep->address, batch->ep->endpoint,
424 usb_str_transfer_type(batch->ep->transfer_type),
425 batch->buffer_size);
426
427 switch (batch->ep->transfer_type) {
428 case USB_TRANSFER_CONTROL:
429 /* TODO: Send setup stage TRB. */
430 /* TODO: Optionally, send data stage TRB followed by zero or
431 more normal TRB's. */
432 /* TODO: Send status stage TRB. */
433 /* TODO: Ring the appropriate doorbell. */
434 break;
435 case USB_TRANSFER_ISOCHRONOUS:
436 /* TODO: Implement me. */
437 break;
438 case USB_TRANSFER_BULK:
439 /* TODO: Implement me. */
440 break;
441 case USB_TRANSFER_INTERRUPT:
442 /* TODO: Implement me. */
443 break;
444 }
445
446 return EOK;
447}
448
449static void hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb, xhci_interrupter_regs_t *intr)
450{
451 usb_log_debug2("TRB event encountered.");
452 switch (TRB_TYPE(*trb)) {
453 case XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT:
454 xhci_handle_command_completion(hc, trb);
455 break;
456 case XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT:
457 /**
458 * TODO: This is a very crude hotfix, I'm not sure if
459 * we can do this one level above in the event handling
460 * loop (incase the xHC adds more events while we process events).
461 */
462 hc->event_ring.dequeue_ptr = host2xhci(64, addr_to_phys(hc->event_ring.dequeue_trb));
463 uint64_t erdp = hc->event_ring.dequeue_ptr;
464 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
465 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
466 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
467 xhci_handle_port_status_change_event(hc, trb);
468 break;
469 default:
470 usb_log_debug2("Event type handling not implemented.");
471 break;
472 }
473}
474
475static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
476{
477 int err;
478 xhci_trb_t trb;
479
480 err = xhci_event_ring_dequeue(event_ring, &trb);;
481
482 while (err != ENOENT) {
483 if (err == EOK) {
484 usb_log_debug2("Dequeued trb from event ring: %s",
485 xhci_trb_str_type(TRB_TYPE(trb)));
486
487 hc_handle_event(hc, &trb, intr);
488 } else {
489 usb_log_warning("Error while accessing event ring: %s", str_error(err));
490 break;
491 }
492
493 err = xhci_event_ring_dequeue(event_ring, &trb);;
494 }
495 usb_log_debug2("Event ring processing finished.");
496
497 /* Update the ERDP to make room in the ring */
498 hc->event_ring.dequeue_ptr = host2xhci(64, addr_to_phys(hc->event_ring.dequeue_trb));
499 uint64_t erdp = hc->event_ring.dequeue_ptr;
500 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
501 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
502 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
503}
504
505void hc_interrupt(xhci_hc_t *hc, uint32_t status)
506{
507 status = xhci2host(32, status);
508
509 /* TODO: Figure out how root hub interrupts work. */
510 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
511 usb_log_debug2("Root hub interrupt.");
512 xhci_rh_interrupt(&hc->rh);
513
514 status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
515 }
516
517 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
518 usb_log_error("Host controller error occured. Bad things gonna happen...");
519 status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
520 }
521
522 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
523 usb_log_debug2("Event interrupt.");
524 hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
525 status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
526 }
527
528 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
529 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
530 status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
531 }
532
533 if (status) {
534 usb_log_error("Non-zero status after interrupt handling (%08x) - missing something?", status);
535 }
536}
537
538static void hc_dcbaa_fini(xhci_hc_t *hc)
539{
540 xhci_trb_ring_t* trb_ring;
541 xhci_scratchpad_free(hc);
542
543 /* Idx 0 already deallocated by xhci_scratchpad_free. */
544 for (unsigned i = 1; i < hc->max_slots + 1; ++i) {
545 if (hc->dcbaa_virt[i].dev_ctx) {
546 free32(hc->dcbaa_virt[i].dev_ctx);
547 hc->dcbaa_virt[i].dev_ctx = NULL;
548 }
549
550 for (unsigned i = 0; i < XHCI_EP_COUNT; ++i) {
551 trb_ring = hc->dcbaa_virt[i].trs[i];
552 if (trb_ring) {
553 hc->dcbaa_virt[i].trs[i] = NULL;
554 xhci_trb_ring_fini(trb_ring);
555 free32(trb_ring);
556 }
557 }
558 }
559
560 free32(hc->dcbaa);
561 free32(hc->dcbaa_virt);
562}
563
564void hc_fini(xhci_hc_t *hc)
565{
566 xhci_trb_ring_fini(&hc->command_ring);
567 xhci_event_ring_fini(&hc->event_ring);
568 hc_dcbaa_fini(hc);
569 xhci_fini_commands(hc);
570 xhci_rh_fini(&hc->rh);
571 pio_disable(hc->base, RNGSZ(hc->mmio_range));
572 usb_log_info("HC(%p): Finalized.", hc);
573}
574
575
576
577/**
578 * @}
579 */
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