source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 8fcd8cf

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8fcd8cf was 91ca111, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: extended capability handling

Currently, only detection of legacy support and parsing of protocol speeds is
implemented.
  • Property mode set to 100644
File size: 11.8 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "hw_struct/trb.h"
43
44static const irq_cmd_t irq_commands[] = {
45 {
46 .cmd = CMD_PIO_READ_32,
47 .dstarg = 1,
48 .addr = NULL
49 },
50 {
51 .cmd = CMD_AND,
52 .srcarg = 1,
53 .dstarg = 2,
54 .value = 0
55 },
56 {
57 .cmd = CMD_PREDICATE,
58 .srcarg = 2,
59 .value = 2
60 },
61 {
62 .cmd = CMD_PIO_WRITE_A_32,
63 .srcarg = 1,
64 .addr = NULL
65 },
66 {
67 .cmd = CMD_ACCEPT
68 }
69};
70
71/**
72 * Default USB Speed ID mapping: Table 157
73 */
74#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
75#define PORT_SPEED(psie, psim) { \
76 .rx_bps = PSI_TO_BPS(psie, psim), \
77 .tx_bps = PSI_TO_BPS(psie, psim) \
78}
79static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 12);
80static const xhci_port_speed_t ps_default_low = PORT_SPEED(1, 1500);
81static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 480);
82static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 5);
83
84/**
85 * Walk the list of extended capabilities.
86 */
87static int hc_parse_ec(xhci_hc_t *hc)
88{
89 unsigned psic, major;
90
91 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
92 xhci_dump_extcap(ec);
93 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
94 case XHCI_EC_USB_LEGACY:
95 assert(hc->legsup == NULL);
96 hc->legsup = (xhci_legsup_t *) ec;
97 break;
98 case XHCI_EC_SUPPORTED_PROTOCOL:
99 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
100 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
101
102 // "Implied" speed
103 if (psic == 0) {
104 /*
105 * According to section 7.2.2.1.2, only USB 2.0
106 * and USB 3.0 can have psic == 0. So we
107 * blindly assume the name == "USB " and minor
108 * == 0.
109 */
110 if (major == 2) {
111 hc->speeds[1] = ps_default_full;
112 hc->speeds[2] = ps_default_low;
113 hc->speeds[3] = ps_default_high;
114 } else if (major == 3) {
115 hc->speeds[4] = ps_default_super;
116 } else {
117 return EINVAL;
118 }
119
120 usb_log_debug2("Implied speed of USB %u set up.", major);
121 } else {
122 for (unsigned i = 0; i < psic; i++) {
123 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
124 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
125 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
126 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
127 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
128
129 uint64_t bps = PSI_TO_BPS(psie, psim);
130
131 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
132 hc->speeds[psiv].rx_bps = bps;
133 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
134 hc->speeds[psiv].tx_bps = bps;
135 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, hc->speeds[psiv].rx_bps, hc->speeds[psiv].tx_bps);
136 }
137 }
138 }
139 }
140 }
141 return EOK;
142}
143
144int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
145{
146 int err;
147
148 if (hw_res->mem_ranges.count != 1) {
149 usb_log_error("Unexpected MMIO area, bailing out.");
150 return EINVAL;
151 }
152
153 hc->mmio_range = hw_res->mem_ranges.ranges[0];
154
155 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
156 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
157
158 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
159 return EOVERFLOW;
160
161 void *base;
162 if ((err = pio_enable_range(&hc->mmio_range, &base)))
163 return err;
164
165 hc->base = base;
166 hc->cap_regs = (xhci_cap_regs_t *) base;
167 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
168 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
169 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
170
171 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
172 if (xec_offset > 0)
173 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
174
175 usb_log_debug2("Initialized MMIO reg areas:");
176 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
177 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
178 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
179 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
180
181 xhci_dump_cap_regs(hc->cap_regs);
182
183 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
184 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
185
186 if ((err = hc_parse_ec(hc))) {
187 pio_disable(hc->base, RNGSZ(hc->mmio_range));
188 return err;
189 }
190
191 return EOK;
192}
193
194int hc_init_memory(xhci_hc_t *hc)
195{
196 int err;
197
198 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(xhci_device_ctx_t));
199 if (!hc->dcbaa)
200 return ENOMEM;
201
202 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
203 goto err_dcbaa;
204
205 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
206 goto err_cmd_ring;
207
208 // TODO: Allocate scratchpad buffers
209
210 return EOK;
211
212 xhci_event_ring_fini(&hc->event_ring);
213err_cmd_ring:
214 xhci_trb_ring_fini(&hc->command_ring);
215err_dcbaa:
216 free32(hc->dcbaa);
217 return err;
218}
219
220
221/**
222 * Generates code to accept interrupts. The xHCI is designed primarily for
223 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
224 * (except 0) are disabled.
225 */
226int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
227{
228 assert(code);
229 assert(hw_res);
230
231 if (hw_res->irqs.count != 1) {
232 usb_log_info("Unexpected HW resources to enable interrupts.");
233 return EINVAL;
234 }
235
236 code->ranges = malloc(sizeof(irq_pio_range_t));
237 if (code->ranges == NULL)
238 return ENOMEM;
239
240 code->cmds = malloc(sizeof(irq_commands));
241 if (code->cmds == NULL) {
242 free(code->ranges);
243 return ENOMEM;
244 }
245
246 code->rangecount = 1;
247 code->ranges[0] = (irq_pio_range_t) {
248 .base = RNGABS(hc->mmio_range),
249 .size = RNGSZ(hc->mmio_range),
250 };
251
252 code->cmdcount = ARRAY_SIZE(irq_commands);
253 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
254
255 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
256 code->cmds[0].addr = intr0_iman;
257 code->cmds[3].addr = intr0_iman;
258 code->cmds[1].value = host2xhci(32, 1);
259
260 return hw_res->irqs.irqs[0];
261}
262
263int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
264{
265 /* No legacy support capability, the controller is solely for us */
266 if (!hc->legsup)
267 return EOK;
268
269 /*
270 * TODO: Implement handoff from BIOS, section 4.22.1
271 * QEMU does not support this, so we have to test on real HW.
272 */
273 return ENOTSUP;
274}
275
276static int hc_reset(xhci_hc_t *hc)
277{
278 /* Stop the HC: set R/S to 0 */
279 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
280
281 /* Wait 16 ms until the HC is halted */
282 async_usleep(16000);
283 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
284
285 /* Reset */
286 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
287
288 /* Wait until the reset is complete */
289 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
290 async_usleep(1000);
291
292 return EOK;
293}
294
295/**
296 * Initialize the HC: section 4.2
297 */
298int hc_start(xhci_hc_t *hc, bool irq)
299{
300 int err;
301
302 if ((err = hc_reset(hc)))
303 return err;
304
305 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
306 async_usleep(1000);
307
308 uint64_t dcbaaptr = addr_to_phys(hc->event_ring.erst);
309 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
310 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
311 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
312
313 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
314 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
315 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
316
317 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
318 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
319 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
320 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erstptr));
321 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erstptr));
322 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
323 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
324
325 // TODO: Setup scratchpad buffers
326
327 if (irq) {
328 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
329 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
330 }
331
332 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
333
334 return EOK;
335}
336
337int hc_status(xhci_hc_t *hc, uint32_t *status)
338{
339 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
340 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
341
342 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
343 return EOK;
344}
345
346static int ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
347{
348 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
349 pio_write_32(&hc->db_arry[doorbell], v);
350 return EOK;
351}
352
353static int send_no_op_command(xhci_hc_t *hc)
354{
355 xhci_trb_t trb;
356 memset(&trb, 0, sizeof(trb));
357
358 trb.control = host2xhci(32, XHCI_TRB_TYPE_NO_OP_CMD << 10);
359
360 xhci_trb_ring_enqueue(&hc->command_ring, &trb);
361 ring_doorbell(hc, 0, 0);
362
363 xhci_dump_trb(&trb);
364 usb_log_debug2("HC(%p): Sent TRB", hc);
365 return EOK;
366}
367
368int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
369{
370 xhci_dump_state(hc);
371 send_no_op_command(hc);
372 async_usleep(1000);
373 xhci_dump_state(hc);
374
375 xhci_dump_trb(hc->event_ring.dequeue_trb);
376 return EOK;
377}
378
379static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
380{
381 int err;
382 xhci_trb_t trb;
383
384 err = xhci_event_ring_dequeue(event_ring, &trb);;
385
386 switch (err) {
387 case EOK:
388 usb_log_debug2("Dequeued from event ring.");
389 xhci_dump_trb(&trb);
390 break;
391
392 case ENOENT:
393 usb_log_debug2("Event ring finished.");
394 break;
395
396 default:
397 usb_log_warning("Error while accessing event ring: %s", str_error(err));
398 }
399
400 /* Update the ERDP to make room inthe ring */
401 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
402 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erstptr));
403 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erstptr));
404}
405
406void hc_interrupt(xhci_hc_t *hc, uint32_t status)
407{
408 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
409 usb_log_error("Host controller error occured. Bad things gonna happen...");
410 }
411
412 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
413 usb_log_debug2("Event interrupt.");
414
415 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
416
417 if (XHCI_REG_RD(intr0, XHCI_INTR_IP)) {
418 XHCI_REG_SET(intr0, XHCI_INTR_IP, 1);
419 hc_run_event_ring(hc, &hc->event_ring, intr0);
420 }
421 }
422
423 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
424 usb_log_error("Port change detected. Not implemented yet!");
425 }
426
427 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
428 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
429 }
430}
431
432void hc_fini(xhci_hc_t *hc)
433{
434 xhci_trb_ring_fini(&hc->command_ring);
435 xhci_event_ring_fini(&hc->event_ring);
436 pio_disable(hc->base, RNGSZ(hc->mmio_range));
437 usb_log_info("HC(%p): Finalized.", hc);
438}
439
440
441
442/**
443 * @}
444 */
Note: See TracBrowser for help on using the repository browser.