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source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 73a5857

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Last change on this file since 73a5857 was 73a5857, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago
usbhost: add joinable_fibril utility
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1	/*
2	* Copyright (c) 2017 Ondrej Hlavaty
3	* All rights reserved.
4	*
5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions
7	* are met:
8	*
9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.
16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/
28
29	/** @addtogroup drvusbxhci
30	* @{
31	*/
32	/** @file
33	* @brief The host controller data bookkeeping.
34	*/
35
36	#include <errno.h>
37	#include <str_error.h>
38	#include <usb/debug.h>
39	#include <usb/host/endpoint.h>
40	#include "debug.h"
41	#include "hc.h"
42	#include "rh.h"
43	#include "hw_struct/trb.h"
44	#include "hw_struct/context.h"
45	#include "endpoint.h"
46	#include "transfers.h"
47	#include "trb_ring.h"
48
49	/**
50	* Default USB Speed ID mapping: Table 157
51	*/
52	#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53	#define PORT_SPEED(usb, mjr, psie, psim) { \
54	.name = "USB ", \
55	.major = mjr, \
56	.minor = 0, \
57	.usb_speed = USB_SPEED_##usb, \
58	.rx_bps = PSI_TO_BPS(psie, psim), \
59	.tx_bps = PSI_TO_BPS(psie, psim) \
60	}
61
62	static const xhci_port_speed_t default_psiv_to_port_speed [] = {
63	[1] = PORT_SPEED(FULL, 2, 2, 12),
64	[2] = PORT_SPEED(LOW, 2, 1, 1500),
65	[3] = PORT_SPEED(HIGH, 2, 2, 480),
66	[4] = PORT_SPEED(SUPER, 3, 3, 5),
67	};
68
69	static const unsigned usb_speed_to_psiv [] = {
70	[USB_SPEED_FULL] = 1,
71	[USB_SPEED_LOW] = 2,
72	[USB_SPEED_HIGH] = 3,
73	[USB_SPEED_SUPER] = 4,
74	};
75
76	/**
77	* Walk the list of extended capabilities.
78	*
79	* The most interesting thing hidden in extended capabilities is the mapping of
80	* ports to protocol versions and speeds.
81	*/
82	static int hc_parse_ec(xhci_hc_t *hc)
83	{
84	unsigned psic, major, minor;
85	xhci_sp_name_t name;
86
87	xhci_port_speed_t *speeds = hc->speeds;
88
89	for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
90	xhci_dump_extcap(ec);
91	switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
92	case XHCI_EC_USB_LEGACY:
93	assert(hc->legsup == NULL);
94	hc->legsup = (xhci_legsup_t *) ec;
95	break;
96	case XHCI_EC_SUPPORTED_PROTOCOL:
97	psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
98	major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
99	minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
100	name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
101
102	if (name.packed != xhci_name_usb.packed) {
103	/**
104	* The detection of such protocol would work,
105	* but the rest of the implementation is made
106	* for the USB protocol only.
107	*/
108	usb_log_error("Unknown protocol %.4s.", name.str);
109	return ENOTSUP;
110	}
111
112	unsigned offset = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
113	unsigned count = XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT);
114	xhci_rh_set_ports_protocol(&hc->rh, offset, count, major);
115
116	// "Implied" speed
117	if (psic == 0) {
118	assert(minor == 0);
119
120	if (major == 2) {
121	speeds[1] = default_psiv_to_port_speed[1];
122	speeds[2] = default_psiv_to_port_speed[2];
123	speeds[3] = default_psiv_to_port_speed[3];
124	} else if (major == 3) {
125	speeds[4] = default_psiv_to_port_speed[4];
126	} else {
127	return EINVAL;
128	}
129
130	usb_log_debug("Implied speed of USB %u.0 set up.", major);
131	} else {
132	for (unsigned i = 0; i < psic; i++) {
133	xhci_psi_t *psi = xhci_extcap_psi(ec, i);
134	unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
135	unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
136	unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
137	unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
138	uint64_t bps = PSI_TO_BPS(psie, psim);
139
140	/*
141	* Speed is not implied, but using one of default PSIV. This
142	* is not clearly stated in xHCI spec. There is a clear
143	* intention to allow xHCI to specify its own speed
144	* parameters, but throughout the document, they used fixed
145	* values for e.g. High-speed (3), without stating the
146	* controller shall have implied default speeds - and for
147	* instance Intel controllers do not. So let's check if the
148	* values match and if so, accept the implied USB speed too.
149	*
150	* The main reason we need this is the usb_speed to have
151	* mapping also for devices connected to hubs.
152	*/
153	if (psiv < ARRAY_SIZE(default_psiv_to_port_speed)
154	&& default_psiv_to_port_speed[psiv].major == major
155	&& default_psiv_to_port_speed[psiv].minor == minor
156	&& default_psiv_to_port_speed[psiv].rx_bps == bps
157	&& default_psiv_to_port_speed[psiv].tx_bps == bps) {
158	speeds[psiv] = default_psiv_to_port_speed[psiv];
159	usb_log_debug("Assumed default %s speed of USB %u.",
160	usb_str_speed(speeds[psiv].usb_speed), major);
161	continue;
162	}
163
164	// Custom speed
165	speeds[psiv].major = major;
166	speeds[psiv].minor = minor;
167	str_ncpy(speeds[psiv].name, 4, name.str, 4);
168	speeds[psiv].usb_speed = USB_SPEED_MAX;
169
170	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_RX)
171	speeds[psiv].rx_bps = bps;
172	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_TX) {
173	speeds[psiv].tx_bps = bps;
174	usb_log_debug("Speed %u set up for bps %" PRIu64
175	" / %" PRIu64 ".", psiv, speeds[psiv].rx_bps,
176	speeds[psiv].tx_bps);
177	}
178	}
179	}
180	}
181	}
182	return EOK;
183	}
184
185	/**
186	* Initialize MMIO spaces of xHC.
187	*/
188	int hc_init_mmio(xhci_hc_t hc, const hw_res_list_parsed_t hw_res)
189	{
190	int err;
191
192	if (hw_res->mem_ranges.count != 1) {
193	usb_log_error("Unexpected MMIO area, bailing out.");
194	return EINVAL;
195	}
196
197	hc->mmio_range = hw_res->mem_ranges.ranges[0];
198
199	usb_log_debug("MMIO area at %p (size %zu), IRQ %d.",
200	RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
201
202	if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
203	return EOVERFLOW;
204
205	void *base;
206	if ((err = pio_enable_range(&hc->mmio_range, &base)))
207	return err;
208
209	hc->reg_base = base;
210	hc->cap_regs = (xhci_cap_regs_t *) base;
211	hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
212	hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
213	hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
214
215	uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
216	if (xec_offset > 0)
217	hc->xecp = (xhci_extcap_t *) (base + xec_offset);
218
219	usb_log_debug("Initialized MMIO reg areas:");
220	usb_log_debug("\tCapability regs: %p", hc->cap_regs);
221	usb_log_debug("\tOperational regs: %p", hc->op_regs);
222	usb_log_debug("\tRuntime regs: %p", hc->rt_regs);
223	usb_log_debug("\tDoorbell array base: %p", hc->db_arry);
224
225	xhci_dump_cap_regs(hc->cap_regs);
226
227	hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
228	hc->csz = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_CSZ);
229	hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
230
231	struct timeval tv;
232	getuptime(&tv);
233	hc->wrap_time = tv.tv_sec * 1000000 + tv.tv_usec;
234	hc->wrap_count = 0;
235
236	unsigned ist = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_IST);
237	hc->ist = (ist & 0x10 >> 1) * (ist & 0xf);
238
239	if ((err = xhci_rh_init(&hc->rh, hc)))
240	goto err_pio;
241
242	if ((err = hc_parse_ec(hc)))
243	goto err_rh;
244
245	return EOK;
246
247	err_rh:
248	xhci_rh_fini(&hc->rh);
249	err_pio:
250	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
251	return err;
252	}
253
254	static int event_worker(void *arg);
255
256	/**
257	* Initialize structures kept in allocated memory.
258	*/
259	int hc_init_memory(xhci_hc_t hc, ddf_dev_t device)
260	{
261	int err;
262
263	if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
264	return ENOMEM;
265	hc->dcbaa = hc->dcbaa_dma.virt;
266
267	if ((err = xhci_event_ring_init(&hc->event_ring, 1)))
268	goto err_dcbaa;
269
270	if ((err = xhci_scratchpad_alloc(hc)))
271	goto err_event_ring;
272
273	if ((err = xhci_init_commands(hc)))
274	goto err_scratch;
275
276	if ((err = xhci_bus_init(&hc->bus, hc)))
277	goto err_cmd;
278
279	hc->event_worker = joinable_fibril_create(&event_worker, hc);
280	if (!hc->event_worker)
281	goto err_bus;
282
283	xhci_sw_ring_init(&hc->sw_ring, PAGE_SIZE / sizeof(xhci_trb_t));
284
285	joinable_fibril_start(hc->event_worker);
286
287	return EOK;
288
289	err_bus:
290	xhci_bus_fini(&hc->bus);
291	err_cmd:
292	xhci_fini_commands(hc);
293	err_scratch:
294	xhci_scratchpad_free(hc);
295	err_event_ring:
296	xhci_event_ring_fini(&hc->event_ring);
297	err_dcbaa:
298	hc->dcbaa = NULL;
299	dma_buffer_free(&hc->dcbaa_dma);
300	return err;
301	}
302
303	/*
304	* Pseudocode:
305	* ip = read(intr[0].iman)
306	* if (ip) {
307	* status = read(usbsts)
308	* assert status
309	* assert ip
310	* accept (passing status)
311	* }
312	* decline
313	*/
314	static const irq_cmd_t irq_commands[] = {
315	{
316	.cmd = CMD_PIO_READ_32,
317	.dstarg = 3,
318	.addr = NULL /* intr[0].iman */
319	},
320	{
321	.cmd = CMD_AND,
322	.srcarg = 3,
323	.dstarg = 4,
324	.value = 0 /* host2xhci(32, 1) */
325	},
326	{
327	.cmd = CMD_PREDICATE,
328	.srcarg = 4,
329	.value = 5
330	},
331	{
332	.cmd = CMD_PIO_READ_32,
333	.dstarg = 1,
334	.addr = NULL /* usbsts */
335	},
336	{
337	.cmd = CMD_AND,
338	.srcarg = 1,
339	.dstarg = 2,
340	.value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
341	},
342	{
343	.cmd = CMD_PIO_WRITE_A_32,
344	.srcarg = 2,
345	.addr = NULL /* usbsts */
346	},
347	{
348	.cmd = CMD_PIO_WRITE_A_32,
349	.srcarg = 3,
350	.addr = NULL /* intr[0].iman */
351	},
352	{
353	.cmd = CMD_ACCEPT
354	},
355	{
356	.cmd = CMD_DECLINE
357	}
358	};
359
360
361	/**
362	* Generates code to accept interrupts. The xHCI is designed primarily for
363	* MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
364	* (except 0) are disabled.
365	*/
366	int hc_irq_code_gen(irq_code_t code, xhci_hc_t hc, const hw_res_list_parsed_t hw_res, int irq)
367	{
368	assert(code);
369	assert(hw_res);
370
371	if (hw_res->irqs.count != 1) {
372	usb_log_info("Unexpected HW resources to enable interrupts.");
373	return EINVAL;
374	}
375
376	code->ranges = malloc(sizeof(irq_pio_range_t));
377	if (code->ranges == NULL)
378	return ENOMEM;
379
380	code->cmds = malloc(sizeof(irq_commands));
381	if (code->cmds == NULL) {
382	free(code->ranges);
383	return ENOMEM;
384	}
385
386	code->rangecount = 1;
387	code->ranges[0] = (irq_pio_range_t) {
388	.base = RNGABS(hc->mmio_range),
389	.size = RNGSZ(hc->mmio_range),
390	};
391
392	code->cmdcount = ARRAY_SIZE(irq_commands);
393	memcpy(code->cmds, irq_commands, sizeof(irq_commands));
394
395	void *intr0_iman = RNGABSPTR(hc->mmio_range)
396	+ XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF)
397	+ offsetof(xhci_rt_regs_t, ir[0]);
398	void *usbsts = RNGABSPTR(hc->mmio_range)
399	+ XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH)
400	+ offsetof(xhci_op_regs_t, usbsts);
401
402	code->cmds[0].addr = intr0_iman;
403	code->cmds[1].value = host2xhci(32, 1);
404	code->cmds[3].addr = usbsts;
405	code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
406	code->cmds[5].addr = usbsts;
407	code->cmds[6].addr = intr0_iman;
408
409	*irq = hw_res->irqs.irqs[0];
410	return EOK;
411	}
412
413	/**
414	* Claim xHC from BIOS. Implements handoff as per Section 4.22.1 of xHCI spec.
415	*/
416	int hc_claim(xhci_hc_t hc, ddf_dev_t dev)
417	{
418	/* No legacy support capability, the controller is solely for us */
419	if (!hc->legsup)
420	return EOK;
421
422	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
423	return ETIMEOUT;
424
425	usb_log_debug("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
426	XHCI_REG_SET(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
427	for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
428	usb_log_debug("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
429	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
430	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
431	if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
432	return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO;
433	}
434	async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
435	}
436	usb_log_error("BIOS did not release XHCI legacy hold!");
437
438	return ENOTSUP;
439	}
440
441	/**
442	* Ask the xHC to reset its state. Implements sequence
443	*/
444	static int hc_reset(xhci_hc_t *hc)
445	{
446	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
447	return ETIMEOUT;
448
449	/* Stop the HC: set R/S to 0 */
450	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
451
452	/* Wait until the HC is halted - it shall take at most 16 ms */
453	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
454	XHCI_REG_MASK(XHCI_OP_HCH)))
455	return ETIMEOUT;
456
457	/* Reset */
458	XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
459
460	/* Wait until the reset is complete */
461	if (xhci_reg_wait(&hc->op_regs->usbcmd, XHCI_REG_MASK(XHCI_OP_HCRST), 0))
462	return ETIMEOUT;
463
464	return EOK;
465	}
466
467	/**
468	* Initialize the HC: section 4.2
469	*/
470	int hc_start(xhci_hc_t *hc, bool irq)
471	{
472	int err;
473
474	if ((err = hc_reset(hc)))
475	return err;
476
477	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
478	return ETIMEOUT;
479
480	uint64_t dcbaaptr = hc->dcbaa_dma.phys;
481	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
482	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
483	XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
484
485	uintptr_t crcr;
486	xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
487	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crcr));
488	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crcr));
489
490	XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
491
492	xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
493	XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
494	uint64_t erdp = hc->event_ring.dequeue_ptr;
495	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
496	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
497	uint64_t erstptr = hc->event_ring.erst.phys;
498	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
499	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
500
501	if (irq) {
502	XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
503	XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
504	}
505
506	XHCI_REG_SET(hc->op_regs, XHCI_OP_HSEE, 1);
507
508	XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
509
510	xhci_rh_startup(&hc->rh);
511
512	return EOK;
513	}
514
515	/**
516	* Used only when polling. Shall supplement the irq_commands.
517	*/
518	int hc_status(bus_t bus, uint32_t status)
519	{
520	xhci_hc_t *hc = bus_to_hc(bus);
521	int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
522	if (ip) {
523	*status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
524	XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
525	XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
526
527	/* interrupt handler expects status from irq_commands, which is
528	* in xhci order. */
529	status = host2xhci(32, status);
530	}
531
532	usb_log_debug("Polled status: %x", *status);
533	return EOK;
534	}
535
536	static int xhci_handle_mfindex_wrap_event(xhci_hc_t hc, xhci_trb_t trb)
537	{
538	struct timeval tv;
539	getuptime(&tv);
540	usb_log_debug("Microframe index wrapped (@%lu.%li, %"PRIu64" total).",
541	tv.tv_sec, tv.tv_usec, hc->wrap_count);
542	hc->wrap_time = ((uint64_t) tv.tv_sec) * 1000000 + ((uint64_t) tv.tv_usec);
543	++hc->wrap_count;
544	return EOK;
545	}
546
547	typedef int (event_handler) (xhci_hc_t , xhci_trb_t *trb);
548
549	/**
550	* These events are handled by separate event handling fibril.
551	*/
552	static event_handler event_handlers [] = {
553	[XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
554	};
555
556	/**
557	* These events are handled directly in the interrupt handler, thus they must
558	* not block waiting for another interrupt.
559	*/
560	static event_handler event_handlers_fast [] = {
561	[XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
562	[XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT] = &xhci_handle_mfindex_wrap_event,
563	};
564
565	static int hc_handle_event(xhci_hc_t hc, xhci_trb_t trb)
566	{
567	const unsigned type = TRB_TYPE(*trb);
568
569	if (type <= ARRAY_SIZE(event_handlers_fast) && event_handlers_fast[type])
570	return event_handlers_fast[type](hc, trb);
571
572	if (type <= ARRAY_SIZE(event_handlers) && event_handlers[type])
573	return xhci_sw_ring_enqueue(&hc->sw_ring, trb);
574
575	if (type == XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT)
576	return xhci_sw_ring_enqueue(&hc->rh.event_ring, trb);
577
578	return ENOTSUP;
579	}
580
581	static int event_worker(void *arg)
582	{
583	int err;
584	xhci_trb_t trb;
585	xhci_hc_t * const hc = arg;
586	assert(hc);
587
588	while (xhci_sw_ring_dequeue(&hc->sw_ring, &trb) != EINTR) {
589	const unsigned type = TRB_TYPE(trb);
590
591	if ((err = event_handlers[type](hc, &trb)))
592	usb_log_error("Failed to handle event: %s", str_error(err));
593	}
594
595	return 0;
596	}
597
598	/**
599	* Dequeue from event ring and handle dequeued events.
600	*
601	* As there can be events, that blocks on waiting for subsequent events,
602	* we solve this problem by deferring some types of events to separate fibrils.
603	*/
604	static void hc_run_event_ring(xhci_hc_t hc, xhci_event_ring_t event_ring,
605	xhci_interrupter_regs_t *intr)
606	{
607	int err;
608
609	xhci_trb_t trb;
610	hc->event_handler = fibril_get_id();
611
612	while ((err = xhci_event_ring_dequeue(event_ring, &trb)) != ENOENT) {
613	if ((err = hc_handle_event(hc, &trb)) != EOK) {
614	usb_log_error("Failed to handle event in interrupt: %s", str_error(err));
615	}
616
617	uint64_t erdp = hc->event_ring.dequeue_ptr;
618	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
619	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
620	}
621
622	hc->event_handler = 0;
623
624	/* Update the ERDP to make room in the ring. */
625	uint64_t erdp = hc->event_ring.dequeue_ptr;
626	erdp \|= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
627	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
628	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
629
630	usb_log_debug2("Event ring run finished.");
631	}
632
633	/**
634	* Handle an interrupt request from xHC. Resolve all situations that trigger an
635	* interrupt separately.
636	*
637	* Note that all RW1C bits in USBSTS register are cleared at the time of
638	* handling the interrupt in irq_code. This method is the top-half.
639	*
640	* @param status contents of USBSTS register at the time of the interrupt.
641	*/
642	void hc_interrupt(bus_t *bus, uint32_t status)
643	{
644	xhci_hc_t *hc = bus_to_hc(bus);
645	status = xhci2host(32, status);
646
647	if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
648	usb_log_error("Host controller error occured. Bad things gonna happen...");
649	status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
650	}
651
652	if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
653	usb_log_debug2("Event interrupt, running the event ring.");
654	hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
655	status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
656	}
657
658	if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
659	usb_log_error("Save/Restore error occured. WTF, "
660	"S/R mechanism not implemented!");
661	status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
662	}
663
664	/* According to Note on p. 302, we may safely ignore the PCD bit. */
665	status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
666
667	if (status) {
668	usb_log_error("Non-zero status after interrupt handling (%08x) "
669	" - missing something?", status);
670	}
671	}
672
673	/**
674	* Tear down all in-memory structures.
675	*/
676	void hc_fini(xhci_hc_t *hc)
677	{
678	xhci_sw_ring_stop(&hc->sw_ring);
679	joinable_fibril_join(hc->event_worker);
680	xhci_sw_ring_fini(&hc->sw_ring);
681
682	xhci_bus_fini(&hc->bus);
683	xhci_event_ring_fini(&hc->event_ring);
684	xhci_scratchpad_free(hc);
685	dma_buffer_free(&hc->dcbaa_dma);
686	xhci_fini_commands(hc);
687	xhci_rh_fini(&hc->rh);
688	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
689	usb_log_info("Finalized.");
690	}
691
692	unsigned hc_speed_to_psiv(usb_speed_t speed)
693	{
694	assert(speed < ARRAY_SIZE(usb_speed_to_psiv));
695	return usb_speed_to_psiv[speed];
696	}
697
698	/**
699	* Ring a xHC Doorbell. Implements section 4.7.
700	*/
701	void hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
702	{
703	assert(hc);
704	uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
705	pio_write_32(&hc->db_arry[doorbell], v);
706	usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
707	}
708
709	/**
710	* Return an index to device context.
711	*/
712	static uint8_t endpoint_dci(xhci_endpoint_t *ep)
713	{
714	return (2 * ep->base.endpoint) +
715	(ep->base.transfer_type == USB_TRANSFER_CONTROL
716	\|\| ep->base.direction == USB_DIRECTION_IN);
717	}
718
719	void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id)
720	{
721	xhci_device_t * const dev = xhci_ep_to_dev(ep);
722	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
723	const uint8_t dci = endpoint_dci(ep);
724	const uint32_t target = (stream_id << 16) \| (dci & 0x1ff);
725	hc_ring_doorbell(hc, dev->slot_id, target);
726	}
727
728	/**
729	* Issue an Enable Slot command. Allocate memory for the slot and fill the
730	* DCBAA with the newly created slot.
731	*/
732	int hc_enable_slot(xhci_device_t *dev)
733	{
734	int err;
735	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
736
737	/* Prepare memory for the context */
738	if ((err = dma_buffer_alloc(&dev->dev_ctx, XHCI_DEVICE_CTX_SIZE(hc))))
739	return err;
740	memset(dev->dev_ctx.virt, 0, XHCI_DEVICE_CTX_SIZE(hc));
741
742	/* Get the slot number */
743	xhci_cmd_t cmd;
744	xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
745
746	err = xhci_cmd_sync(hc, &cmd);
747
748	/* Link them together */
749	if (err == EOK) {
750	dev->slot_id = cmd.slot_id;
751	hc->dcbaa[dev->slot_id] = host2xhci(64, dev->dev_ctx.phys);
752	}
753
754	xhci_cmd_fini(&cmd);
755
756	if (err)
757	dma_buffer_free(&dev->dev_ctx);
758
759	return err;
760	}
761
762	/**
763	* Issue a Disable Slot command for a slot occupied by device.
764	* Frees the device context.
765	*/
766	int hc_disable_slot(xhci_device_t *dev)
767	{
768	int err;
769	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
770
771	if ((err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = dev->slot_id))) {
772	return err;
773	}
774
775	/* Free the device context. */
776	hc->dcbaa[dev->slot_id] = 0;
777	dma_buffer_free(&dev->dev_ctx);
778
779	/* Mark the slot as invalid. */
780	dev->slot_id = 0;
781
782	return EOK;
783	}
784
785	/**
786	* Prepare an empty Endpoint Input Context inside a dma buffer.
787	*/
788	static int create_configure_ep_input_ctx(xhci_device_t dev, dma_buffer_t dma_buf)
789	{
790	const xhci_hc_t * hc = bus_to_hc(dev->base.bus);
791	const int err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc));
792	if (err)
793	return err;
794
795	xhci_input_ctx_t *ictx = dma_buf->virt;
796	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
797
798	// Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
799	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 0);
800	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
801	xhci_setup_slot_context(dev, slot_ctx);
802
803	return EOK;
804	}
805
806	/**
807	* Initialize a device, assigning it an address. Implements section 4.3.4.
808	*
809	* @param dev Device to assing an address (unconfigured yet)
810	*/
811	int hc_address_device(xhci_device_t *dev)
812	{
813	int err = ENOMEM;
814	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
815	xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]);
816
817	/* Although we have the precise PSIV value on devices of tier 1,
818	* we have to rely on reverse mapping on others. */
819	if (!usb_speed_to_psiv[dev->base.speed]) {
820	usb_log_error("Device reported an USB speed (%s) that cannot be mapped "
821	"to HC port speed.", usb_str_speed(dev->base.speed));
822	return EINVAL;
823	}
824
825	/* Issue configure endpoint command (sec 4.3.5). */
826	dma_buffer_t ictx_dma_buf;
827	if ((err = create_configure_ep_input_ctx(dev, &ictx_dma_buf)))
828	return err;
829	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
830
831	/* Copy endpoint 0 context and set A1 flag. */
832	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 1);
833	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, 1);
834	xhci_setup_endpoint_context(ep0, ep_ctx);
835
836	/* Address device needs Ctx entries set to 1 only */
837	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
838	XHCI_SLOT_CTX_ENTRIES_SET(*slot_ctx, 1);
839
840	/* Issue Address Device command. */
841	if ((err = xhci_cmd_sync_inline(hc, ADDRESS_DEVICE,
842	.slot_id = dev->slot_id,
843	.input_ctx = ictx_dma_buf
844	)))
845	return err;
846
847	xhci_device_ctx_t *device_ctx = dev->dev_ctx.virt;
848	dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(*XHCI_GET_SLOT_CTX(device_ctx, hc));
849	usb_log_debug("Obtained USB address: %d.", dev->base.address);
850
851	return EOK;
852	}
853
854	/**
855	* Issue a Configure Device command for a device in slot.
856	*
857	* @param slot_id Slot ID assigned to the device.
858	*/
859	int hc_configure_device(xhci_device_t *dev)
860	{
861	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
862
863	/* Issue configure endpoint command (sec 4.3.5). */
864	dma_buffer_t ictx_dma_buf;
865	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
866	if (err)
867	return err;
868
869	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
870	.slot_id = dev->slot_id,
871	.input_ctx = ictx_dma_buf
872	);
873	}
874
875	/**
876	* Issue a Deconfigure Device command for a device in slot.
877	*
878	* @param dev The owner of the device
879	*/
880	int hc_deconfigure_device(xhci_device_t *dev)
881	{
882	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
883
884	/* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
885	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
886	.slot_id = dev->slot_id,
887	.deconfigure = true
888	);
889	}
890
891	/**
892	* Instruct xHC to add an endpoint with supplied endpoint context.
893	*
894	* @param dev The owner of the device
895	* @param ep_idx Endpoint DCI in question
896	* @param ep_ctx Endpoint context of the endpoint
897	*/
898	int hc_add_endpoint(xhci_endpoint_t *ep)
899	{
900	xhci_device_t * const dev = xhci_ep_to_dev(ep);
901	const unsigned dci = endpoint_dci(ep);
902
903	/* Issue configure endpoint command (sec 4.3.5). */
904	dma_buffer_t ictx_dma_buf;
905	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
906	if (err)
907	return err;
908
909	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
910
911	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
912	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
913
914	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
915	xhci_setup_endpoint_context(ep, ep_ctx);
916
917	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
918	.slot_id = dev->slot_id,
919	.input_ctx = ictx_dma_buf
920	);
921	}
922
923	/**
924	* Instruct xHC to drop an endpoint.
925	*
926	* @param dev The owner of the endpoint
927	* @param ep_idx Endpoint DCI in question
928	*/
929	int hc_drop_endpoint(xhci_endpoint_t *ep)
930	{
931	xhci_device_t * const dev = xhci_ep_to_dev(ep);
932	const unsigned dci = endpoint_dci(ep);
933
934	/* Issue configure endpoint command (sec 4.3.5). */
935	dma_buffer_t ictx_dma_buf;
936	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
937	if (err)
938	return err;
939
940	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
941	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
942	XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
943
944	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
945	.slot_id = dev->slot_id,
946	.input_ctx = ictx_dma_buf
947	);
948	}
949
950	/**
951	* Instruct xHC to update information about an endpoint, using supplied
952	* endpoint context.
953	*
954	* @param dev The owner of the endpoint
955	* @param ep_idx Endpoint DCI in question
956	* @param ep_ctx Endpoint context of the endpoint
957	*/
958	int hc_update_endpoint(xhci_endpoint_t *ep)
959	{
960	xhci_device_t * const dev = xhci_ep_to_dev(ep);
961	const unsigned dci = endpoint_dci(ep);
962
963	dma_buffer_t ictx_dma_buf;
964	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
965
966	const int err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));
967	if (err)
968	return err;
969
970	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
971	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
972
973	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
974	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
975	xhci_setup_endpoint_context(ep, ep_ctx);
976
977	return xhci_cmd_sync_inline(hc, EVALUATE_CONTEXT,
978	.slot_id = dev->slot_id,
979	.input_ctx = ictx_dma_buf
980	);
981	}
982
983	/**
984	* Instruct xHC to stop running a transfer ring on an endpoint.
985	*
986	* @param dev The owner of the endpoint
987	* @param ep_idx Endpoint DCI in question
988	*/
989	int hc_stop_endpoint(xhci_endpoint_t *ep)
990	{
991	xhci_device_t * const dev = xhci_ep_to_dev(ep);
992	const unsigned dci = endpoint_dci(ep);
993	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
994	return xhci_cmd_sync_inline(hc, STOP_ENDPOINT,
995	.slot_id = dev->slot_id,
996	.endpoint_id = dci
997	);
998	}
999
1000	/**
1001	* Instruct xHC to reset halted endpoint.
1002	*
1003	* @param dev The owner of the endpoint
1004	* @param ep_idx Endpoint DCI in question
1005	*/
1006	int hc_reset_endpoint(xhci_endpoint_t *ep)
1007	{
1008	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1009	const unsigned dci = endpoint_dci(ep);
1010	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1011	return xhci_cmd_sync_inline(hc, RESET_ENDPOINT,
1012	.slot_id = dev->slot_id,
1013	.endpoint_id = dci
1014	);
1015	}
1016
1017	/**
1018	* Reset a ring position in both software and hardware.
1019	*
1020	* @param dev The owner of the endpoint
1021	*/
1022	int hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id)
1023	{
1024	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1025	const unsigned dci = endpoint_dci(ep);
1026	uintptr_t addr;
1027
1028	xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id);
1029	xhci_trb_ring_reset_dequeue_state(ring, &addr);
1030
1031	xhci_hc_t * const hc = bus_to_hc(endpoint_get_bus(&ep->base));
1032	return xhci_cmd_sync_inline(hc, SET_TR_DEQUEUE_POINTER,
1033	.slot_id = dev->slot_id,
1034	.endpoint_id = dci,
1035	.stream_id = stream_id,
1036	.dequeue_ptr = addr,
1037	);
1038	}
1039
1040	/**
1041	* @}
1042	*/

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