Context Navigation

hc.c@ 5a68791

Visit:

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export

Last change on this file since 5a68791 was d1582b50, checked in by Jiri Svoboda <jiri@…>, 5 years ago

Fix spacing in single-line comments using latest ccheck

This found incorrectly formatted section comments (with blocks of
asterisks or dashes). I strongly believe against using section comments
but I am not simply removing them since that would probably be
controversial.

Property mode set to 100644

File size: 30.9 KB

Line
1	/*
2	* Copyright (c) 2018 Ondrej Hlavaty, Petr Manek, Jaroslav Jindrak, Jan Hrach, Michal Staruch
3	* All rights reserved.
4	*
5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions
7	* are met:
8	*
9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.
16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/
28
29	/** @addtogroup drvusbxhci
30	* @{
31	*/
32	/** @file
33	* @brief The host controller data bookkeeping.
34	*/
35
36	#include <errno.h>
37	#include <str_error.h>
38	#include <usb/debug.h>
39	#include <usb/host/endpoint.h>
40	#include "debug.h"
41	#include "hc.h"
42	#include "rh.h"
43	#include "hw_struct/trb.h"
44	#include "hw_struct/context.h"
45	#include "endpoint.h"
46	#include "transfers.h"
47	#include "trb_ring.h"
48
49	/**
50	* Default USB Speed ID mapping: Table 157
51	*/
52	#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53	#define PORT_SPEED(usb, mjr, psie, psim) { \
54	.name = "USB ", \
55	.major = mjr, \
56	.minor = 0, \
57	.usb_speed = USB_SPEED_##usb, \
58	.rx_bps = PSI_TO_BPS(psie, psim), \
59	.tx_bps = PSI_TO_BPS(psie, psim) \
60	}
61
62	static const xhci_port_speed_t default_psiv_to_port_speed [] = {
63	[1] = PORT_SPEED(FULL, 2, 2, 12),
64	[2] = PORT_SPEED(LOW, 2, 1, 1500),
65	[3] = PORT_SPEED(HIGH, 2, 2, 480),
66	[4] = PORT_SPEED(SUPER, 3, 3, 5),
67	};
68
69	static const unsigned usb_speed_to_psiv [] = {
70	[USB_SPEED_FULL] = 1,
71	[USB_SPEED_LOW] = 2,
72	[USB_SPEED_HIGH] = 3,
73	[USB_SPEED_SUPER] = 4,
74	};
75
76	/**
77	* Walk the list of extended capabilities.
78	*
79	* The most interesting thing hidden in extended capabilities is the mapping of
80	* ports to protocol versions and speeds.
81	*/
82	static errno_t hc_parse_ec(xhci_hc_t *hc)
83	{
84	unsigned psic, major, minor;
85	xhci_sp_name_t name;
86
87	xhci_port_speed_t *speeds = hc->speeds;
88
89	for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
90	xhci_dump_extcap(ec);
91	switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
92	case XHCI_EC_USB_LEGACY:
93	assert(hc->legsup == NULL);
94	hc->legsup = (xhci_legsup_t *) ec;
95	break;
96	case XHCI_EC_SUPPORTED_PROTOCOL:
97	psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
98	major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
99	minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
100	name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
101
102	if (name.packed != xhci_name_usb.packed) {
103	/**
104	* The detection of such protocol would work,
105	* but the rest of the implementation is made
106	* for the USB protocol only.
107	*/
108	usb_log_error("Unknown protocol %.4s.", name.str);
109	return ENOTSUP;
110	}
111
112	unsigned offset = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
113	unsigned count = XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT);
114	xhci_rh_set_ports_protocol(&hc->rh, offset, count, major);
115
116	// "Implied" speed
117	if (psic == 0) {
118	assert(minor == 0);
119
120	if (major == 2) {
121	speeds[1] = default_psiv_to_port_speed[1];
122	speeds[2] = default_psiv_to_port_speed[2];
123	speeds[3] = default_psiv_to_port_speed[3];
124	} else if (major == 3) {
125	speeds[4] = default_psiv_to_port_speed[4];
126	} else {
127	return EINVAL;
128	}
129
130	usb_log_debug("Implied speed of USB %u.0 set up.", major);
131	} else {
132	for (unsigned i = 0; i < psic; i++) {
133	xhci_psi_t *psi = xhci_extcap_psi(ec, i);
134	unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
135	unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
136	unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
137	unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
138	uint64_t bps = PSI_TO_BPS(psie, psim);
139
140	/*
141	* Speed is not implied, but using one of default PSIV. This
142	* is not clearly stated in xHCI spec. There is a clear
143	* intention to allow xHCI to specify its own speed
144	* parameters, but throughout the document, they used fixed
145	* values for e.g. High-speed (3), without stating the
146	* controller shall have implied default speeds - and for
147	* instance Intel controllers do not. So let's check if the
148	* values match and if so, accept the implied USB speed too.
149	*
150	* The main reason we need this is the usb_speed to have
151	* mapping also for devices connected to hubs.
152	*/
153	if (psiv < ARRAY_SIZE(default_psiv_to_port_speed) &&
154	default_psiv_to_port_speed[psiv].major == major &&
155	default_psiv_to_port_speed[psiv].minor == minor &&
156	default_psiv_to_port_speed[psiv].rx_bps == bps &&
157	default_psiv_to_port_speed[psiv].tx_bps == bps) {
158	speeds[psiv] = default_psiv_to_port_speed[psiv];
159	usb_log_debug("Assumed default %s speed of USB %u.",
160	usb_str_speed(speeds[psiv].usb_speed), major);
161	continue;
162	}
163
164	// Custom speed
165	speeds[psiv].major = major;
166	speeds[psiv].minor = minor;
167	str_ncpy(speeds[psiv].name, 4, name.str, 4);
168	speeds[psiv].usb_speed = USB_SPEED_MAX;
169
170	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_RX)
171	speeds[psiv].rx_bps = bps;
172	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_TX) {
173	speeds[psiv].tx_bps = bps;
174	usb_log_debug("Speed %u set up for bps %" PRIu64
175	" / %" PRIu64 ".", psiv, speeds[psiv].rx_bps,
176	speeds[psiv].tx_bps);
177	}
178	}
179	}
180	}
181	}
182	return EOK;
183	}
184
185	/**
186	* Initialize MMIO spaces of xHC.
187	*/
188	errno_t hc_init_mmio(xhci_hc_t hc, const hw_res_list_parsed_t hw_res)
189	{
190	errno_t err;
191
192	if (hw_res->mem_ranges.count != 1) {
193	usb_log_error("Unexpected MMIO area, bailing out.");
194	return EINVAL;
195	}
196
197	hc->mmio_range = hw_res->mem_ranges.ranges[0];
198
199	usb_log_debug("MMIO area at %p (size %zu), IRQ %d.",
200	RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
201
202	if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
203	return EOVERFLOW;
204
205	void *base;
206	if ((err = pio_enable_range(&hc->mmio_range, &base)))
207	return err;
208
209	hc->reg_base = base;
210	hc->cap_regs = (xhci_cap_regs_t *) base;
211	hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
212	hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
213	hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
214
215	uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
216	if (xec_offset > 0)
217	hc->xecp = (xhci_extcap_t *) (base + xec_offset);
218
219	usb_log_debug("Initialized MMIO reg areas:");
220	usb_log_debug("\tCapability regs: %p", hc->cap_regs);
221	usb_log_debug("\tOperational regs: %p", hc->op_regs);
222	usb_log_debug("\tRuntime regs: %p", hc->rt_regs);
223	usb_log_debug("\tDoorbell array base: %p", hc->db_arry);
224
225	xhci_dump_cap_regs(hc->cap_regs);
226
227	hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
228	hc->csz = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_CSZ);
229	hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
230
231	struct timespec ts;
232	getuptime(&ts);
233	hc->wrap_time = SEC2USEC(ts.tv_sec) + NSEC2USEC(ts.tv_nsec);
234	hc->wrap_count = 0;
235
236	unsigned ist = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_IST);
237	hc->ist = (ist & 0x10 >> 1) * (ist & 0xf);
238
239	if ((err = xhci_rh_init(&hc->rh, hc)))
240	goto err_pio;
241
242	if ((err = hc_parse_ec(hc)))
243	goto err_rh;
244
245	return EOK;
246
247	err_rh:
248	xhci_rh_fini(&hc->rh);
249	err_pio:
250	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
251	return err;
252	}
253
254	static int event_worker(void *arg);
255
256	/**
257	* Initialize structures kept in allocated memory.
258	*/
259	errno_t hc_init_memory(xhci_hc_t hc, ddf_dev_t device)
260	{
261	errno_t err = ENOMEM;
262
263	if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
264	return ENOMEM;
265	hc->dcbaa = hc->dcbaa_dma.virt;
266
267	hc->event_worker = joinable_fibril_create(&event_worker, hc);
268	if (!hc->event_worker)
269	goto err_dcbaa;
270
271	if ((err = xhci_event_ring_init(&hc->event_ring, 1)))
272	goto err_worker;
273
274	if ((err = xhci_scratchpad_alloc(hc)))
275	goto err_event_ring;
276
277	if ((err = xhci_init_commands(hc)))
278	goto err_scratch;
279
280	if ((err = xhci_bus_init(&hc->bus, hc)))
281	goto err_cmd;
282
283	xhci_sw_ring_init(&hc->sw_ring, PAGE_SIZE / sizeof(xhci_trb_t));
284
285	return EOK;
286
287	err_cmd:
288	xhci_fini_commands(hc);
289	err_scratch:
290	xhci_scratchpad_free(hc);
291	err_event_ring:
292	xhci_event_ring_fini(&hc->event_ring);
293	err_worker:
294	joinable_fibril_destroy(hc->event_worker);
295	err_dcbaa:
296	hc->dcbaa = NULL;
297	dma_buffer_free(&hc->dcbaa_dma);
298	return err;
299	}
300
301	/*
302	* Pseudocode:
303	* ip = read(intr[0].iman)
304	* if (ip) {
305	* status = read(usbsts)
306	* assert status
307	* assert ip
308	* accept (passing status)
309	* }
310	* decline
311	*/
312	static const irq_cmd_t irq_commands[] = {
313	{
314	.cmd = CMD_PIO_READ_32,
315	.dstarg = 3,
316	.addr = NULL /* intr[0].iman */
317	},
318	{
319	.cmd = CMD_AND,
320	.srcarg = 3,
321	.dstarg = 4,
322	.value = 0 /* host2xhci(32, 1) */
323	},
324	{
325	.cmd = CMD_PREDICATE,
326	.srcarg = 4,
327	.value = 5
328	},
329	{
330	.cmd = CMD_PIO_READ_32,
331	.dstarg = 1,
332	.addr = NULL /* usbsts */
333	},
334	{
335	.cmd = CMD_AND,
336	.srcarg = 1,
337	.dstarg = 2,
338	.value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
339	},
340	{
341	.cmd = CMD_PIO_WRITE_A_32,
342	.srcarg = 2,
343	.addr = NULL /* usbsts */
344	},
345	{
346	.cmd = CMD_PIO_WRITE_A_32,
347	.srcarg = 3,
348	.addr = NULL /* intr[0].iman */
349	},
350	{
351	.cmd = CMD_ACCEPT
352	},
353	{
354	.cmd = CMD_DECLINE
355	}
356	};
357
358	/**
359	* Generates code to accept interrupts. The xHCI is designed primarily for
360	* MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
361	* (except 0) are disabled.
362	*/
363	errno_t hc_irq_code_gen(irq_code_t code, xhci_hc_t hc, const hw_res_list_parsed_t hw_res, int irq)
364	{
365	assert(code);
366	assert(hw_res);
367
368	if (hw_res->irqs.count != 1) {
369	usb_log_info("Unexpected HW resources to enable interrupts.");
370	return EINVAL;
371	}
372
373	code->ranges = malloc(sizeof(irq_pio_range_t));
374	if (code->ranges == NULL)
375	return ENOMEM;
376
377	code->cmds = malloc(sizeof(irq_commands));
378	if (code->cmds == NULL) {
379	free(code->ranges);
380	return ENOMEM;
381	}
382
383	code->rangecount = 1;
384	code->ranges[0] = (irq_pio_range_t) {
385	.base = RNGABS(hc->mmio_range),
386	.size = RNGSZ(hc->mmio_range),
387	};
388
389	code->cmdcount = ARRAY_SIZE(irq_commands);
390	memcpy(code->cmds, irq_commands, sizeof(irq_commands));
391
392	void *intr0_iman = RNGABSPTR(hc->mmio_range) +
393	XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) +
394	offsetof(xhci_rt_regs_t, ir[0]);
395	void *usbsts = RNGABSPTR(hc->mmio_range) +
396	XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) +
397	offsetof(xhci_op_regs_t, usbsts);
398
399	code->cmds[0].addr = intr0_iman;
400	code->cmds[1].value = host2xhci(32, 1);
401	code->cmds[3].addr = usbsts;
402	code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
403	code->cmds[5].addr = usbsts;
404	code->cmds[6].addr = intr0_iman;
405
406	*irq = hw_res->irqs.irqs[0];
407	return EOK;
408	}
409
410	/**
411	* Claim xHC from BIOS. Implements handoff as per Section 4.22.1 of xHCI spec.
412	*/
413	errno_t hc_claim(xhci_hc_t hc, ddf_dev_t dev)
414	{
415	/* No legacy support capability, the controller is solely for us */
416	if (!hc->legsup)
417	return EOK;
418
419	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
420	return ETIMEOUT;
421
422	usb_log_debug("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
423	XHCI_REG_SET(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
424	for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
425	usb_log_debug("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
426	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
427	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
428	if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
429	return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO;
430	}
431	fibril_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
432	}
433	usb_log_error("BIOS did not release XHCI legacy hold!");
434
435	return ENOTSUP;
436	}
437
438	/**
439	* Ask the xHC to reset its state. Implements sequence
440	*/
441	static errno_t hc_reset(xhci_hc_t *hc)
442	{
443	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
444	return ETIMEOUT;
445
446	/* Stop the HC: set R/S to 0 */
447	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
448
449	/* Wait until the HC is halted - it shall take at most 16 ms */
450	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
451	XHCI_REG_MASK(XHCI_OP_HCH)))
452	return ETIMEOUT;
453
454	/* Reset */
455	XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
456
457	/* Wait until the reset is complete */
458	if (xhci_reg_wait(&hc->op_regs->usbcmd, XHCI_REG_MASK(XHCI_OP_HCRST), 0))
459	return ETIMEOUT;
460
461	return EOK;
462	}
463
464	/**
465	* Initialize the HC: section 4.2
466	*/
467	errno_t hc_start(xhci_hc_t *hc)
468	{
469	errno_t err;
470
471	if ((err = hc_reset(hc)))
472	return err;
473
474	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
475	return ETIMEOUT;
476
477	uintptr_t dcbaa_phys = dma_buffer_phys_base(&hc->dcbaa_dma);
478	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP, dcbaa_phys);
479	XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
480
481	uintptr_t crcr;
482	xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
483	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR, crcr);
484
485	XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
486
487	xhci_event_ring_reset(&hc->event_ring);
488
489	xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
490	XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
491	XHCI_REG_WR(intr0, XHCI_INTR_ERDP, hc->event_ring.dequeue_ptr);
492
493	const uintptr_t erstba_phys = dma_buffer_phys_base(&hc->event_ring.erst);
494	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA, erstba_phys);
495
496	if (cap_handle_valid(hc->base.irq_handle)) {
497	XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
498	XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
499	}
500
501	XHCI_REG_SET(hc->op_regs, XHCI_OP_HSEE, 1);
502
503	xhci_sw_ring_restart(&hc->sw_ring);
504	joinable_fibril_start(hc->event_worker);
505
506	xhci_start_command_ring(hc);
507
508	XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
509
510	/* RH needs to access port states on startup */
511	xhci_rh_start(&hc->rh);
512
513	return EOK;
514	}
515
516	static void hc_stop(xhci_hc_t *hc)
517	{
518	/* Stop the HC in hardware. */
519	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
520
521	/*
522	* Wait until the HC is halted - it shall take at most 16 ms.
523	* Note that we ignore the return value here.
524	*/
525	xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
526	XHCI_REG_MASK(XHCI_OP_HCH));
527
528	/* Make sure commands will not block other fibrils. */
529	xhci_nuke_command_ring(hc);
530
531	/* Stop the event worker fibril to restart it */
532	xhci_sw_ring_stop(&hc->sw_ring);
533	joinable_fibril_join(hc->event_worker);
534
535	/*
536	* Then, disconnect all roothub devices, which shall trigger
537	* disconnection of everything
538	*/
539	xhci_rh_stop(&hc->rh);
540	}
541
542	static void hc_reinitialize(xhci_hc_t *hc)
543	{
544	/* Stop everything. */
545	hc_stop(hc);
546
547	usb_log_info("HC stopped. Starting again...");
548
549	/* The worker fibrils need to be started again */
550	joinable_fibril_recreate(hc->event_worker);
551	joinable_fibril_recreate(hc->rh.event_worker);
552
553	/* Now, the HC shall be stopped and software shall be clean. */
554	hc_start(hc);
555	}
556
557	static bool hc_is_broken(xhci_hc_t *hc)
558	{
559	const uint32_t usbcmd = XHCI_REG_RD_FIELD(&hc->op_regs->usbcmd, 32);
560	const uint32_t usbsts = XHCI_REG_RD_FIELD(&hc->op_regs->usbsts, 32);
561
562	return !(usbcmd & XHCI_REG_MASK(XHCI_OP_RS)) \|\|
563	(usbsts & XHCI_REG_MASK(XHCI_OP_HCE)) \|\|
564	(usbsts & XHCI_REG_MASK(XHCI_OP_HSE));
565	}
566
567	/**
568	* Used only when polling. Shall supplement the irq_commands.
569	*/
570	errno_t hc_status(bus_t bus, uint32_t status)
571	{
572	xhci_hc_t *hc = bus_to_hc(bus);
573	int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
574	if (ip) {
575	*status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
576	XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
577	XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
578
579	/*
580	* interrupt handler expects status from irq_commands, which is
581	* in xhci order.
582	*/
583	status = host2xhci(32, status);
584	}
585
586	usb_log_debug("Polled status: %x", *status);
587	return EOK;
588	}
589
590	static errno_t xhci_handle_mfindex_wrap_event(xhci_hc_t hc, xhci_trb_t trb)
591	{
592	struct timespec ts;
593	getuptime(&ts);
594	usb_log_debug("Microframe index wrapped (@%lld.%lld, %" PRIu64 " total).",
595	ts.tv_sec, NSEC2USEC(ts.tv_nsec), hc->wrap_count);
596	hc->wrap_time = SEC2USEC(ts.tv_sec) + NSEC2USEC(ts.tv_nsec);
597	++hc->wrap_count;
598	return EOK;
599	}
600
601	typedef errno_t (event_handler) (xhci_hc_t , xhci_trb_t *trb);
602
603	/**
604	* These events are handled by separate event handling fibril.
605	*/
606	static event_handler event_handlers [] = {
607	[XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
608	};
609
610	/**
611	* These events are handled directly in the interrupt handler, thus they must
612	* not block waiting for another interrupt.
613	*/
614	static event_handler event_handlers_fast [] = {
615	[XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
616	[XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT] = &xhci_handle_mfindex_wrap_event,
617	};
618
619	static errno_t hc_handle_event(xhci_hc_t hc, xhci_trb_t trb)
620	{
621	const unsigned type = TRB_TYPE(*trb);
622
623	if (type <= ARRAY_SIZE(event_handlers_fast) && event_handlers_fast[type])
624	return event_handlers_fast[type](hc, trb);
625
626	if (type <= ARRAY_SIZE(event_handlers) && event_handlers[type])
627	return xhci_sw_ring_enqueue(&hc->sw_ring, trb);
628
629	if (type == XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT)
630	return xhci_sw_ring_enqueue(&hc->rh.event_ring, trb);
631
632	return ENOTSUP;
633	}
634
635	static int event_worker(void *arg)
636	{
637	errno_t err;
638	xhci_trb_t trb;
639	xhci_hc_t *const hc = arg;
640	assert(hc);
641
642	while (xhci_sw_ring_dequeue(&hc->sw_ring, &trb) != EINTR) {
643	const unsigned type = TRB_TYPE(trb);
644
645	if ((err = event_handlers[type](hc, &trb)))
646	usb_log_error("Failed to handle event: %s", str_error(err));
647	}
648
649	return 0;
650	}
651
652	/**
653	* Dequeue from event ring and handle dequeued events.
654	*
655	* As there can be events, that blocks on waiting for subsequent events,
656	* we solve this problem by deferring some types of events to separate fibrils.
657	*/
658	static void hc_run_event_ring(xhci_hc_t hc, xhci_event_ring_t event_ring,
659	xhci_interrupter_regs_t *intr)
660	{
661	errno_t err;
662
663	xhci_trb_t trb;
664	hc->event_handler = fibril_get_id();
665
666	while ((err = xhci_event_ring_dequeue(event_ring, &trb)) != ENOENT) {
667	if ((err = hc_handle_event(hc, &trb)) != EOK) {
668	usb_log_error("Failed to handle event in interrupt: %s", str_error(err));
669	}
670
671	XHCI_REG_WR(intr, XHCI_INTR_ERDP, hc->event_ring.dequeue_ptr);
672	}
673
674	hc->event_handler = 0;
675
676	uint64_t erdp = hc->event_ring.dequeue_ptr;
677	erdp \|= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
678	XHCI_REG_WR(intr, XHCI_INTR_ERDP, erdp);
679
680	usb_log_debug2("Event ring run finished.");
681	}
682
683	/**
684	* Handle an interrupt request from xHC. Resolve all situations that trigger an
685	* interrupt separately.
686	*
687	* Note that all RW1C bits in USBSTS register are cleared at the time of
688	* handling the interrupt in irq_code. This method is the top-half.
689	*
690	* @param status contents of USBSTS register at the time of the interrupt.
691	*/
692	void hc_interrupt(bus_t *bus, uint32_t status)
693	{
694	xhci_hc_t *hc = bus_to_hc(bus);
695	status = xhci2host(32, status);
696
697	if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
698	usb_log_error("Host system error occured. Aren't we supposed to be dead already?");
699	return;
700	}
701
702	if (status & XHCI_REG_MASK(XHCI_OP_HCE)) {
703	usb_log_error("Host controller error occured. Reinitializing...");
704	hc_reinitialize(hc);
705	return;
706	}
707
708	if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
709	usb_log_debug2("Event interrupt, running the event ring.");
710	hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
711	status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
712	}
713
714	if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
715	usb_log_error("Save/Restore error occured. WTF, "
716	"S/R mechanism not implemented!");
717	status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
718	}
719
720	/* According to Note on p. 302, we may safely ignore the PCD bit. */
721	status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
722
723	if (status) {
724	usb_log_error("Non-zero status after interrupt handling (%08x) "
725	" - missing something?", status);
726	}
727	}
728
729	/**
730	* Tear down all in-memory structures.
731	*/
732	void hc_fini(xhci_hc_t *hc)
733	{
734	hc_stop(hc);
735
736	xhci_sw_ring_fini(&hc->sw_ring);
737	joinable_fibril_destroy(hc->event_worker);
738	xhci_bus_fini(&hc->bus);
739	xhci_event_ring_fini(&hc->event_ring);
740	xhci_scratchpad_free(hc);
741	dma_buffer_free(&hc->dcbaa_dma);
742	xhci_fini_commands(hc);
743	xhci_rh_fini(&hc->rh);
744	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
745	usb_log_info("Finalized.");
746	}
747
748	unsigned hc_speed_to_psiv(usb_speed_t speed)
749	{
750	assert(speed < ARRAY_SIZE(usb_speed_to_psiv));
751	return usb_speed_to_psiv[speed];
752	}
753
754	/**
755	* Ring a xHC Doorbell. Implements section 4.7.
756	*/
757	void hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
758	{
759	assert(hc);
760	uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
761	pio_write_32(&hc->db_arry[doorbell], v);
762	usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
763	}
764
765	/**
766	* Return an index to device context.
767	*/
768	static uint8_t endpoint_dci(xhci_endpoint_t *ep)
769	{
770	return (2 * ep->base.endpoint) +
771	(ep->base.transfer_type == USB_TRANSFER_CONTROL \|\|
772	ep->base.direction == USB_DIRECTION_IN);
773	}
774
775	void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id)
776	{
777	xhci_device_t *const dev = xhci_ep_to_dev(ep);
778	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
779	const uint8_t dci = endpoint_dci(ep);
780	const uint32_t target = (stream_id << 16) \| (dci & 0x1ff);
781	hc_ring_doorbell(hc, dev->slot_id, target);
782	}
783
784	/**
785	* Issue an Enable Slot command. Allocate memory for the slot and fill the
786	* DCBAA with the newly created slot.
787	*/
788	errno_t hc_enable_slot(xhci_device_t *dev)
789	{
790	errno_t err;
791	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
792
793	/* Prepare memory for the context */
794	if ((err = dma_buffer_alloc(&dev->dev_ctx, XHCI_DEVICE_CTX_SIZE(hc))))
795	return err;
796	memset(dev->dev_ctx.virt, 0, XHCI_DEVICE_CTX_SIZE(hc));
797
798	/* Get the slot number */
799	xhci_cmd_t cmd;
800	xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
801
802	err = xhci_cmd_sync(hc, &cmd);
803
804	/* Link them together */
805	if (err == EOK) {
806	dev->slot_id = cmd.slot_id;
807	hc->dcbaa[dev->slot_id] =
808	host2xhci(64, dma_buffer_phys_base(&dev->dev_ctx));
809	}
810
811	xhci_cmd_fini(&cmd);
812
813	if (err)
814	dma_buffer_free(&dev->dev_ctx);
815
816	return err;
817	}
818
819	/**
820	* Issue a Disable Slot command for a slot occupied by device.
821	* Frees the device context.
822	*/
823	errno_t hc_disable_slot(xhci_device_t *dev)
824	{
825	errno_t err;
826	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
827	xhci_cmd_t cmd;
828
829	xhci_cmd_init(&cmd, XHCI_CMD_DISABLE_SLOT);
830	cmd.slot_id = dev->slot_id;
831	err = xhci_cmd_sync(hc, &cmd);
832	xhci_cmd_fini(&cmd);
833	if (err != EOK)
834	return err;
835
836	/* Free the device context. */
837	hc->dcbaa[dev->slot_id] = 0;
838	dma_buffer_free(&dev->dev_ctx);
839
840	/* Mark the slot as invalid. */
841	dev->slot_id = 0;
842
843	return EOK;
844	}
845
846	/**
847	* Prepare an empty Endpoint Input Context inside a dma buffer.
848	*/
849	static errno_t create_configure_ep_input_ctx(xhci_device_t dev, dma_buffer_t dma_buf)
850	{
851	const xhci_hc_t *hc = bus_to_hc(dev->base.bus);
852	const errno_t err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc));
853	if (err)
854	return err;
855
856	xhci_input_ctx_t *ictx = dma_buf->virt;
857	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
858
859	// Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
860	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 0);
861	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
862	xhci_setup_slot_context(dev, slot_ctx);
863
864	return EOK;
865	}
866
867	/**
868	* Initialize a device, assigning it an address. Implements section 4.3.4.
869	*
870	* @param dev Device to assing an address (unconfigured yet)
871	*/
872	errno_t hc_address_device(xhci_device_t *dev)
873	{
874	errno_t err = ENOMEM;
875	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
876	xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]);
877
878	/*
879	* Although we have the precise PSIV value on devices of tier 1,
880	* we have to rely on reverse mapping on others.
881	*/
882	if (!usb_speed_to_psiv[dev->base.speed]) {
883	usb_log_error("Device reported an USB speed (%s) that cannot be mapped "
884	"to HC port speed.", usb_str_speed(dev->base.speed));
885	return EINVAL;
886	}
887
888	/* Issue configure endpoint command (sec 4.3.5). */
889	dma_buffer_t ictx_dma_buf;
890	if ((err = create_configure_ep_input_ctx(dev, &ictx_dma_buf)))
891	return err;
892	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
893
894	/* Copy endpoint 0 context and set A1 flag. */
895	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 1);
896	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, 1);
897	xhci_setup_endpoint_context(ep0, ep_ctx);
898
899	/* Address device needs Ctx entries set to 1 only */
900	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
901	XHCI_SLOT_CTX_ENTRIES_SET(*slot_ctx, 1);
902
903	/* Issue Address Device command. */
904	xhci_cmd_t cmd;
905	xhci_cmd_init(&cmd, XHCI_CMD_ADDRESS_DEVICE);
906	cmd.slot_id = dev->slot_id;
907	cmd.input_ctx = ictx_dma_buf;
908	err = xhci_cmd_sync(hc, &cmd);
909	xhci_cmd_fini(&cmd);
910	if (err != EOK)
911	return err;
912
913	xhci_device_ctx_t *device_ctx = dev->dev_ctx.virt;
914	dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(*XHCI_GET_SLOT_CTX(device_ctx, hc));
915	usb_log_debug("Obtained USB address: %d.", dev->base.address);
916
917	return EOK;
918	}
919
920	/**
921	* Issue a Configure Device command for a device in slot.
922	*
923	* @param slot_id Slot ID assigned to the device.
924	*/
925	errno_t hc_configure_device(xhci_device_t *dev)
926	{
927	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
928	xhci_cmd_t cmd;
929
930	/* Issue configure endpoint command (sec 4.3.5). */
931	dma_buffer_t ictx_dma_buf;
932	errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
933	if (err != EOK)
934	return err;
935
936	xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT);
937	cmd.slot_id = dev->slot_id;
938	cmd.input_ctx = ictx_dma_buf;
939	err = xhci_cmd_sync(hc, &cmd);
940	xhci_cmd_fini(&cmd);
941
942	return err;
943	}
944
945	/**
946	* Issue a Deconfigure Device command for a device in slot.
947	*
948	* @param dev The owner of the device
949	*/
950	errno_t hc_deconfigure_device(xhci_device_t *dev)
951	{
952	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
953	xhci_cmd_t cmd;
954	errno_t err;
955
956	if (hc_is_broken(hc))
957	return EOK;
958
959	/* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
960	xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT);
961	cmd.slot_id = dev->slot_id;
962	cmd.deconfigure = true;
963
964	err = xhci_cmd_sync(hc, &cmd);
965	xhci_cmd_fini(&cmd);
966
967	return err;
968	}
969
970	/**
971	* Instruct xHC to add an endpoint with supplied endpoint context.
972	*
973	* @param dev The owner of the device
974	* @param ep_idx Endpoint DCI in question
975	* @param ep_ctx Endpoint context of the endpoint
976	*/
977	errno_t hc_add_endpoint(xhci_endpoint_t *ep)
978	{
979	xhci_device_t *const dev = xhci_ep_to_dev(ep);
980	const unsigned dci = endpoint_dci(ep);
981	xhci_cmd_t cmd;
982
983	/* Issue configure endpoint command (sec 4.3.5). */
984	dma_buffer_t ictx_dma_buf;
985	errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
986	if (err != EOK)
987	return err;
988
989	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
990
991	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
992	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
993
994	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
995	xhci_setup_endpoint_context(ep, ep_ctx);
996
997	xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT);
998	cmd.slot_id = dev->slot_id;
999	cmd.input_ctx = ictx_dma_buf;
1000	err = xhci_cmd_sync(hc, &cmd);
1001	xhci_cmd_fini(&cmd);
1002
1003	return err;
1004	}
1005
1006	/**
1007	* Instruct xHC to drop an endpoint.
1008	*
1009	* @param dev The owner of the endpoint
1010	* @param ep_idx Endpoint DCI in question
1011	*/
1012	errno_t hc_drop_endpoint(xhci_endpoint_t *ep)
1013	{
1014	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1015	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1016	const unsigned dci = endpoint_dci(ep);
1017	xhci_cmd_t cmd;
1018
1019	if (hc_is_broken(hc))
1020	return EOK;
1021
1022	/* Issue configure endpoint command (sec 4.3.5). */
1023	dma_buffer_t ictx_dma_buf;
1024	errno_t err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
1025	if (err != EOK)
1026	return err;
1027
1028	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
1029	XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
1030
1031	xhci_cmd_init(&cmd, XHCI_CMD_CONFIGURE_ENDPOINT);
1032	cmd.slot_id = dev->slot_id;
1033	cmd.input_ctx = ictx_dma_buf;
1034	err = xhci_cmd_sync(hc, &cmd);
1035	xhci_cmd_fini(&cmd);
1036
1037	return err;
1038	}
1039
1040	/**
1041	* Instruct xHC to update information about an endpoint, using supplied
1042	* endpoint context.
1043	*
1044	* @param dev The owner of the endpoint
1045	* @param ep_idx Endpoint DCI in question
1046	* @param ep_ctx Endpoint context of the endpoint
1047	*/
1048	errno_t hc_update_endpoint(xhci_endpoint_t *ep)
1049	{
1050	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1051	const unsigned dci = endpoint_dci(ep);
1052	xhci_cmd_t cmd;
1053
1054	dma_buffer_t ictx_dma_buf;
1055	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1056
1057	errno_t err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));
1058	if (err != EOK)
1059	return err;
1060
1061	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
1062	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
1063
1064	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
1065	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
1066	xhci_setup_endpoint_context(ep, ep_ctx);
1067
1068	xhci_cmd_init(&cmd, XHCI_CMD_EVALUATE_CONTEXT);
1069	cmd.slot_id = dev->slot_id;
1070	cmd.input_ctx = ictx_dma_buf;
1071	err = xhci_cmd_sync(hc, &cmd);
1072	xhci_cmd_fini(&cmd);
1073
1074	return err;
1075	}
1076
1077	/**
1078	* Instruct xHC to stop running a transfer ring on an endpoint.
1079	*
1080	* @param dev The owner of the endpoint
1081	* @param ep_idx Endpoint DCI in question
1082	*/
1083	errno_t hc_stop_endpoint(xhci_endpoint_t *ep)
1084	{
1085	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1086	const unsigned dci = endpoint_dci(ep);
1087	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1088	xhci_cmd_t cmd;
1089	errno_t err;
1090
1091	if (hc_is_broken(hc))
1092	return EOK;
1093
1094	xhci_cmd_init(&cmd, XHCI_CMD_STOP_ENDPOINT);
1095	cmd.slot_id = dev->slot_id;
1096	cmd.endpoint_id = dci;
1097	err = xhci_cmd_sync(hc, &cmd);
1098	xhci_cmd_fini(&cmd);
1099
1100	return err;
1101	}
1102
1103	/**
1104	* Instruct xHC to reset halted endpoint.
1105	*
1106	* @param dev The owner of the endpoint
1107	* @param ep_idx Endpoint DCI in question
1108	*/
1109	errno_t hc_reset_endpoint(xhci_endpoint_t *ep)
1110	{
1111	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1112	const unsigned dci = endpoint_dci(ep);
1113	xhci_hc_t *const hc = bus_to_hc(dev->base.bus);
1114	xhci_cmd_t cmd;
1115	errno_t err;
1116
1117	xhci_cmd_init(&cmd, XHCI_CMD_RESET_ENDPOINT);
1118	cmd.slot_id = dev->slot_id;
1119	cmd.endpoint_id = dci;
1120	err = xhci_cmd_sync(hc, &cmd);
1121	xhci_cmd_fini(&cmd);
1122
1123	return err;
1124	}
1125
1126	/**
1127	* Reset a ring position in both software and hardware.
1128	*
1129	* @param dev The owner of the endpoint
1130	*/
1131	errno_t hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id)
1132	{
1133	xhci_device_t *const dev = xhci_ep_to_dev(ep);
1134	const unsigned dci = endpoint_dci(ep);
1135	uintptr_t addr;
1136	xhci_cmd_t cmd;
1137	errno_t err;
1138
1139	xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id);
1140	xhci_trb_ring_reset_dequeue_state(ring, &addr);
1141
1142	xhci_hc_t *const hc = bus_to_hc(endpoint_get_bus(&ep->base));
1143
1144	xhci_cmd_init(&cmd, XHCI_CMD_SET_TR_DEQUEUE_POINTER);
1145	cmd.slot_id = dev->slot_id;
1146	cmd.endpoint_id = dci;
1147	cmd.stream_id = stream_id;
1148	cmd.dequeue_ptr = addr;
1149	err = xhci_cmd_sync(hc, &cmd);
1150	xhci_cmd_fini(&cmd);
1151
1152	return err;
1153	}
1154
1155	/**
1156	* @}
1157	*/

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 5a68791

Download in other formats: