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Last change on this file since 4d12eda was 4d12eda, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: transfer events must be fast

When a roothub connected device is disconnected during enumeration,
it may wait for the descriptor read, but the event is blocked by fibril
waiting until the enumeration finishes.

Property mode set to 100644

File size: 29.5 KB

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1	/*
2	* Copyright (c) 2017 Ondrej Hlavaty
3	* All rights reserved.
4	*
5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions
7	* are met:
8	*
9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.
16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/
28
29	/** @addtogroup drvusbxhci
30	* @{
31	*/
32	/** @file
33	* @brief The host controller data bookkeeping.
34	*/
35
36	#include <errno.h>
37	#include <str_error.h>
38	#include <usb/debug.h>
39	#include <usb/host/endpoint.h>
40	#include "debug.h"
41	#include "hc.h"
42	#include "rh.h"
43	#include "hw_struct/trb.h"
44	#include "hw_struct/context.h"
45	#include "endpoint.h"
46	#include "transfers.h"
47	#include "trb_ring.h"
48
49	/**
50	* Default USB Speed ID mapping: Table 157
51	*/
52	#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53	#define PORT_SPEED(usb, mjr, psie, psim) { \
54	.name = "USB ", \
55	.major = mjr, \
56	.minor = 0, \
57	.usb_speed = USB_SPEED_##usb, \
58	.rx_bps = PSI_TO_BPS(psie, psim), \
59	.tx_bps = PSI_TO_BPS(psie, psim) \
60	}
61
62	static const xhci_port_speed_t default_psiv_to_port_speed [] = {
63	[1] = PORT_SPEED(FULL, 2, 2, 12),
64	[2] = PORT_SPEED(LOW, 2, 1, 1500),
65	[3] = PORT_SPEED(HIGH, 2, 2, 480),
66	[4] = PORT_SPEED(SUPER, 3, 3, 5),
67	};
68
69	static const unsigned usb_speed_to_psiv [] = {
70	[USB_SPEED_FULL] = 1,
71	[USB_SPEED_LOW] = 2,
72	[USB_SPEED_HIGH] = 3,
73	[USB_SPEED_SUPER] = 4,
74	};
75
76	/**
77	* Walk the list of extended capabilities.
78	*
79	* The most interesting thing hidden in extended capabilities is the mapping of
80	* ports to protocol versions and speeds.
81	*/
82	static int hc_parse_ec(xhci_hc_t *hc)
83	{
84	unsigned psic, major, minor;
85	xhci_sp_name_t name;
86
87	xhci_port_speed_t *speeds = hc->speeds;
88
89	for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
90	xhci_dump_extcap(ec);
91	switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
92	case XHCI_EC_USB_LEGACY:
93	assert(hc->legsup == NULL);
94	hc->legsup = (xhci_legsup_t *) ec;
95	break;
96	case XHCI_EC_SUPPORTED_PROTOCOL:
97	psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
98	major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
99	minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
100	name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
101
102	if (name.packed != xhci_name_usb.packed) {
103	/**
104	* The detection of such protocol would work,
105	* but the rest of the implementation is made
106	* for the USB protocol only.
107	*/
108	usb_log_error("Unknown protocol %.4s.", name.str);
109	return ENOTSUP;
110	}
111
112	unsigned offset = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
113	unsigned count = XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT);
114	xhci_rh_set_ports_protocol(&hc->rh, offset, count, major);
115
116	// "Implied" speed
117	if (psic == 0) {
118	assert(minor == 0);
119
120	if (major == 2) {
121	speeds[1] = default_psiv_to_port_speed[1];
122	speeds[2] = default_psiv_to_port_speed[2];
123	speeds[3] = default_psiv_to_port_speed[3];
124	} else if (major == 3) {
125	speeds[4] = default_psiv_to_port_speed[4];
126	} else {
127	return EINVAL;
128	}
129
130	usb_log_debug("Implied speed of USB %u.0 set up.", major);
131	} else {
132	for (unsigned i = 0; i < psic; i++) {
133	xhci_psi_t *psi = xhci_extcap_psi(ec, i);
134	unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
135	unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
136	unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
137	unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
138	uint64_t bps = PSI_TO_BPS(psie, psim);
139
140	/*
141	* Speed is not implied, but using one of default PSIV. This
142	* is not clearly stated in xHCI spec. There is a clear
143	* intention to allow xHCI to specify its own speed
144	* parameters, but throughout the document, they used fixed
145	* values for e.g. High-speed (3), without stating the
146	* controller shall have implied default speeds - and for
147	* instance Intel controllers do not. So let's check if the
148	* values match and if so, accept the implied USB speed too.
149	*
150	* The main reason we need this is the usb_speed to have
151	* mapping also for devices connected to hubs.
152	*/
153	if (psiv < ARRAY_SIZE(default_psiv_to_port_speed)
154	&& default_psiv_to_port_speed[psiv].major == major
155	&& default_psiv_to_port_speed[psiv].minor == minor
156	&& default_psiv_to_port_speed[psiv].rx_bps == bps
157	&& default_psiv_to_port_speed[psiv].tx_bps == bps) {
158	speeds[psiv] = default_psiv_to_port_speed[psiv];
159	usb_log_debug("Assumed default %s speed of USB %u.",
160	usb_str_speed(speeds[psiv].usb_speed), major);
161	continue;
162	}
163
164	// Custom speed
165	speeds[psiv].major = major;
166	speeds[psiv].minor = minor;
167	str_ncpy(speeds[psiv].name, 4, name.str, 4);
168	speeds[psiv].usb_speed = USB_SPEED_MAX;
169
170	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_RX)
171	speeds[psiv].rx_bps = bps;
172	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_TX) {
173	speeds[psiv].tx_bps = bps;
174	usb_log_debug("Speed %u set up for bps %" PRIu64
175	" / %" PRIu64 ".", psiv, speeds[psiv].rx_bps,
176	speeds[psiv].tx_bps);
177	}
178	}
179	}
180	}
181	}
182	return EOK;
183	}
184
185	/**
186	* Initialize MMIO spaces of xHC.
187	*/
188	int hc_init_mmio(xhci_hc_t hc, const hw_res_list_parsed_t hw_res)
189	{
190	int err;
191
192	if (hw_res->mem_ranges.count != 1) {
193	usb_log_error("Unexpected MMIO area, bailing out.");
194	return EINVAL;
195	}
196
197	hc->mmio_range = hw_res->mem_ranges.ranges[0];
198
199	usb_log_debug("MMIO area at %p (size %zu), IRQ %d.",
200	RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
201
202	if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
203	return EOVERFLOW;
204
205	void *base;
206	if ((err = pio_enable_range(&hc->mmio_range, &base)))
207	return err;
208
209	hc->reg_base = base;
210	hc->cap_regs = (xhci_cap_regs_t *) base;
211	hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
212	hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
213	hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
214
215	uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
216	if (xec_offset > 0)
217	hc->xecp = (xhci_extcap_t *) (base + xec_offset);
218
219	usb_log_debug("Initialized MMIO reg areas:");
220	usb_log_debug("\tCapability regs: %p", hc->cap_regs);
221	usb_log_debug("\tOperational regs: %p", hc->op_regs);
222	usb_log_debug("\tRuntime regs: %p", hc->rt_regs);
223	usb_log_debug("\tDoorbell array base: %p", hc->db_arry);
224
225	xhci_dump_cap_regs(hc->cap_regs);
226
227	hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
228	hc->csz = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_CSZ);
229	hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
230
231	struct timeval tv;
232	getuptime(&tv);
233	hc->wrap_time = tv.tv_sec * 1000000 + tv.tv_usec;
234	hc->wrap_count = 0;
235
236	unsigned ist = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_IST);
237	hc->ist = (ist & 0x10 >> 1) * (ist & 0xf);
238
239	if ((err = xhci_rh_init(&hc->rh, hc)))
240	goto err_pio;
241
242	if ((err = hc_parse_ec(hc)))
243	goto err_rh;
244
245	return EOK;
246
247	err_rh:
248	xhci_rh_fini(&hc->rh);
249	err_pio:
250	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
251	return err;
252	}
253
254	static int event_worker(void *arg);
255
256	/**
257	* Initialize structures kept in allocated memory.
258	*/
259	int hc_init_memory(xhci_hc_t hc, ddf_dev_t device)
260	{
261	int err;
262
263	if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
264	return ENOMEM;
265	hc->dcbaa = hc->dcbaa_dma.virt;
266
267	if ((err = xhci_event_ring_init(&hc->event_ring, 1)))
268	goto err_dcbaa;
269
270	if ((err = xhci_scratchpad_alloc(hc)))
271	goto err_event_ring;
272
273	if ((err = xhci_init_commands(hc)))
274	goto err_scratch;
275
276	if ((err = xhci_bus_init(&hc->bus, hc)))
277	goto err_cmd;
278
279	fid_t fid = fibril_create(&event_worker, hc);
280	if (!fid)
281	goto err_bus;
282
283	// TODO: completion_reset
284	hc->event_fibril_completion.active = true;
285	fibril_mutex_initialize(&hc->event_fibril_completion.guard);
286	fibril_condvar_initialize(&hc->event_fibril_completion.cv);
287
288	xhci_sw_ring_init(&hc->sw_ring, PAGE_SIZE / sizeof(xhci_trb_t));
289
290	fibril_add_ready(fid);
291
292	return EOK;
293
294	err_bus:
295	xhci_bus_fini(&hc->bus);
296	err_cmd:
297	xhci_fini_commands(hc);
298	err_scratch:
299	xhci_scratchpad_free(hc);
300	err_event_ring:
301	xhci_event_ring_fini(&hc->event_ring);
302	err_dcbaa:
303	hc->dcbaa = NULL;
304	dma_buffer_free(&hc->dcbaa_dma);
305	return err;
306	}
307
308	/*
309	* Pseudocode:
310	* ip = read(intr[0].iman)
311	* if (ip) {
312	* status = read(usbsts)
313	* assert status
314	* assert ip
315	* accept (passing status)
316	* }
317	* decline
318	*/
319	static const irq_cmd_t irq_commands[] = {
320	{
321	.cmd = CMD_PIO_READ_32,
322	.dstarg = 3,
323	.addr = NULL /* intr[0].iman */
324	},
325	{
326	.cmd = CMD_AND,
327	.srcarg = 3,
328	.dstarg = 4,
329	.value = 0 /* host2xhci(32, 1) */
330	},
331	{
332	.cmd = CMD_PREDICATE,
333	.srcarg = 4,
334	.value = 5
335	},
336	{
337	.cmd = CMD_PIO_READ_32,
338	.dstarg = 1,
339	.addr = NULL /* usbsts */
340	},
341	{
342	.cmd = CMD_AND,
343	.srcarg = 1,
344	.dstarg = 2,
345	.value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
346	},
347	{
348	.cmd = CMD_PIO_WRITE_A_32,
349	.srcarg = 2,
350	.addr = NULL /* usbsts */
351	},
352	{
353	.cmd = CMD_PIO_WRITE_A_32,
354	.srcarg = 3,
355	.addr = NULL /* intr[0].iman */
356	},
357	{
358	.cmd = CMD_ACCEPT
359	},
360	{
361	.cmd = CMD_DECLINE
362	}
363	};
364
365
366	/**
367	* Generates code to accept interrupts. The xHCI is designed primarily for
368	* MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
369	* (except 0) are disabled.
370	*/
371	int hc_irq_code_gen(irq_code_t code, xhci_hc_t hc, const hw_res_list_parsed_t *hw_res)
372	{
373	assert(code);
374	assert(hw_res);
375
376	if (hw_res->irqs.count != 1) {
377	usb_log_info("Unexpected HW resources to enable interrupts.");
378	return EINVAL;
379	}
380
381	code->ranges = malloc(sizeof(irq_pio_range_t));
382	if (code->ranges == NULL)
383	return ENOMEM;
384
385	code->cmds = malloc(sizeof(irq_commands));
386	if (code->cmds == NULL) {
387	free(code->ranges);
388	return ENOMEM;
389	}
390
391	code->rangecount = 1;
392	code->ranges[0] = (irq_pio_range_t) {
393	.base = RNGABS(hc->mmio_range),
394	.size = RNGSZ(hc->mmio_range),
395	};
396
397	code->cmdcount = ARRAY_SIZE(irq_commands);
398	memcpy(code->cmds, irq_commands, sizeof(irq_commands));
399
400	void *intr0_iman = RNGABSPTR(hc->mmio_range)
401	+ XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF)
402	+ offsetof(xhci_rt_regs_t, ir[0]);
403	void *usbsts = RNGABSPTR(hc->mmio_range)
404	+ XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH)
405	+ offsetof(xhci_op_regs_t, usbsts);
406
407	code->cmds[0].addr = intr0_iman;
408	code->cmds[1].value = host2xhci(32, 1);
409	code->cmds[3].addr = usbsts;
410	code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
411	code->cmds[5].addr = usbsts;
412	code->cmds[6].addr = intr0_iman;
413
414	return hw_res->irqs.irqs[0];
415	}
416
417	/**
418	* Claim xHC from BIOS. Implements handoff as per Section 4.22.1 of xHCI spec.
419	*/
420	int hc_claim(xhci_hc_t hc, ddf_dev_t dev)
421	{
422	/* No legacy support capability, the controller is solely for us */
423	if (!hc->legsup)
424	return EOK;
425
426	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
427	return ETIMEOUT;
428
429	usb_log_debug("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
430	XHCI_REG_SET(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
431	for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
432	usb_log_debug("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
433	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
434	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
435	if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
436	return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO;
437	}
438	async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
439	}
440	usb_log_error("BIOS did not release XHCI legacy hold!");
441
442	return ENOTSUP;
443	}
444
445	/**
446	* Ask the xHC to reset its state. Implements sequence
447	*/
448	static int hc_reset(xhci_hc_t *hc)
449	{
450	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
451	return ETIMEOUT;
452
453	/* Stop the HC: set R/S to 0 */
454	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
455
456	/* Wait until the HC is halted - it shall take at most 16 ms */
457	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH),
458	XHCI_REG_MASK(XHCI_OP_HCH)))
459	return ETIMEOUT;
460
461	/* Reset */
462	XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
463
464	/* Wait until the reset is complete */
465	if (xhci_reg_wait(&hc->op_regs->usbcmd, XHCI_REG_MASK(XHCI_OP_HCRST), 0))
466	return ETIMEOUT;
467
468	return EOK;
469	}
470
471	/**
472	* Initialize the HC: section 4.2
473	*/
474	int hc_start(xhci_hc_t *hc, bool irq)
475	{
476	int err;
477
478	if ((err = hc_reset(hc)))
479	return err;
480
481	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
482	return ETIMEOUT;
483
484	uint64_t dcbaaptr = hc->dcbaa_dma.phys;
485	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
486	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
487	XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
488
489	uintptr_t crcr;
490	xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
491	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crcr));
492	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crcr));
493
494	XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
495
496	xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
497	XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
498	uint64_t erdp = hc->event_ring.dequeue_ptr;
499	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
500	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
501	uint64_t erstptr = hc->event_ring.erst.phys;
502	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
503	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
504
505	if (irq) {
506	XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
507	XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
508	}
509
510	XHCI_REG_SET(hc->op_regs, XHCI_OP_HSEE, 1);
511
512	XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
513
514	xhci_rh_startup(&hc->rh);
515
516	return EOK;
517	}
518
519	/**
520	* Used only when polling. Shall supplement the irq_commands.
521	*/
522	int hc_status(bus_t bus, uint32_t status)
523	{
524	xhci_hc_t *hc = bus_to_hc(bus);
525	int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
526	if (ip) {
527	*status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
528	XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
529	XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
530
531	/* interrupt handler expects status from irq_commands, which is
532	* in xhci order. */
533	status = host2xhci(32, status);
534	}
535
536	usb_log_debug("Polled status: %x", *status);
537	return EOK;
538	}
539
540	static int xhci_handle_mfindex_wrap_event(xhci_hc_t hc, xhci_trb_t trb)
541	{
542	struct timeval tv;
543	getuptime(&tv);
544	usb_log_debug("Microframe index wrapped (@%lu.%li, %"PRIu64" total).",
545	tv.tv_sec, tv.tv_usec, hc->wrap_count);
546	hc->wrap_time = ((uint64_t) tv.tv_sec) * 1000000 + ((uint64_t) tv.tv_usec);
547	++hc->wrap_count;
548	return EOK;
549	}
550
551	static int handle_port_status_change_event(xhci_hc_t hc, xhci_trb_t trb)
552	{
553	uint8_t port_id = XHCI_QWORD_EXTRACT(trb->parameter, 31, 24);
554	usb_log_debug("Port status change event detected for port %u.", port_id);
555	xhci_rh_handle_port_change(&hc->rh, port_id);
556	return EOK;
557	}
558
559	typedef int (event_handler) (xhci_hc_t , xhci_trb_t *trb);
560
561	/**
562	* These events are handled by separate event handling fibril.
563	*/
564	static event_handler event_handlers [] = {
565	[XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT] = &handle_port_status_change_event,
566	};
567
568	/**
569	* These events are handled directly in the interrupt handler, thus they must
570	* not block waiting for another interrupt.
571	*/
572	static event_handler event_handlers_fast [] = {
573	[XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
574	[XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT] = &xhci_handle_mfindex_wrap_event,
575	[XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
576	};
577
578	static int hc_handle_event(xhci_hc_t hc, xhci_trb_t trb)
579	{
580	const unsigned type = TRB_TYPE(*trb);
581
582	if (type <= ARRAY_SIZE(event_handlers_fast) && event_handlers_fast[type])
583	return event_handlers_fast[type](hc, trb);
584
585	if (type <= ARRAY_SIZE(event_handlers) && event_handlers[type])
586	return xhci_sw_ring_enqueue(&hc->sw_ring, trb);
587
588	return ENOTSUP;
589	}
590
591	static int event_worker(void *arg)
592	{
593	int err;
594	xhci_trb_t trb;
595	xhci_hc_t * const hc = arg;
596	assert(hc);
597
598	while (xhci_sw_ring_dequeue(&hc->sw_ring, &trb) != EINTR) {
599	const unsigned type = TRB_TYPE(trb);
600
601	if ((err = event_handlers[type](hc, &trb)))
602	usb_log_error("Failed to handle event: %s", str_error(err));
603	}
604
605	// TODO: completion_complete
606	fibril_mutex_lock(&hc->event_fibril_completion.guard);
607	hc->event_fibril_completion.active = false;
608	fibril_condvar_wait(&hc->event_fibril_completion.cv,
609	&hc->event_fibril_completion.guard);
610	fibril_mutex_unlock(&hc->event_fibril_completion.guard);
611
612	return EOK;
613	}
614
615	/**
616	* Dequeue from event ring and handle dequeued events.
617	*
618	* As there can be events, that blocks on waiting for subsequent events,
619	* we solve this problem by first copying the event TRBs from the event ring,
620	* then asserting EHB and only after, handling the events.
621	*
622	* Whenever the event handling blocks, it switches fibril, and incoming
623	* IPC notification will create new event handling fibril for us.
624	*/
625	static void hc_run_event_ring(xhci_hc_t hc, xhci_event_ring_t event_ring,
626	xhci_interrupter_regs_t *intr)
627	{
628	int err;
629
630	xhci_trb_t trb;
631	hc->event_handler = fibril_get_id();
632
633	while ((err = xhci_event_ring_dequeue(event_ring, &trb)) != ENOENT) {
634	if ((err = hc_handle_event(hc, &trb)) != EOK) {
635	usb_log_error("Failed to handle event in interrupt: %s", str_error(err));
636	}
637
638	uint64_t erdp = hc->event_ring.dequeue_ptr;
639	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
640	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
641	}
642
643	hc->event_handler = 0;
644
645	/* Update the ERDP to make room in the ring. */
646	uint64_t erdp = hc->event_ring.dequeue_ptr;
647	erdp \|= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
648	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
649	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
650
651	usb_log_debug2("Event ring run finished.");
652	}
653
654	/**
655	* Handle an interrupt request from xHC. Resolve all situations that trigger an
656	* interrupt separately.
657	*
658	* Note that all RW1C bits in USBSTS register are cleared at the time of
659	* handling the interrupt in irq_code. This method is the top-half.
660	*
661	* @param status contents of USBSTS register at the time of the interrupt.
662	*/
663	void hc_interrupt(bus_t *bus, uint32_t status)
664	{
665	xhci_hc_t *hc = bus_to_hc(bus);
666	status = xhci2host(32, status);
667
668	if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
669	usb_log_error("Host controller error occured. Bad things gonna happen...");
670	status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
671	}
672
673	if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
674	usb_log_debug2("Event interrupt, running the event ring.");
675	hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
676	status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
677	}
678
679	if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
680	usb_log_error("Save/Restore error occured. WTF, "
681	"S/R mechanism not implemented!");
682	status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
683	}
684
685	/* According to Note on p. 302, we may safely ignore the PCD bit. */
686	status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
687
688	if (status) {
689	usb_log_error("Non-zero status after interrupt handling (%08x) "
690	" - missing something?", status);
691	}
692	}
693
694	/**
695	* Tear down all in-memory structures.
696	*/
697	void hc_fini(xhci_hc_t *hc)
698	{
699	xhci_sw_ring_stop(&hc->sw_ring);
700
701	// TODO: completion_wait
702	fibril_mutex_lock(&hc->event_fibril_completion.guard);
703	while (hc->event_fibril_completion.active)
704	fibril_condvar_wait(&hc->event_fibril_completion.cv,
705	&hc->event_fibril_completion.guard);
706	fibril_mutex_unlock(&hc->event_fibril_completion.guard);
707	xhci_sw_ring_fini(&hc->sw_ring);
708
709	xhci_bus_fini(&hc->bus);
710	xhci_event_ring_fini(&hc->event_ring);
711	xhci_scratchpad_free(hc);
712	dma_buffer_free(&hc->dcbaa_dma);
713	xhci_fini_commands(hc);
714	xhci_rh_fini(&hc->rh);
715	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
716	usb_log_info("Finalized.");
717	}
718
719	unsigned hc_speed_to_psiv(usb_speed_t speed)
720	{
721	assert(speed < ARRAY_SIZE(usb_speed_to_psiv));
722	return usb_speed_to_psiv[speed];
723	}
724
725	/**
726	* Ring a xHC Doorbell. Implements section 4.7.
727	*/
728	void hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
729	{
730	assert(hc);
731	uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
732	pio_write_32(&hc->db_arry[doorbell], v);
733	usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
734	}
735
736	/**
737	* Return an index to device context.
738	*/
739	static uint8_t endpoint_dci(xhci_endpoint_t *ep)
740	{
741	return (2 * ep->base.endpoint) +
742	(ep->base.transfer_type == USB_TRANSFER_CONTROL
743	\|\| ep->base.direction == USB_DIRECTION_IN);
744	}
745
746	void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id)
747	{
748	xhci_device_t * const dev = xhci_ep_to_dev(ep);
749	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
750	const uint8_t dci = endpoint_dci(ep);
751	const uint32_t target = (stream_id << 16) \| (dci & 0x1ff);
752	hc_ring_doorbell(hc, dev->slot_id, target);
753	}
754
755	/**
756	* Issue an Enable Slot command. Allocate memory for the slot and fill the
757	* DCBAA with the newly created slot.
758	*/
759	int hc_enable_slot(xhci_device_t *dev)
760	{
761	int err;
762	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
763
764	/* Prepare memory for the context */
765	if ((err = dma_buffer_alloc(&dev->dev_ctx, XHCI_DEVICE_CTX_SIZE(hc))))
766	return err;
767	memset(dev->dev_ctx.virt, 0, XHCI_DEVICE_CTX_SIZE(hc));
768
769	/* Get the slot number */
770	xhci_cmd_t cmd;
771	xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
772
773	err = xhci_cmd_sync(hc, &cmd);
774
775	/* Link them together */
776	if (err == EOK) {
777	dev->slot_id = cmd.slot_id;
778	hc->dcbaa[dev->slot_id] = host2xhci(64, dev->dev_ctx.phys);
779	}
780
781	xhci_cmd_fini(&cmd);
782
783	if (err)
784	dma_buffer_free(&dev->dev_ctx);
785
786	return err;
787	}
788
789	/**
790	* Issue a Disable Slot command for a slot occupied by device.
791	* Frees the device context.
792	*/
793	int hc_disable_slot(xhci_device_t *dev)
794	{
795	int err;
796	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
797
798	if ((err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = dev->slot_id))) {
799	return err;
800	}
801
802	/* Free the device context. */
803	hc->dcbaa[dev->slot_id] = 0;
804	dma_buffer_free(&dev->dev_ctx);
805
806	/* Mark the slot as invalid. */
807	dev->slot_id = 0;
808
809	return EOK;
810	}
811
812	/**
813	* Prepare an empty Endpoint Input Context inside a dma buffer.
814	*/
815	static int create_configure_ep_input_ctx(xhci_device_t dev, dma_buffer_t dma_buf)
816	{
817	const xhci_hc_t * hc = bus_to_hc(dev->base.bus);
818	const int err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc));
819	if (err)
820	return err;
821
822	xhci_input_ctx_t *ictx = dma_buf->virt;
823	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
824
825	// Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
826	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 0);
827	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
828	xhci_setup_slot_context(dev, slot_ctx);
829
830	return EOK;
831	}
832
833	/**
834	* Initialize a device, assigning it an address. Implements section 4.3.4.
835	*
836	* @param dev Device to assing an address (unconfigured yet)
837	*/
838	int hc_address_device(xhci_device_t *dev)
839	{
840	int err = ENOMEM;
841	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
842	xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]);
843
844	/* Although we have the precise PSIV value on devices of tier 1,
845	* we have to rely on reverse mapping on others. */
846	if (!usb_speed_to_psiv[dev->base.speed]) {
847	usb_log_error("Device reported an USB speed (%s) that cannot be mapped "
848	"to HC port speed.", usb_str_speed(dev->base.speed));
849	return EINVAL;
850	}
851
852	/* Issue configure endpoint command (sec 4.3.5). */
853	dma_buffer_t ictx_dma_buf;
854	if ((err = create_configure_ep_input_ctx(dev, &ictx_dma_buf)))
855	return err;
856	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
857
858	/* Copy endpoint 0 context and set A1 flag. */
859	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 1);
860	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, 1);
861	xhci_setup_endpoint_context(ep0, ep_ctx);
862
863	/* Address device needs Ctx entries set to 1 only */
864	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
865	XHCI_SLOT_CTX_ENTRIES_SET(*slot_ctx, 1);
866
867	/* Issue Address Device command. */
868	if ((err = xhci_cmd_sync_inline(hc, ADDRESS_DEVICE,
869	.slot_id = dev->slot_id,
870	.input_ctx = ictx_dma_buf
871	)))
872	return err;
873
874	xhci_device_ctx_t *device_ctx = dev->dev_ctx.virt;
875	dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(*XHCI_GET_SLOT_CTX(device_ctx, hc));
876	usb_log_debug("Obtained USB address: %d.", dev->base.address);
877
878	return EOK;
879	}
880
881	/**
882	* Issue a Configure Device command for a device in slot.
883	*
884	* @param slot_id Slot ID assigned to the device.
885	*/
886	int hc_configure_device(xhci_device_t *dev)
887	{
888	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
889
890	/* Issue configure endpoint command (sec 4.3.5). */
891	dma_buffer_t ictx_dma_buf;
892	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
893	if (err)
894	return err;
895
896	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
897	.slot_id = dev->slot_id,
898	.input_ctx = ictx_dma_buf
899	);
900	}
901
902	/**
903	* Issue a Deconfigure Device command for a device in slot.
904	*
905	* @param dev The owner of the device
906	*/
907	int hc_deconfigure_device(xhci_device_t *dev)
908	{
909	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
910
911	/* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
912	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
913	.slot_id = dev->slot_id,
914	.deconfigure = true
915	);
916	}
917
918	/**
919	* Instruct xHC to add an endpoint with supplied endpoint context.
920	*
921	* @param dev The owner of the device
922	* @param ep_idx Endpoint DCI in question
923	* @param ep_ctx Endpoint context of the endpoint
924	*/
925	int hc_add_endpoint(xhci_endpoint_t *ep)
926	{
927	xhci_device_t * const dev = xhci_ep_to_dev(ep);
928	const unsigned dci = endpoint_dci(ep);
929
930	/* Issue configure endpoint command (sec 4.3.5). */
931	dma_buffer_t ictx_dma_buf;
932	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
933	if (err)
934	return err;
935
936	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
937
938	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
939	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
940
941	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
942	xhci_setup_endpoint_context(ep, ep_ctx);
943
944	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
945	.slot_id = dev->slot_id,
946	.input_ctx = ictx_dma_buf
947	);
948	}
949
950	/**
951	* Instruct xHC to drop an endpoint.
952	*
953	* @param dev The owner of the endpoint
954	* @param ep_idx Endpoint DCI in question
955	*/
956	int hc_drop_endpoint(xhci_endpoint_t *ep)
957	{
958	xhci_device_t * const dev = xhci_ep_to_dev(ep);
959	const unsigned dci = endpoint_dci(ep);
960
961	/* Issue configure endpoint command (sec 4.3.5). */
962	dma_buffer_t ictx_dma_buf;
963	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
964	if (err)
965	return err;
966
967	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
968	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
969	XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
970
971	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT,
972	.slot_id = dev->slot_id,
973	.input_ctx = ictx_dma_buf
974	);
975	}
976
977	/**
978	* Instruct xHC to update information about an endpoint, using supplied
979	* endpoint context.
980	*
981	* @param dev The owner of the endpoint
982	* @param ep_idx Endpoint DCI in question
983	* @param ep_ctx Endpoint context of the endpoint
984	*/
985	int hc_update_endpoint(xhci_endpoint_t *ep)
986	{
987	xhci_device_t * const dev = xhci_ep_to_dev(ep);
988	const unsigned dci = endpoint_dci(ep);
989
990	dma_buffer_t ictx_dma_buf;
991	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
992
993	const int err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));
994	if (err)
995	return err;
996
997	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
998	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
999
1000	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
1001	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
1002	xhci_setup_endpoint_context(ep, ep_ctx);
1003
1004	return xhci_cmd_sync_inline(hc, EVALUATE_CONTEXT,
1005	.slot_id = dev->slot_id,
1006	.input_ctx = ictx_dma_buf
1007	);
1008	}
1009
1010	/**
1011	* Instruct xHC to stop running a transfer ring on an endpoint.
1012	*
1013	* @param dev The owner of the endpoint
1014	* @param ep_idx Endpoint DCI in question
1015	*/
1016	int hc_stop_endpoint(xhci_endpoint_t *ep)
1017	{
1018	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1019	const unsigned dci = endpoint_dci(ep);
1020	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1021	return xhci_cmd_sync_inline(hc, STOP_ENDPOINT,
1022	.slot_id = dev->slot_id,
1023	.endpoint_id = dci
1024	);
1025	}
1026
1027	/**
1028	* Instruct xHC to reset halted endpoint.
1029	*
1030	* @param dev The owner of the endpoint
1031	* @param ep_idx Endpoint DCI in question
1032	*/
1033	int hc_reset_endpoint(xhci_endpoint_t *ep)
1034	{
1035	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1036	const unsigned dci = endpoint_dci(ep);
1037	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1038	return xhci_cmd_sync_inline(hc, RESET_ENDPOINT,
1039	.slot_id = dev->slot_id,
1040	.endpoint_id = dci
1041	);
1042	}
1043
1044	/**
1045	* Reset a ring position in both software and hardware.
1046	*
1047	* @param dev The owner of the endpoint
1048	*/
1049	int hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id)
1050	{
1051	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1052	const unsigned dci = endpoint_dci(ep);
1053	uintptr_t addr;
1054
1055	xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id);
1056	xhci_trb_ring_reset_dequeue_state(ring, &addr);
1057
1058	xhci_hc_t * const hc = bus_to_hc(endpoint_get_bus(&ep->base));
1059	return xhci_cmd_sync_inline(hc, SET_TR_DEQUEUE_POINTER,
1060	.slot_id = dev->slot_id,
1061	.endpoint_id = dci,
1062	.stream_id = stream_id,
1063	.dequeue_ptr = addr,
1064	);
1065	}
1066
1067	/**
1068	* @}
1069	*/

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source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 4d12eda

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