source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 37789b5f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 37789b5f was 37789b5f, checked in by Jaroslav Jindrak <dzejrou@…>, 8 years ago

Fixed the dcbaa pointer passed to the xHC.
  • Property mode set to 100644
File size: 12.1 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "commands.h"
45
46static const irq_cmd_t irq_commands[] = {
47 {
48 .cmd = CMD_PIO_READ_32,
49 .dstarg = 1,
50 .addr = NULL
51 },
52 {
53 .cmd = CMD_AND,
54 .srcarg = 1,
55 .dstarg = 2,
56 .value = 0
57 },
58 {
59 .cmd = CMD_PREDICATE,
60 .srcarg = 2,
61 .value = 2
62 },
63 {
64 .cmd = CMD_PIO_WRITE_A_32,
65 .srcarg = 1,
66 .addr = NULL
67 },
68 {
69 .cmd = CMD_ACCEPT
70 }
71};
72
73/**
74 * Default USB Speed ID mapping: Table 157
75 */
76#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
77#define PORT_SPEED(psie, psim) { \
78 .rx_bps = PSI_TO_BPS(psie, psim), \
79 .tx_bps = PSI_TO_BPS(psie, psim) \
80}
81static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 12);
82static const xhci_port_speed_t ps_default_low = PORT_SPEED(1, 1500);
83static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 480);
84static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 5);
85
86/**
87 * Walk the list of extended capabilities.
88 */
89static int hc_parse_ec(xhci_hc_t *hc)
90{
91 unsigned psic, major;
92
93 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
94 xhci_dump_extcap(ec);
95 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
96 case XHCI_EC_USB_LEGACY:
97 assert(hc->legsup == NULL);
98 hc->legsup = (xhci_legsup_t *) ec;
99 break;
100 case XHCI_EC_SUPPORTED_PROTOCOL:
101 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
102 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
103
104 // "Implied" speed
105 if (psic == 0) {
106 /*
107 * According to section 7.2.2.1.2, only USB 2.0
108 * and USB 3.0 can have psic == 0. So we
109 * blindly assume the name == "USB " and minor
110 * == 0.
111 */
112 if (major == 2) {
113 hc->speeds[1] = ps_default_full;
114 hc->speeds[2] = ps_default_low;
115 hc->speeds[3] = ps_default_high;
116 } else if (major == 3) {
117 hc->speeds[4] = ps_default_super;
118 } else {
119 return EINVAL;
120 }
121
122 usb_log_debug2("Implied speed of USB %u set up.", major);
123 } else {
124 for (unsigned i = 0; i < psic; i++) {
125 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
126 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
127 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
128 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
129 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
130
131 uint64_t bps = PSI_TO_BPS(psie, psim);
132
133 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
134 hc->speeds[psiv].rx_bps = bps;
135 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
136 hc->speeds[psiv].tx_bps = bps;
137 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, hc->speeds[psiv].rx_bps, hc->speeds[psiv].tx_bps);
138 }
139 }
140 }
141 }
142 }
143 return EOK;
144}
145
146int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
147{
148 int err;
149
150 if (hw_res->mem_ranges.count != 1) {
151 usb_log_error("Unexpected MMIO area, bailing out.");
152 return EINVAL;
153 }
154
155 hc->mmio_range = hw_res->mem_ranges.ranges[0];
156
157 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
158 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
159
160 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
161 return EOVERFLOW;
162
163 void *base;
164 if ((err = pio_enable_range(&hc->mmio_range, &base)))
165 return err;
166
167 hc->base = base;
168 hc->cap_regs = (xhci_cap_regs_t *) base;
169 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
170 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
171 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
172
173 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
174 if (xec_offset > 0)
175 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
176
177 usb_log_debug2("Initialized MMIO reg areas:");
178 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
179 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
180 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
181 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
182
183 xhci_dump_cap_regs(hc->cap_regs);
184
185 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
186 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
187
188 if ((err = hc_parse_ec(hc))) {
189 pio_disable(hc->base, RNGSZ(hc->mmio_range));
190 return err;
191 }
192
193 return EOK;
194}
195
196int hc_init_memory(xhci_hc_t *hc)
197{
198 int err;
199
200 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(xhci_device_ctx_t*));
201 if (!hc->dcbaa)
202 return ENOMEM;
203
204 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
205 goto err_dcbaa;
206
207 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
208 goto err_cmd_ring;
209
210 if ((err = xhci_scratchpad_alloc(hc)))
211 goto err_event_ring;
212
213 return EOK;
214
215err_event_ring:
216 xhci_event_ring_fini(&hc->event_ring);
217err_cmd_ring:
218 xhci_trb_ring_fini(&hc->command_ring);
219err_dcbaa:
220 free32(hc->dcbaa);
221 return err;
222}
223
224
225/**
226 * Generates code to accept interrupts. The xHCI is designed primarily for
227 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
228 * (except 0) are disabled.
229 */
230int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
231{
232 assert(code);
233 assert(hw_res);
234
235 if (hw_res->irqs.count != 1) {
236 usb_log_info("Unexpected HW resources to enable interrupts.");
237 return EINVAL;
238 }
239
240 code->ranges = malloc(sizeof(irq_pio_range_t));
241 if (code->ranges == NULL)
242 return ENOMEM;
243
244 code->cmds = malloc(sizeof(irq_commands));
245 if (code->cmds == NULL) {
246 free(code->ranges);
247 return ENOMEM;
248 }
249
250 code->rangecount = 1;
251 code->ranges[0] = (irq_pio_range_t) {
252 .base = RNGABS(hc->mmio_range),
253 .size = RNGSZ(hc->mmio_range),
254 };
255
256 code->cmdcount = ARRAY_SIZE(irq_commands);
257 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
258
259 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
260 code->cmds[0].addr = intr0_iman;
261 code->cmds[3].addr = intr0_iman;
262 code->cmds[1].value = host2xhci(32, 1);
263
264 return hw_res->irqs.irqs[0];
265}
266
267int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
268{
269 /* No legacy support capability, the controller is solely for us */
270 if (!hc->legsup)
271 return EOK;
272
273 /*
274 * TODO: Implement handoff from BIOS, section 4.22.1
275 * QEMU does not support this, so we have to test on real HW.
276 */
277 return ENOTSUP;
278}
279
280static int hc_reset(xhci_hc_t *hc)
281{
282 /* Stop the HC: set R/S to 0 */
283 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
284
285 /* Wait 16 ms until the HC is halted */
286 async_usleep(16000);
287 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
288
289 /* Reset */
290 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
291
292 /* Wait until the reset is complete */
293 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
294 async_usleep(1000);
295
296 return EOK;
297}
298
299/**
300 * Initialize the HC: section 4.2
301 */
302int hc_start(xhci_hc_t *hc, bool irq)
303{
304 int err;
305
306 if ((err = hc_reset(hc)))
307 return err;
308
309 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
310 async_usleep(1000);
311
312 uint64_t dcbaaptr = addr_to_phys(hc->dcbaa);
313 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
314 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
315 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
316
317 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
318 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
319 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
320
321 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
322 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
323 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
324 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erstptr));
325 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erstptr));
326 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
327 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
328
329 // TODO: Setup scratchpad buffers
330
331 if (irq) {
332 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
333 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
334 }
335
336 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
337
338 return EOK;
339}
340
341int hc_status(xhci_hc_t *hc, uint32_t *status)
342{
343 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
344 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
345
346 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
347 return EOK;
348}
349
350int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
351{
352 xhci_dump_state(hc);
353 xhci_send_no_op_command(hc);
354 async_usleep(1000);
355 xhci_dump_state(hc);
356
357 xhci_dump_trb(hc->event_ring.dequeue_trb);
358 return EOK;
359}
360
361static void hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb)
362{
363 usb_log_debug2("TRB event encountered.");
364 switch (TRB_TYPE(*trb)) {
365 case XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT:
366 xhci_handle_command_completion(hc, trb);
367 break;
368 case XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT:
369 xhci_handle_port_status_change_event(hc, trb);
370 break;
371 default:
372 usb_log_debug2("Event type handling not implemented.");
373 break;
374 }
375}
376
377static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
378{
379 int err;
380 xhci_trb_t trb;
381
382 err = xhci_event_ring_dequeue(event_ring, &trb);;
383
384 switch (err) {
385 case EOK:
386 usb_log_debug2("Dequeued from event ring.");
387 xhci_dump_trb(&trb);
388
389 hc_handle_event(hc, &trb);
390 break;
391
392 case ENOENT:
393 usb_log_debug2("Event ring finished.");
394 break;
395
396 default:
397 usb_log_warning("Error while accessing event ring: %s", str_error(err));
398 }
399
400 /* Update the ERDP to make room in the ring */
401 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
402 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erstptr));
403 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erstptr));
404}
405
406void hc_interrupt(xhci_hc_t *hc, uint32_t status)
407{
408 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
409 usb_log_error("Host controller error occured. Bad things gonna happen...");
410 }
411
412 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
413 usb_log_debug2("Event interrupt.");
414
415 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
416
417 if (XHCI_REG_RD(intr0, XHCI_INTR_IP)) {
418 XHCI_REG_SET(intr0, XHCI_INTR_IP, 1);
419 hc_run_event_ring(hc, &hc->event_ring, intr0);
420 }
421 }
422
423 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
424 usb_log_error("Port change detected. Not implemented yet!");
425 }
426
427 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
428 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
429 }
430}
431
432static void hc_dcbaa_fini(xhci_hc_t *hc)
433{
434 xhci_scratchpad_free(hc);
435
436 /* Idx 0 already deallocated by xhci_scratchpad_free. */
437 for (unsigned i = 1; i < hc->max_slots + 1; ++i) {
438 if (hc->dcbaa[i] != NULL) {
439 free32(hc->dcbaa[i]);
440 hc->dcbaa[i] = NULL;
441 }
442 }
443
444 free32(hc->dcbaa);
445}
446
447void hc_fini(xhci_hc_t *hc)
448{
449 xhci_trb_ring_fini(&hc->command_ring);
450 xhci_event_ring_fini(&hc->event_ring);
451 hc_dcbaa_fini(hc);
452 pio_disable(hc->base, RNGSZ(hc->mmio_range));
453 usb_log_info("HC(%p): Finalized.", hc);
454}
455
456
457
458/**
459 * @}
460 */
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