source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 370a1c8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 370a1c8 was 370a1c8, checked in by Michal Staruch <salmelu@…>, 8 years ago

Extcap fix, not correctly determine if port is USB 2/3
  • Property mode set to 100644
File size: 16.4 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "debug.h"
41#include "hc.h"
42#include "rh.h"
43#include "hw_struct/trb.h"
44#include "commands.h"
45
46/**
47 * Default USB Speed ID mapping: Table 157
48 */
49#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
50#define PORT_SPEED(psie, psim) { \
51 .rx_bps = PSI_TO_BPS(psie, psim), \
52 .tx_bps = PSI_TO_BPS(psie, psim) \
53}
54static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 12);
55static const xhci_port_speed_t ps_default_low = PORT_SPEED(1, 1500);
56static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 480);
57static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 5);
58
59/**
60 * Walk the list of extended capabilities.
61 */
62static int hc_parse_ec(xhci_hc_t *hc)
63{
64 unsigned psic, major;
65
66 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
67 xhci_dump_extcap(ec);
68 switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
69 case XHCI_EC_USB_LEGACY:
70 assert(hc->legsup == NULL);
71 hc->legsup = (xhci_legsup_t *) ec;
72 break;
73 case XHCI_EC_SUPPORTED_PROTOCOL:
74 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
75 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
76
77 // "Implied" speed
78 if (psic == 0) {
79 /*
80 * According to section 7.2.2.1.2, only USB 2.0
81 * and USB 3.0 can have psic == 0. So we
82 * blindly assume the name == "USB " and minor
83 * == 0.
84 */
85
86 unsigned ports_from = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
87 unsigned ports_to = ports_from
88 + XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT) - 1;
89
90 if (major == 2) {
91 hc->speeds[1] = ps_default_full;
92 hc->speeds[2] = ps_default_low;
93 hc->speeds[3] = ps_default_high;
94 hc->rh.usb2_port_start = ports_from;
95 hc->rh.usb2_port_end = ports_to;
96 } else if (major == 3) {
97 hc->speeds[4] = ps_default_super;
98 hc->rh.usb3_port_start = ports_from;
99 hc->rh.usb3_port_end = ports_to;
100 } else {
101 return EINVAL;
102 }
103
104 usb_log_debug2("Implied speed of USB %u set up.", major);
105 } else {
106 for (unsigned i = 0; i < psic; i++) {
107 xhci_psi_t *psi = xhci_extcap_psi(ec, i);
108 unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
109 unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
110 unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
111 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
112
113 uint64_t bps = PSI_TO_BPS(psie, psim);
114
115 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX)
116 hc->speeds[psiv].rx_bps = bps;
117 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) {
118 hc->speeds[psiv].tx_bps = bps;
119 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, hc->speeds[psiv].rx_bps, hc->speeds[psiv].tx_bps);
120 }
121 }
122 }
123 }
124 }
125 return EOK;
126}
127
128int hc_init_mmio(xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
129{
130 int err;
131
132 if (hw_res->mem_ranges.count != 1) {
133 usb_log_error("Unexpected MMIO area, bailing out.");
134 return EINVAL;
135 }
136
137 hc->mmio_range = hw_res->mem_ranges.ranges[0];
138
139 usb_log_debug("MMIO area at %p (size %zu), IRQ %d.\n",
140 RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
141
142 if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
143 return EOVERFLOW;
144
145 void *base;
146 if ((err = pio_enable_range(&hc->mmio_range, &base)))
147 return err;
148
149 hc->base = base;
150 hc->cap_regs = (xhci_cap_regs_t *) base;
151 hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
152 hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
153 hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
154
155 uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
156 if (xec_offset > 0)
157 hc->xecp = (xhci_extcap_t *) (base + xec_offset);
158
159 usb_log_debug2("Initialized MMIO reg areas:");
160 usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
161 usb_log_debug2("\tOperational regs: %p", hc->op_regs);
162 usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
163 usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
164
165 xhci_dump_cap_regs(hc->cap_regs);
166
167 hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
168 hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
169
170 if ((err = hc_parse_ec(hc))) {
171 pio_disable(hc->base, RNGSZ(hc->mmio_range));
172 return err;
173 }
174
175 return EOK;
176}
177
178int hc_init_memory(xhci_hc_t *hc)
179{
180 int err;
181
182 hc->dcbaa = malloc32((1 + hc->max_slots) * sizeof(uint64_t));
183 if (!hc->dcbaa)
184 return ENOMEM;
185
186 hc->dcbaa_virt = malloc32((1 + hc->max_slots) * sizeof(xhci_virt_device_ctx_t));
187 if (!hc->dcbaa_virt) {
188 err = ENOMEM;
189 goto err_dcbaa;
190 }
191
192 if ((err = xhci_trb_ring_init(&hc->command_ring, hc)))
193 goto err_dcbaa_virt;
194
195 if ((err = xhci_event_ring_init(&hc->event_ring, hc)))
196 goto err_cmd_ring;
197
198 if ((err = xhci_scratchpad_alloc(hc)))
199 goto err_event_ring;
200
201 if ((err = xhci_init_commands(hc)))
202 goto err_scratch;
203
204 if ((err = xhci_rh_init(&hc->rh)))
205 goto err_cmd;
206
207 return EOK;
208
209err_cmd:
210 xhci_fini_commands(hc);
211err_scratch:
212 xhci_scratchpad_free(hc);
213err_event_ring:
214 xhci_event_ring_fini(&hc->event_ring);
215err_cmd_ring:
216 xhci_trb_ring_fini(&hc->command_ring);
217err_dcbaa_virt:
218 free32(hc->dcbaa_virt);
219err_dcbaa:
220 free32(hc->dcbaa);
221 return err;
222}
223
224/*
225 * Pseudocode:
226 * ip = read(intr[0].iman)
227 * if (ip) {
228 * status = read(usbsts)
229 * assert status
230 * assert ip
231 * accept (passing status)
232 * }
233 * decline
234 */
235static const irq_cmd_t irq_commands[] = {
236 {
237 .cmd = CMD_PIO_READ_32,
238 .dstarg = 3,
239 .addr = NULL /* intr[0].iman */
240 },
241 {
242 .cmd = CMD_AND,
243 .srcarg = 3,
244 .dstarg = 4,
245 .value = 0 /* host2xhci(32, 1) */
246 },
247 {
248 .cmd = CMD_PREDICATE,
249 .srcarg = 4,
250 .value = 5
251 },
252 {
253 .cmd = CMD_PIO_READ_32,
254 .dstarg = 1,
255 .addr = NULL /* usbsts */
256 },
257 {
258 .cmd = CMD_AND,
259 .srcarg = 1,
260 .dstarg = 2,
261 .value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
262 },
263 {
264 .cmd = CMD_PIO_WRITE_A_32,
265 .srcarg = 2,
266 .addr = NULL /* usbsts */
267 },
268 {
269 .cmd = CMD_PIO_WRITE_A_32,
270 .srcarg = 4,
271 .addr = NULL /* intr[0].iman */
272 },
273 {
274 .cmd = CMD_ACCEPT
275 },
276 {
277 .cmd = CMD_DECLINE
278 }
279};
280
281
282/**
283 * Generates code to accept interrupts. The xHCI is designed primarily for
284 * MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
285 * (except 0) are disabled.
286 */
287int hc_irq_code_gen(irq_code_t *code, xhci_hc_t *hc, const hw_res_list_parsed_t *hw_res)
288{
289 assert(code);
290 assert(hw_res);
291
292 if (hw_res->irqs.count != 1) {
293 usb_log_info("Unexpected HW resources to enable interrupts.");
294 return EINVAL;
295 }
296
297 code->ranges = malloc(sizeof(irq_pio_range_t));
298 if (code->ranges == NULL)
299 return ENOMEM;
300
301 code->cmds = malloc(sizeof(irq_commands));
302 if (code->cmds == NULL) {
303 free(code->ranges);
304 return ENOMEM;
305 }
306
307 code->rangecount = 1;
308 code->ranges[0] = (irq_pio_range_t) {
309 .base = RNGABS(hc->mmio_range),
310 .size = RNGSZ(hc->mmio_range),
311 };
312
313 code->cmdcount = ARRAY_SIZE(irq_commands);
314 memcpy(code->cmds, irq_commands, sizeof(irq_commands));
315
316 void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
317 void *usbsts = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) + offsetof(xhci_op_regs_t, usbsts);
318 code->cmds[0].addr = intr0_iman;
319 code->cmds[1].value = host2xhci(32, 1);
320 code->cmds[3].addr = usbsts;
321 code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
322 code->cmds[5].addr = usbsts;
323 code->cmds[6].addr = intr0_iman;
324
325 return hw_res->irqs.irqs[0];
326}
327
328int hc_claim(xhci_hc_t *hc, ddf_dev_t *dev)
329{
330 /* No legacy support capability, the controller is solely for us */
331 if (!hc->legsup)
332 return EOK;
333
334 /* Section 4.22.1 */
335 /* TODO: Test this with USB3-aware BIOS */
336 usb_log_debug2("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
337 XHCI_REG_WR(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
338 for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
339 usb_log_debug2("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
340 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
341 XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
342 if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
343 assert(XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1);
344 return EOK;
345 }
346 async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
347 }
348 usb_log_error("BIOS did not release XHCI legacy hold!\n");
349
350 return ENOTSUP;
351}
352
353static int hc_reset(xhci_hc_t *hc)
354{
355 /* Stop the HC: set R/S to 0 */
356 XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
357
358 /* Wait 16 ms until the HC is halted */
359 async_usleep(16000);
360 assert(XHCI_REG_RD(hc->op_regs, XHCI_OP_HCH));
361
362 /* Reset */
363 XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
364
365 /* Wait until the reset is complete */
366 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_HCRST))
367 async_usleep(1000);
368
369 return EOK;
370}
371
372/**
373 * Initialize the HC: section 4.2
374 */
375int hc_start(xhci_hc_t *hc, bool irq)
376{
377 int err;
378
379 if ((err = hc_reset(hc)))
380 return err;
381
382 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CNR))
383 async_usleep(1000);
384
385 uint64_t dcbaaptr = addr_to_phys(hc->dcbaa);
386 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
387 XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
388 XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, 0);
389
390 uint64_t crptr = xhci_trb_ring_get_dequeue_ptr(&hc->command_ring);
391 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crptr) >> 6);
392 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crptr));
393
394 uint64_t erstptr = addr_to_phys(hc->event_ring.erst);
395 uint64_t erdp = hc->event_ring.dequeue_ptr;
396 xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
397 XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
398 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
399 XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
400 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
401 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
402
403 if (irq) {
404 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
405 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
406 }
407
408 XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
409
410 return EOK;
411}
412
413/**
414 * Used only when polling. Shall supplement the irq_commands.
415 */
416int hc_status(xhci_hc_t *hc, uint32_t *status)
417{
418 int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
419 if (ip) {
420 *status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
421 XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
422 XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
423
424 /* interrupt handler expects status from irq_commands, which is
425 * in xhci order. */
426 *status = host2xhci(32, *status);
427 }
428
429 usb_log_debug2("HC(%p): Polled status: %x", hc, *status);
430 return EOK;
431}
432
433int hc_schedule(xhci_hc_t *hc, usb_transfer_batch_t *batch)
434{
435 assert(batch);
436
437 /* Check for root hub communication */
438 if (batch->ep->address == xhci_rh_get_address(&hc->rh)) {
439 usb_log_debug("XHCI root hub request.\n");
440 return xhci_rh_schedule(&hc->rh, batch);
441 }
442
443 usb_log_debug2("EP(%d:%d) started %s transfer of size %lu.",
444 batch->ep->address, batch->ep->endpoint,
445 usb_str_transfer_type(batch->ep->transfer_type),
446 batch->buffer_size);
447
448 switch (batch->ep->transfer_type) {
449 case USB_TRANSFER_CONTROL:
450 /* TODO: Send setup stage TRB. */
451 /* TODO: Optionally, send data stage TRB followed by zero or
452 more normal TRB's. */
453 /* TODO: Send status stage TRB. */
454 /* TODO: Ring the appropriate doorbell. */
455 break;
456 case USB_TRANSFER_ISOCHRONOUS:
457 /* TODO: Implement me. */
458 break;
459 case USB_TRANSFER_BULK:
460 /* TODO: Implement me. */
461 break;
462 case USB_TRANSFER_INTERRUPT:
463 /* TODO: Implement me. */
464 break;
465 }
466
467 return EOK;
468}
469
470static void hc_handle_event(xhci_hc_t *hc, xhci_trb_t *trb, xhci_interrupter_regs_t *intr)
471{
472 usb_log_debug2("TRB event encountered.");
473 switch (TRB_TYPE(*trb)) {
474 case XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT:
475 xhci_handle_command_completion(hc, trb);
476 break;
477 case XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT:
478 /**
479 * TODO: This is a very crude hotfix, I'm not sure if
480 * we can do this one level above in the event handling
481 * loop (incase the xHC adds more events while we process events).
482 */
483 hc->event_ring.dequeue_ptr = host2xhci(64, addr_to_phys(hc->event_ring.dequeue_trb));
484 uint64_t erdp = hc->event_ring.dequeue_ptr;
485 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
486 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
487 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
488 xhci_handle_port_status_change_event(hc, trb);
489 break;
490 default:
491 usb_log_debug2("Event type handling not implemented.");
492 break;
493 }
494}
495
496static void hc_run_event_ring(xhci_hc_t *hc, xhci_event_ring_t *event_ring, xhci_interrupter_regs_t *intr)
497{
498 int err;
499 xhci_trb_t trb;
500
501 err = xhci_event_ring_dequeue(event_ring, &trb);;
502
503 while (err != ENOENT) {
504 if (err == EOK) {
505 usb_log_debug2("Dequeued trb from event ring: %s",
506 xhci_trb_str_type(TRB_TYPE(trb)));
507
508 hc_handle_event(hc, &trb, intr);
509 } else {
510 usb_log_warning("Error while accessing event ring: %s", str_error(err));
511 break;
512 }
513
514 err = xhci_event_ring_dequeue(event_ring, &trb);;
515 }
516 usb_log_debug2("Event ring processing finished.");
517
518 /* Update the ERDP to make room in the ring */
519 hc->event_ring.dequeue_ptr = host2xhci(64, addr_to_phys(hc->event_ring.dequeue_trb));
520 uint64_t erdp = hc->event_ring.dequeue_ptr;
521 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
522 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
523 XHCI_REG_SET(intr, XHCI_INTR_ERDP_EHB, 1);
524}
525
526void hc_interrupt(xhci_hc_t *hc, uint32_t status)
527{
528 status = xhci2host(32, status);
529
530 /* TODO: Figure out how root hub interrupts work. */
531 if (status & XHCI_REG_MASK(XHCI_OP_PCD)) {
532 usb_log_debug2("Root hub interrupt.");
533 xhci_rh_interrupt(&hc->rh);
534
535 status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
536 }
537
538 if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
539 usb_log_error("Host controller error occured. Bad things gonna happen...");
540 status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
541 }
542
543 if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
544 usb_log_debug2("Event interrupt.");
545 hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
546 status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
547 }
548
549 if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
550 usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
551 status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
552 }
553
554 if (status) {
555 usb_log_error("Non-zero status after interrupt handling (%08x) - missing something?", status);
556 }
557}
558
559static void hc_dcbaa_fini(xhci_hc_t *hc)
560{
561 xhci_trb_ring_t* trb_ring;
562 xhci_scratchpad_free(hc);
563
564 /* Idx 0 already deallocated by xhci_scratchpad_free. */
565 for (unsigned i = 1; i < hc->max_slots + 1; ++i) {
566 if (hc->dcbaa_virt[i].dev_ctx) {
567 free32(hc->dcbaa_virt[i].dev_ctx);
568 hc->dcbaa_virt[i].dev_ctx = NULL;
569 }
570
571 for (unsigned i = 0; i < XHCI_EP_COUNT; ++i) {
572 trb_ring = hc->dcbaa_virt[i].trs[i];
573 if (trb_ring) {
574 hc->dcbaa_virt[i].trs[i] = NULL;
575 xhci_trb_ring_fini(trb_ring);
576 free32(trb_ring);
577 }
578 }
579 }
580
581 free32(hc->dcbaa);
582 free32(hc->dcbaa_virt);
583}
584
585void hc_fini(xhci_hc_t *hc)
586{
587 xhci_trb_ring_fini(&hc->command_ring);
588 xhci_event_ring_fini(&hc->event_ring);
589 hc_dcbaa_fini(hc);
590 xhci_fini_commands(hc);
591 xhci_rh_fini(&hc->rh);
592 pio_disable(hc->base, RNGSZ(hc->mmio_range));
593 usb_log_info("HC(%p): Finalized.", hc);
594}
595
596
597
598/**
599 * @}
600 */
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