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source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 2aaba7e

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Last change on this file since 2aaba7e was 51c1d500, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago
xhci: move HC semantics from endpoint/device to hc module
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File size: 29.4 KB

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1	/*
2	* Copyright (c) 2017 Ondrej Hlavaty
3	* All rights reserved.
4	*
5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions
7	* are met:
8	*
9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.
16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/
28
29	/** @addtogroup drvusbxhci
30	* @{
31	*/
32	/** @file
33	* @brief The host controller data bookkeeping.
34	*/
35
36	#include <errno.h>
37	#include <str_error.h>
38	#include <usb/debug.h>
39	#include <usb/host/endpoint.h>
40	#include "debug.h"
41	#include "hc.h"
42	#include "rh.h"
43	#include "hw_struct/trb.h"
44	#include "hw_struct/context.h"
45	#include "endpoint.h"
46	#include "transfers.h"
47	#include "trb_ring.h"
48
49	/**
50	* Default USB Speed ID mapping: Table 157
51	*/
52	#define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie))
53	#define PORT_SPEED(usb, mjr, psie, psim) { \
54	.name = "USB ", \
55	.major = mjr, \
56	.minor = 0, \
57	.usb_speed = USB_SPEED_##usb, \
58	.rx_bps = PSI_TO_BPS(psie, psim), \
59	.tx_bps = PSI_TO_BPS(psie, psim) \
60	}
61
62	static const xhci_port_speed_t default_psiv_to_port_speed [] = {
63	[1] = PORT_SPEED(FULL, 2, 2, 12),
64	[2] = PORT_SPEED(LOW, 2, 1, 1500),
65	[3] = PORT_SPEED(HIGH, 2, 2, 480),
66	[4] = PORT_SPEED(SUPER, 3, 3, 5),
67	};
68
69	static const unsigned usb_speed_to_psiv [] = {
70	[USB_SPEED_FULL] = 1,
71	[USB_SPEED_LOW] = 2,
72	[USB_SPEED_HIGH] = 3,
73	[USB_SPEED_SUPER] = 4,
74	};
75
76	/**
77	* Walk the list of extended capabilities.
78	*
79	* The most interesting thing hidden in extended capabilities is the mapping of
80	* ports to protocol versions and speeds.
81	*/
82	static int hc_parse_ec(xhci_hc_t *hc)
83	{
84	unsigned psic, major, minor;
85	xhci_sp_name_t name;
86
87	xhci_port_speed_t *speeds = hc->speeds;
88
89	for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) {
90	xhci_dump_extcap(ec);
91	switch (XHCI_REG_RD(ec, XHCI_EC_CAP_ID)) {
92	case XHCI_EC_USB_LEGACY:
93	assert(hc->legsup == NULL);
94	hc->legsup = (xhci_legsup_t *) ec;
95	break;
96	case XHCI_EC_SUPPORTED_PROTOCOL:
97	psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC);
98	major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR);
99	minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR);
100	name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME));
101
102	if (name.packed != xhci_name_usb.packed) {
103	/**
104	* The detection of such protocol would work,
105	* but the rest of the implementation is made
106	* for the USB protocol only.
107	*/
108	usb_log_error("Unknown protocol %.4s.", name.str);
109	return ENOTSUP;
110	}
111
112	unsigned offset = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF);
113	unsigned count = XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT);
114	xhci_rh_set_ports_protocol(&hc->rh, offset, count, major);
115
116	// "Implied" speed
117	if (psic == 0) {
118	assert(minor == 0);
119
120	if (major == 2) {
121	speeds[1] = default_psiv_to_port_speed[1];
122	speeds[2] = default_psiv_to_port_speed[2];
123	speeds[3] = default_psiv_to_port_speed[3];
124	} else if (major == 3) {
125	speeds[4] = default_psiv_to_port_speed[4];
126	} else {
127	return EINVAL;
128	}
129
130	usb_log_debug2("Implied speed of USB %u.0 set up.", major);
131	} else {
132	for (unsigned i = 0; i < psic; i++) {
133	xhci_psi_t *psi = xhci_extcap_psi(ec, i);
134	unsigned sim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
135	unsigned psiv = XHCI_REG_RD(psi, XHCI_PSI_PSIV);
136	unsigned psie = XHCI_REG_RD(psi, XHCI_PSI_PSIE);
137	unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM);
138	uint64_t bps = PSI_TO_BPS(psie, psim);
139
140	/*
141	* Speed is not implied, but using one of default PSIV. This is
142	* not clearly stated in xHCI spec. There is a clear intention
143	* to allow xHCI to specify its own speed parameters, but
144	* throughout the document, they used fixed values for e.g.
145	* High-speed (3), without stating the controller shall have
146	* implied default speeds - and for instance Intel controllers
147	* do not. So let's check if the values match and if so, accept
148	* the implied USB speed too.
149	*
150	* The main reason we need this is the usb_speed to have
151	* mapping also for devices connected to hubs.
152	*/
153	if (psiv < ARRAY_SIZE(default_psiv_to_port_speed)
154	&& default_psiv_to_port_speed[psiv].major == major
155	&& default_psiv_to_port_speed[psiv].minor == minor
156	&& default_psiv_to_port_speed[psiv].rx_bps == bps
157	&& default_psiv_to_port_speed[psiv].tx_bps == bps) {
158	speeds[psiv] = default_psiv_to_port_speed[psiv];
159	usb_log_debug2("Assumed default %s speed of USB %u.", usb_str_speed(speeds[psiv].usb_speed), major);
160	continue;
161	}
162
163	// Custom speed
164	speeds[psiv].major = major;
165	speeds[psiv].minor = minor;
166	str_ncpy(speeds[psiv].name, 4, name.str, 4);
167	speeds[psiv].usb_speed = USB_SPEED_MAX;
168
169	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_RX)
170	speeds[psiv].rx_bps = bps;
171	if (sim == XHCI_PSI_PLT_SYMM \|\| sim == XHCI_PSI_PLT_TX) {
172	speeds[psiv].tx_bps = bps;
173	usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, speeds[psiv].rx_bps, speeds[psiv].tx_bps);
174	}
175	}
176	}
177	}
178	}
179	return EOK;
180	}
181
182	/**
183	* Initialize MMIO spaces of xHC.
184	*/
185	int hc_init_mmio(xhci_hc_t hc, const hw_res_list_parsed_t hw_res)
186	{
187	int err;
188
189	if (hw_res->mem_ranges.count != 1) {
190	usb_log_error("Unexpected MMIO area, bailing out.");
191	return EINVAL;
192	}
193
194	hc->mmio_range = hw_res->mem_ranges.ranges[0];
195
196	usb_log_debug("MMIO area at %p (size %zu), IRQ %d.",
197	RNGABSPTR(hc->mmio_range), RNGSZ(hc->mmio_range), hw_res->irqs.irqs[0]);
198
199	if (RNGSZ(hc->mmio_range) < sizeof(xhci_cap_regs_t))
200	return EOVERFLOW;
201
202	void *base;
203	if ((err = pio_enable_range(&hc->mmio_range, &base)))
204	return err;
205
206	hc->reg_base = base;
207	hc->cap_regs = (xhci_cap_regs_t *) base;
208	hc->op_regs = (xhci_op_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH));
209	hc->rt_regs = (xhci_rt_regs_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF));
210	hc->db_arry = (xhci_doorbell_t *) (base + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_DBOFF));
211
212	uintptr_t xec_offset = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_XECP) * sizeof(xhci_dword_t);
213	if (xec_offset > 0)
214	hc->xecp = (xhci_extcap_t *) (base + xec_offset);
215
216	usb_log_debug2("Initialized MMIO reg areas:");
217	usb_log_debug2("\tCapability regs: %p", hc->cap_regs);
218	usb_log_debug2("\tOperational regs: %p", hc->op_regs);
219	usb_log_debug2("\tRuntime regs: %p", hc->rt_regs);
220	usb_log_debug2("\tDoorbell array base: %p", hc->db_arry);
221
222	xhci_dump_cap_regs(hc->cap_regs);
223
224	hc->ac64 = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_AC64);
225	hc->csz = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_CSZ);
226	hc->max_slots = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_SLOTS);
227
228	struct timeval tv;
229	getuptime(&tv);
230	hc->wrap_time = tv.tv_sec * 1000000 + tv.tv_usec;
231	hc->wrap_count = 0;
232
233	unsigned ist = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_IST);
234	hc->ist = (ist & 0x10 >> 1) * (ist & 0xf);
235
236	if ((err = xhci_rh_init(&hc->rh, hc)))
237	goto err_pio;
238
239	if ((err = hc_parse_ec(hc)))
240	goto err_rh;
241
242	return EOK;
243
244	err_rh:
245	xhci_rh_fini(&hc->rh);
246	err_pio:
247	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
248	return err;
249	}
250
251	static int event_worker(void *arg);
252
253	/**
254	* Initialize structures kept in allocated memory.
255	*/
256	int hc_init_memory(xhci_hc_t hc, ddf_dev_t device)
257	{
258	int err;
259
260	if (dma_buffer_alloc(&hc->dcbaa_dma, (1 + hc->max_slots) * sizeof(uint64_t)))
261	return ENOMEM;
262	hc->dcbaa = hc->dcbaa_dma.virt;
263
264	if ((err = xhci_event_ring_init(&hc->event_ring)))
265	goto err_dcbaa;
266
267	if ((err = xhci_scratchpad_alloc(hc)))
268	goto err_event_ring;
269
270	if ((err = xhci_init_commands(hc)))
271	goto err_scratch;
272
273	if ((err = xhci_bus_init(&hc->bus, hc)))
274	goto err_cmd;
275
276	fid_t fid = fibril_create(&event_worker, hc);
277	if (!fid)
278	goto err_bus;
279
280	// TODO: completion_reset
281	hc->event_fibril_completion.active = true;
282	fibril_mutex_initialize(&hc->event_fibril_completion.guard);
283	fibril_condvar_initialize(&hc->event_fibril_completion.cv);
284
285	xhci_sw_ring_init(&hc->sw_ring, PAGE_SIZE / sizeof(xhci_trb_t));
286
287	fibril_add_ready(fid);
288
289	return EOK;
290
291	err_bus:
292	xhci_bus_fini(&hc->bus);
293	err_cmd:
294	xhci_fini_commands(hc);
295	err_scratch:
296	xhci_scratchpad_free(hc);
297	err_event_ring:
298	xhci_event_ring_fini(&hc->event_ring);
299	err_dcbaa:
300	hc->dcbaa = NULL;
301	dma_buffer_free(&hc->dcbaa_dma);
302	return err;
303	}
304
305	/*
306	* Pseudocode:
307	* ip = read(intr[0].iman)
308	* if (ip) {
309	* status = read(usbsts)
310	* assert status
311	* assert ip
312	* accept (passing status)
313	* }
314	* decline
315	*/
316	static const irq_cmd_t irq_commands[] = {
317	{
318	.cmd = CMD_PIO_READ_32,
319	.dstarg = 3,
320	.addr = NULL /* intr[0].iman */
321	},
322	{
323	.cmd = CMD_AND,
324	.srcarg = 3,
325	.dstarg = 4,
326	.value = 0 /* host2xhci(32, 1) */
327	},
328	{
329	.cmd = CMD_PREDICATE,
330	.srcarg = 4,
331	.value = 5
332	},
333	{
334	.cmd = CMD_PIO_READ_32,
335	.dstarg = 1,
336	.addr = NULL /* usbsts */
337	},
338	{
339	.cmd = CMD_AND,
340	.srcarg = 1,
341	.dstarg = 2,
342	.value = 0 /* host2xhci(32, XHCI_STATUS_ACK_MASK) */
343	},
344	{
345	.cmd = CMD_PIO_WRITE_A_32,
346	.srcarg = 2,
347	.addr = NULL /* usbsts */
348	},
349	{
350	.cmd = CMD_PIO_WRITE_A_32,
351	.srcarg = 3,
352	.addr = NULL /* intr[0].iman */
353	},
354	{
355	.cmd = CMD_ACCEPT
356	},
357	{
358	.cmd = CMD_DECLINE
359	}
360	};
361
362
363	/**
364	* Generates code to accept interrupts. The xHCI is designed primarily for
365	* MSI/MSI-X, but we use PCI Interrupt Pin. In this mode, all the Interrupters
366	* (except 0) are disabled.
367	*/
368	int hc_irq_code_gen(irq_code_t code, xhci_hc_t hc, const hw_res_list_parsed_t *hw_res)
369	{
370	assert(code);
371	assert(hw_res);
372
373	if (hw_res->irqs.count != 1) {
374	usb_log_info("Unexpected HW resources to enable interrupts.");
375	return EINVAL;
376	}
377
378	code->ranges = malloc(sizeof(irq_pio_range_t));
379	if (code->ranges == NULL)
380	return ENOMEM;
381
382	code->cmds = malloc(sizeof(irq_commands));
383	if (code->cmds == NULL) {
384	free(code->ranges);
385	return ENOMEM;
386	}
387
388	code->rangecount = 1;
389	code->ranges[0] = (irq_pio_range_t) {
390	.base = RNGABS(hc->mmio_range),
391	.size = RNGSZ(hc->mmio_range),
392	};
393
394	code->cmdcount = ARRAY_SIZE(irq_commands);
395	memcpy(code->cmds, irq_commands, sizeof(irq_commands));
396
397	void *intr0_iman = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_RTSOFF) + offsetof(xhci_rt_regs_t, ir[0]);
398	void *usbsts = RNGABSPTR(hc->mmio_range) + XHCI_REG_RD(hc->cap_regs, XHCI_CAP_LENGTH) + offsetof(xhci_op_regs_t, usbsts);
399	code->cmds[0].addr = intr0_iman;
400	code->cmds[1].value = host2xhci(32, 1);
401	code->cmds[3].addr = usbsts;
402	code->cmds[4].value = host2xhci(32, XHCI_STATUS_ACK_MASK);
403	code->cmds[5].addr = usbsts;
404	code->cmds[6].addr = intr0_iman;
405
406	return hw_res->irqs.irqs[0];
407	}
408
409	/**
410	* Claim xHC from BIOS. Implements handoff as per Section 4.22.1 of xHCI spec.
411	*/
412	int hc_claim(xhci_hc_t hc, ddf_dev_t dev)
413	{
414	/* No legacy support capability, the controller is solely for us */
415	if (!hc->legsup)
416	return EOK;
417
418	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
419	return ETIMEOUT;
420
421	usb_log_debug2("LEGSUP: bios: %x, os: %x", hc->legsup->sem_bios, hc->legsup->sem_os);
422	XHCI_REG_SET(hc->legsup, XHCI_LEGSUP_SEM_OS, 1);
423	for (int i = 0; i <= (XHCI_LEGSUP_BIOS_TIMEOUT_US / XHCI_LEGSUP_POLLING_DELAY_1MS); i++) {
424	usb_log_debug2("LEGSUP: elapsed: %i ms, bios: %x, os: %x", i,
425	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS),
426	XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS));
427	if (XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_BIOS) == 0) {
428	return XHCI_REG_RD(hc->legsup, XHCI_LEGSUP_SEM_OS) == 1 ? EOK : EIO;
429	}
430	async_usleep(XHCI_LEGSUP_POLLING_DELAY_1MS);
431	}
432	usb_log_error("BIOS did not release XHCI legacy hold!");
433
434	return ENOTSUP;
435	}
436
437	/**
438	* Ask the xHC to reset its state. Implements sequence
439	*/
440	static int hc_reset(xhci_hc_t *hc)
441	{
442	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
443	return ETIMEOUT;
444
445	/* Stop the HC: set R/S to 0 */
446	XHCI_REG_CLR(hc->op_regs, XHCI_OP_RS, 1);
447
448	/* Wait until the HC is halted - it shall take at most 16 ms */
449	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_HCH), XHCI_REG_MASK(XHCI_OP_HCH)))
450	return ETIMEOUT;
451
452	/* Reset */
453	XHCI_REG_SET(hc->op_regs, XHCI_OP_HCRST, 1);
454
455	/* Wait until the reset is complete */
456	if (xhci_reg_wait(&hc->op_regs->usbcmd, XHCI_REG_MASK(XHCI_OP_HCRST), 0))
457	return ETIMEOUT;
458
459	return EOK;
460	}
461
462	/**
463	* Initialize the HC: section 4.2
464	*/
465	int hc_start(xhci_hc_t *hc, bool irq)
466	{
467	int err;
468
469	if ((err = hc_reset(hc)))
470	return err;
471
472	if (xhci_reg_wait(&hc->op_regs->usbsts, XHCI_REG_MASK(XHCI_OP_CNR), 0))
473	return ETIMEOUT;
474
475	uint64_t dcbaaptr = hc->dcbaa_dma.phys;
476	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
477	XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
478	XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
479
480	uintptr_t crcr;
481	xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
482	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crcr));
483	XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crcr));
484
485	XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
486
487	xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
488	XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
489	uint64_t erdp = hc->event_ring.dequeue_ptr;
490	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
491	XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
492	uint64_t erstptr = hc->event_ring.erst.phys;
493	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
494	XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
495
496
497	if (irq) {
498	XHCI_REG_SET(intr0, XHCI_INTR_IE, 1);
499	XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
500	}
501
502	XHCI_REG_SET(hc->op_regs, XHCI_OP_HSEE, 1);
503
504	XHCI_REG_SET(hc->op_regs, XHCI_OP_RS, 1);
505
506	xhci_rh_startup(&hc->rh);
507
508	return EOK;
509	}
510
511	/**
512	* Used only when polling. Shall supplement the irq_commands.
513	*/
514	int hc_status(bus_t bus, uint32_t status)
515	{
516	xhci_hc_t *hc = bus_to_hc(bus);
517	int ip = XHCI_REG_RD(hc->rt_regs->ir, XHCI_INTR_IP);
518	if (ip) {
519	*status = XHCI_REG_RD(hc->op_regs, XHCI_OP_STATUS);
520	XHCI_REG_WR(hc->op_regs, XHCI_OP_STATUS, *status & XHCI_STATUS_ACK_MASK);
521	XHCI_REG_WR(hc->rt_regs->ir, XHCI_INTR_IP, 1);
522
523	/* interrupt handler expects status from irq_commands, which is
524	* in xhci order. */
525	status = host2xhci(32, status);
526	}
527
528	usb_log_debug2("Polled status: %x", *status);
529	return EOK;
530	}
531
532	static int xhci_handle_mfindex_wrap_event(xhci_hc_t hc, xhci_trb_t trb)
533	{
534	struct timeval tv;
535	getuptime(&tv);
536	usb_log_debug2("Microframe index wrapped (@%lu.%li, %"PRIu64" total).", tv.tv_sec, tv.tv_usec, hc->wrap_count);
537	hc->wrap_time = ((uint64_t) tv.tv_sec) * 1000000 + ((uint64_t) tv.tv_usec);
538	++hc->wrap_count;
539	return EOK;
540	}
541
542	static int handle_port_status_change_event(xhci_hc_t hc, xhci_trb_t trb)
543	{
544	uint8_t port_id = XHCI_QWORD_EXTRACT(trb->parameter, 31, 24);
545	usb_log_debug("Port status change event detected for port %u.", port_id);
546	xhci_rh_handle_port_change(&hc->rh, port_id);
547	return EOK;
548	}
549
550	typedef int (event_handler) (xhci_hc_t , xhci_trb_t *trb);
551
552	/**
553	* These events are handled by separate event handling fibril.
554	*/
555	static event_handler event_handlers [] = {
556	[XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVENT] = &handle_port_status_change_event,
557	[XHCI_TRB_TYPE_TRANSFER_EVENT] = &xhci_handle_transfer_event,
558	};
559
560	/**
561	* These events are handled directly in the interrupt handler, thus they must
562	* not block waiting for another interrupt.
563	*/
564	static event_handler event_handlers_fast [] = {
565	[XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT] = &xhci_handle_command_completion,
566	[XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT] = &xhci_handle_mfindex_wrap_event,
567	};
568
569	static int hc_handle_event(xhci_hc_t hc, xhci_trb_t trb)
570	{
571	const unsigned type = TRB_TYPE(*trb);
572
573	if (type <= ARRAY_SIZE(event_handlers_fast) && event_handlers_fast[type])
574	return event_handlers_fast[type](hc, trb);
575
576	if (type <= ARRAY_SIZE(event_handlers) && event_handlers[type])
577	return xhci_sw_ring_enqueue(&hc->sw_ring, trb);
578
579	return ENOTSUP;
580	}
581
582	static int event_worker(void *arg)
583	{
584	int err;
585	xhci_trb_t trb;
586	xhci_hc_t * const hc = arg;
587	assert(hc);
588
589	while (xhci_sw_ring_dequeue(&hc->sw_ring, &trb) != EINTR) {
590	const unsigned type = TRB_TYPE(trb);
591
592	if ((err = event_handlers[type](hc, &trb)))
593	usb_log_error("Failed to handle event: %s", str_error(err));
594	}
595
596	// TODO: completion_complete
597	fibril_mutex_lock(&hc->event_fibril_completion.guard);
598	hc->event_fibril_completion.active = false;
599	fibril_condvar_wait(&hc->event_fibril_completion.cv, &hc->event_fibril_completion.guard);
600	fibril_mutex_unlock(&hc->event_fibril_completion.guard);
601
602	return EOK;
603	}
604
605	/**
606	* Dequeue from event ring and handle dequeued events.
607	*
608	* As there can be events, that blocks on waiting for subsequent events,
609	* we solve this problem by first copying the event TRBs from the event ring,
610	* then asserting EHB and only after, handling the events.
611	*
612	* Whenever the event handling blocks, it switches fibril, and incoming
613	* IPC notification will create new event handling fibril for us.
614	*/
615	static void hc_run_event_ring(xhci_hc_t hc, xhci_event_ring_t event_ring, xhci_interrupter_regs_t *intr)
616	{
617	int err;
618
619	xhci_trb_t trb;
620	hc->event_handler = fibril_get_id();
621
622	while ((err = xhci_event_ring_dequeue(event_ring, &trb)) != ENOENT) {
623	if ((err = hc_handle_event(hc, &trb)) != EOK) {
624	usb_log_error("Failed to handle event in interrupt: %s", str_error(err));
625	}
626
627	uint64_t erdp = hc->event_ring.dequeue_ptr;
628	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
629	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
630	}
631
632	hc->event_handler = 0;
633
634	/* Update the ERDP to make room in the ring. */
635	uint64_t erdp = hc->event_ring.dequeue_ptr;
636	erdp \|= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
637	XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
638	XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
639
640	usb_log_debug2("Event ring run finished.");
641	}
642
643	/**
644	* Handle an interrupt request from xHC. Resolve all situations that trigger an
645	* interrupt separately.
646	*
647	* Note that all RW1C bits in USBSTS register are cleared at the time of
648	* handling the interrupt in irq_code. This method is the top-half.
649	*
650	* @param status contents of USBSTS register at the time of the interrupt.
651	*/
652	void hc_interrupt(bus_t *bus, uint32_t status)
653	{
654	xhci_hc_t *hc = bus_to_hc(bus);
655	status = xhci2host(32, status);
656
657	if (status & XHCI_REG_MASK(XHCI_OP_HSE)) {
658	usb_log_error("Host controller error occured. Bad things gonna happen...");
659	status &= ~XHCI_REG_MASK(XHCI_OP_HSE);
660	}
661
662	if (status & XHCI_REG_MASK(XHCI_OP_EINT)) {
663	usb_log_debug2("Event interrupt, running the event ring.");
664	hc_run_event_ring(hc, &hc->event_ring, &hc->rt_regs->ir[0]);
665	status &= ~XHCI_REG_MASK(XHCI_OP_EINT);
666	}
667
668	if (status & XHCI_REG_MASK(XHCI_OP_SRE)) {
669	usb_log_error("Save/Restore error occured. WTF, S/R mechanism not implemented!");
670	status &= ~XHCI_REG_MASK(XHCI_OP_SRE);
671	}
672
673	/* According to Note on p. 302, we may safely ignore the PCD bit. */
674	status &= ~XHCI_REG_MASK(XHCI_OP_PCD);
675
676	if (status) {
677	usb_log_error("Non-zero status after interrupt handling (%08x) - missing something?", status);
678	}
679	}
680
681	/**
682	* Tear down all in-memory structures.
683	*/
684	void hc_fini(xhci_hc_t *hc)
685	{
686	xhci_sw_ring_stop(&hc->sw_ring);
687
688	// TODO: completion_wait
689	fibril_mutex_lock(&hc->event_fibril_completion.guard);
690	while (hc->event_fibril_completion.active)
691	fibril_condvar_wait(&hc->event_fibril_completion.cv, &hc->event_fibril_completion.guard);
692	fibril_mutex_unlock(&hc->event_fibril_completion.guard);
693	xhci_sw_ring_fini(&hc->sw_ring);
694
695	xhci_bus_fini(&hc->bus);
696	xhci_event_ring_fini(&hc->event_ring);
697	xhci_scratchpad_free(hc);
698	dma_buffer_free(&hc->dcbaa_dma);
699	xhci_fini_commands(hc);
700	xhci_rh_fini(&hc->rh);
701	pio_disable(hc->reg_base, RNGSZ(hc->mmio_range));
702	usb_log_info("Finalized.");
703	}
704
705	unsigned hc_speed_to_psiv(usb_speed_t speed)
706	{
707	assert(speed < ARRAY_SIZE(usb_speed_to_psiv));
708	return usb_speed_to_psiv[speed];
709	}
710
711	/**
712	* Ring a xHC Doorbell. Implements section 4.7.
713	*/
714	void hc_ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
715	{
716	assert(hc);
717	uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
718	pio_write_32(&hc->db_arry[doorbell], v);
719	usb_log_debug2("Ringing doorbell %d (target: %d)", doorbell, target);
720	}
721
722	/**
723	* Return an index to device context.
724	*/
725	static uint8_t endpoint_dci(xhci_endpoint_t *ep)
726	{
727	return (2 * ep->base.endpoint) +
728	(ep->base.transfer_type == USB_TRANSFER_CONTROL
729	\|\| ep->base.direction == USB_DIRECTION_IN);
730	}
731
732	void hc_ring_ep_doorbell(xhci_endpoint_t *ep, uint32_t stream_id)
733	{
734	xhci_device_t * const dev = xhci_ep_to_dev(ep);
735	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
736	const uint8_t dci = endpoint_dci(ep);
737	const uint32_t target = (stream_id << 16) \| (dci & 0x1ff);
738	hc_ring_doorbell(hc, dev->slot_id, target);
739	}
740
741	/**
742	* Issue an Enable Slot command. Allocate memory for the slot and fill the
743	* DCBAA with the newly created slot.
744	*/
745	int hc_enable_slot(xhci_device_t *dev)
746	{
747	int err;
748	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
749
750	/* Prepare memory for the context */
751	if ((err = dma_buffer_alloc(&dev->dev_ctx, XHCI_DEVICE_CTX_SIZE(hc))))
752	return err;
753	memset(dev->dev_ctx.virt, 0, XHCI_DEVICE_CTX_SIZE(hc));
754
755	/* Get the slot number */
756	xhci_cmd_t cmd;
757	xhci_cmd_init(&cmd, XHCI_CMD_ENABLE_SLOT);
758
759	err = xhci_cmd_sync(hc, &cmd);
760
761	/* Link them together */
762	if (err == EOK) {
763	dev->slot_id = cmd.slot_id;
764	hc->dcbaa[dev->slot_id] = host2xhci(64, dev->dev_ctx.phys);
765	}
766
767	xhci_cmd_fini(&cmd);
768
769	if (err)
770	dma_buffer_free(&dev->dev_ctx);
771
772	return err;
773	}
774
775	/**
776	* Issue a Disable Slot command for a slot occupied by device.
777	* Frees the device context.
778	*/
779	int hc_disable_slot(xhci_device_t *dev)
780	{
781	int err;
782	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
783
784	if ((err = xhci_cmd_sync_inline(hc, DISABLE_SLOT, .slot_id = dev->slot_id))) {
785	return err;
786	}
787
788	/* Free the device context. */
789	hc->dcbaa[dev->slot_id] = 0;
790	dma_buffer_free(&dev->dev_ctx);
791
792	/* Mark the slot as invalid. */
793	dev->slot_id = 0;
794
795	return EOK;
796	}
797
798	/**
799	* Prepare an empty Endpoint Input Context inside a dma buffer.
800	*/
801	static int create_configure_ep_input_ctx(xhci_device_t dev, dma_buffer_t dma_buf)
802	{
803	const xhci_hc_t * hc = bus_to_hc(dev->base.bus);
804	const int err = dma_buffer_alloc(dma_buf, XHCI_INPUT_CTX_SIZE(hc));
805	if (err)
806	return err;
807
808	xhci_input_ctx_t *ictx = dma_buf->virt;
809	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
810
811	// Quoting sec. 4.6.5 and 4.6.6: A1, D0, D1 are down (already zeroed), A0 is up.
812	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 0);
813	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
814	xhci_setup_slot_context(dev, slot_ctx);
815
816	return EOK;
817	}
818
819	/**
820	* Initialize a device, assigning it an address. Implements section 4.3.4.
821	*
822	* @param dev Device to assing an address (unconfigured yet)
823	*/
824	int hc_address_device(xhci_device_t *dev)
825	{
826	int err = ENOMEM;
827	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
828	xhci_endpoint_t *ep0 = xhci_endpoint_get(dev->base.endpoints[0]);
829
830	/* Although we have the precise PSIV value on devices of tier 1,
831	* we have to rely on reverse mapping on others. */
832	if (!usb_speed_to_psiv[dev->base.speed]) {
833	usb_log_error("Device reported an USB speed (%s) that cannot be mapped to HC port speed.", usb_str_speed(dev->base.speed));
834	return EINVAL;
835	}
836
837	/* Issue configure endpoint command (sec 4.3.5). */
838	dma_buffer_t ictx_dma_buf;
839	if ((err = create_configure_ep_input_ctx(dev, &ictx_dma_buf)))
840	return err;
841	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
842
843	/* Copy endpoint 0 context and set A1 flag. */
844	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), 1);
845	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, 1);
846	xhci_setup_endpoint_context(ep0, ep_ctx);
847
848	/* Address device needs Ctx entries set to 1 only */
849	xhci_slot_ctx_t *slot_ctx = XHCI_GET_SLOT_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc);
850	XHCI_SLOT_CTX_ENTRIES_SET(*slot_ctx, 1);
851
852	/* Issue Address Device command. */
853	if ((err = xhci_cmd_sync_inline(hc, ADDRESS_DEVICE, .slot_id = dev->slot_id, .input_ctx = ictx_dma_buf)))
854	return err;
855
856	xhci_device_ctx_t *device_ctx = dev->dev_ctx.virt;
857	dev->base.address = XHCI_SLOT_DEVICE_ADDRESS(*XHCI_GET_SLOT_CTX(device_ctx, hc));
858	usb_log_debug2("Obtained USB address: %d.", dev->base.address);
859
860	return EOK;
861	}
862
863	/**
864	* Issue a Configure Device command for a device in slot.
865	*
866	* @param slot_id Slot ID assigned to the device.
867	*/
868	int hc_configure_device(xhci_device_t *dev)
869	{
870	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
871
872	/* Issue configure endpoint command (sec 4.3.5). */
873	dma_buffer_t ictx_dma_buf;
874	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
875	if (err)
876	return err;
877
878	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, .slot_id = dev->slot_id, .input_ctx = ictx_dma_buf);
879	}
880
881	/**
882	* Issue a Deconfigure Device command for a device in slot.
883	*
884	* @param dev The owner of the device
885	*/
886	int hc_deconfigure_device(xhci_device_t *dev)
887	{
888	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
889
890	/* Issue configure endpoint command (sec 4.3.5) with the DC flag. */
891	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, .slot_id = dev->slot_id, .deconfigure = true);
892	}
893
894	/**
895	* Instruct xHC to add an endpoint with supplied endpoint context.
896	*
897	* @param dev The owner of the device
898	* @param ep_idx Endpoint DCI in question
899	* @param ep_ctx Endpoint context of the endpoint
900	*/
901	int hc_add_endpoint(xhci_endpoint_t *ep)
902	{
903	xhci_device_t * const dev = xhci_ep_to_dev(ep);
904	const unsigned dci = endpoint_dci(ep);
905
906	/* Issue configure endpoint command (sec 4.3.5). */
907	dma_buffer_t ictx_dma_buf;
908	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
909	if (err)
910	return err;
911
912	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
913
914	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
915	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
916
917	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
918	xhci_setup_endpoint_context(ep, ep_ctx);
919
920	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, .slot_id = dev->slot_id, .input_ctx = ictx_dma_buf);
921	}
922
923	/**
924	* Instruct xHC to drop an endpoint.
925	*
926	* @param dev The owner of the endpoint
927	* @param ep_idx Endpoint DCI in question
928	*/
929	int hc_drop_endpoint(xhci_endpoint_t *ep)
930	{
931	xhci_device_t * const dev = xhci_ep_to_dev(ep);
932	const unsigned dci = endpoint_dci(ep);
933
934	/* Issue configure endpoint command (sec 4.3.5). */
935	dma_buffer_t ictx_dma_buf;
936	const int err = create_configure_ep_input_ctx(dev, &ictx_dma_buf);
937	if (err)
938	return err;
939
940	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
941	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
942	XHCI_INPUT_CTRL_CTX_DROP_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
943
944	return xhci_cmd_sync_inline(hc, CONFIGURE_ENDPOINT, .slot_id = dev->slot_id, .input_ctx = ictx_dma_buf);
945	}
946
947	/**
948	* Instruct xHC to update information about an endpoint, using supplied
949	* endpoint context.
950	*
951	* @param dev The owner of the endpoint
952	* @param ep_idx Endpoint DCI in question
953	* @param ep_ctx Endpoint context of the endpoint
954	*/
955	int hc_update_endpoint(xhci_endpoint_t *ep)
956	{
957	xhci_device_t * const dev = xhci_ep_to_dev(ep);
958	const unsigned dci = endpoint_dci(ep);
959
960	dma_buffer_t ictx_dma_buf;
961	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
962
963	const int err = dma_buffer_alloc(&ictx_dma_buf, XHCI_INPUT_CTX_SIZE(hc));
964	if (err)
965	return err;
966
967	xhci_input_ctx_t *ictx = ictx_dma_buf.virt;
968	memset(ictx, 0, XHCI_INPUT_CTX_SIZE(hc));
969
970	XHCI_INPUT_CTRL_CTX_ADD_SET(*XHCI_GET_CTRL_CTX(ictx, hc), dci);
971	xhci_ep_ctx_t *ep_ctx = XHCI_GET_EP_CTX(XHCI_GET_DEVICE_CTX(ictx, hc), hc, dci);
972	xhci_setup_endpoint_context(ep, ep_ctx);
973
974	return xhci_cmd_sync_inline(hc, EVALUATE_CONTEXT, .slot_id = dev->slot_id, .input_ctx = ictx_dma_buf);
975	}
976
977	/**
978	* Instruct xHC to stop running a transfer ring on an endpoint.
979	*
980	* @param dev The owner of the endpoint
981	* @param ep_idx Endpoint DCI in question
982	*/
983	int hc_stop_endpoint(xhci_endpoint_t *ep)
984	{
985	xhci_device_t * const dev = xhci_ep_to_dev(ep);
986	const unsigned dci = endpoint_dci(ep);
987	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
988	return xhci_cmd_sync_inline(hc, STOP_ENDPOINT, .slot_id = dev->slot_id, .endpoint_id = dci);
989	}
990
991	/**
992	* Instruct xHC to reset halted endpoint.
993	*
994	* @param dev The owner of the endpoint
995	* @param ep_idx Endpoint DCI in question
996	*/
997	int hc_reset_endpoint(xhci_endpoint_t *ep)
998	{
999	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1000	const unsigned dci = endpoint_dci(ep);
1001	xhci_hc_t * const hc = bus_to_hc(dev->base.bus);
1002	return xhci_cmd_sync_inline(hc, RESET_ENDPOINT, .slot_id = dev->slot_id, .endpoint_id = dci);
1003	}
1004
1005	/**
1006	* Reset a ring position in both software and hardware.
1007	*
1008	* @param dev The owner of the endpoint
1009	*/
1010	int hc_reset_ring(xhci_endpoint_t *ep, uint32_t stream_id)
1011	{
1012	xhci_device_t * const dev = xhci_ep_to_dev(ep);
1013	const unsigned dci = endpoint_dci(ep);
1014	uintptr_t addr;
1015
1016	xhci_trb_ring_t *ring = xhci_endpoint_get_ring(ep, stream_id);
1017	xhci_trb_ring_reset_dequeue_state(ring, &addr);
1018
1019	xhci_hc_t * const hc = bus_to_hc(endpoint_get_bus(&ep->base));
1020	return xhci_cmd_sync_inline(hc, SET_TR_DEQUEUE_POINTER,
1021	.slot_id = dev->slot_id,
1022	.endpoint_id = dci,
1023	.stream_id = stream_id,
1024	.dequeue_ptr = addr,
1025	);
1026	}
1027
1028	/**
1029	* @}
1030	*/

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