source: mainline/uspace/drv/bus/usb/xhci/hc.c@ 5cbccd4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5cbccd4 was 5cbccd4, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: register structures

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/*
2 * Copyright (c) 2017 Ondrej Hlavaty
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller data bookkeeping.
34 */
35
36#include <errno.h>
37#include <usb/debug.h>
38#include "debug.h"
39#include "hc.h"
40
41int xhci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
42{
43 assert(code);
44 assert(hw_res);
45
46 usb_log_debug("Gen IRQ code, got %zu IRQs, %zu DMA chs, %zu mem rngs, %zu IO rngs",
47 hw_res->irqs.count,
48 hw_res->dma_channels.count,
49 hw_res->mem_ranges.count,
50 hw_res->io_ranges.count);
51
52 if (hw_res->irqs.count != 1
53 || hw_res->dma_channels.count != 0
54 || hw_res->mem_ranges.count != 1
55 || hw_res->io_ranges.count != 0) {
56 usb_log_debug("Unexpected HW resources, bailing out.");
57 return EINVAL;
58 }
59
60 addr_range_t mmio_range = hw_res->mem_ranges.ranges[0];
61
62 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
63 RNGABSPTR(mmio_range), RNGSZ(mmio_range), hw_res->irqs.irqs[0]);
64
65 xhci_cap_regs_t *cap_regs = NULL;
66 int ret = pio_enable_range(&mmio_range, (void **)&cap_regs);
67 if (ret != EOK)
68 return ret;
69
70 xhci_dump_cap_regs(cap_regs);
71
72 /*
73 * XHCI uses an Interrupter mechanism. Possibly, we want to set it up here.
74 */
75 code->rangecount = 0;
76 code->ranges = NULL;
77 code->cmdcount = 0;
78 code->cmds = NULL;
79
80 return EOK;
81}
82
83int xhci_hc_status(hcd_t *hcd, uint32_t *status)
84{
85 usb_log_info("status");
86 return ENOTSUP;
87}
88
89int xhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
90{
91 usb_log_info("schedule");
92 return ENOTSUP;
93}
94
95void xhci_hc_interrupt(hcd_t *hcd, uint32_t status)
96{
97 usb_log_info("Interrupted!");
98}
99
100
101/**
102 * @}
103 */
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