source: mainline/uspace/drv/bus/usb/xhci/endpoint.c@ 889146e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 889146e was 6b433a8, checked in by Salmelu <salmelu@…>, 8 years ago

Isochronous transfers - endpoint initialization
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File size: 11.8 KB
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1/*
2 * Copyright (c) 2017 Petr Manek
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller endpoint management.
34 */
35
36#include <usb/host/endpoint.h>
37#include <usb/descriptor.h>
38
39#include <errno.h>
40#include <macros.h>
41
42#include "hc.h"
43#include "bus.h"
44#include "commands.h"
45#include "endpoint.h"
46
47int xhci_endpoint_init(xhci_endpoint_t *xhci_ep, xhci_bus_t *xhci_bus)
48{
49 assert(xhci_ep);
50 assert(xhci_bus);
51
52 bus_t *bus = &xhci_bus->base;
53 endpoint_t *ep = &xhci_ep->base;
54
55 endpoint_init(ep, bus);
56
57 return EOK;
58}
59
60void xhci_endpoint_fini(xhci_endpoint_t *xhci_ep)
61{
62 assert(xhci_ep);
63
64 // TODO: Something missed?
65}
66
67static int xhci_endpoint_type(xhci_endpoint_t *ep)
68{
69 const bool in = ep->base.direction == USB_DIRECTION_IN;
70
71 switch (ep->base.transfer_type) {
72 case USB_TRANSFER_CONTROL:
73 return EP_TYPE_CONTROL;
74
75 case USB_TRANSFER_ISOCHRONOUS:
76 return in ? EP_TYPE_ISOCH_IN
77 : EP_TYPE_ISOCH_OUT;
78
79 case USB_TRANSFER_BULK:
80 return in ? EP_TYPE_BULK_IN
81 : EP_TYPE_BULK_OUT;
82
83 case USB_TRANSFER_INTERRUPT:
84 return in ? EP_TYPE_INTERRUPT_IN
85 : EP_TYPE_INTERRUPT_OUT;
86 }
87
88 return EP_TYPE_INVALID;
89}
90
91static bool endpoint_using_streams(xhci_endpoint_t *xhci_ep)
92{
93 return xhci_ep->primary_stream_ctx_array != NULL;
94}
95
96static size_t primary_stream_ctx_array_max_size(xhci_endpoint_t *xhci_ep)
97{
98 if (!xhci_ep->max_streams)
99 return 0;
100
101 /* Section 6.2.3, Table 61 */
102 return 1 << (xhci_ep->max_streams + 1);
103}
104
105// static bool primary_stream_ctx_has_secondary_array(xhci_stream_ctx_t *primary_ctx) {
106// /* Section 6.2.4.1, SCT values */
107// return XHCI_STREAM_SCT(*primary_ctx) >= 2;
108// }
109//
110// static size_t secondary_stream_ctx_array_size(xhci_stream_ctx_t *primary_ctx) {
111// if (XHCI_STREAM_SCT(*primary_ctx) < 2) return 0;
112// return 2 << XHCI_STREAM_SCT(*primary_ctx);
113// }
114
115static void initialize_primary_streams(xhci_hc_t *hc, xhci_endpoint_t *xhci_ep, unsigned count) {
116 for (size_t index = 0; index < count; ++index) {
117 xhci_stream_ctx_t *ctx = &xhci_ep->primary_stream_ctx_array[index];
118 xhci_trb_ring_t *ring = &xhci_ep->primary_stream_rings[index];
119
120 /* Init and register TRB ring for every primary stream */
121 xhci_trb_ring_init(ring);
122 XHCI_STREAM_DEQ_PTR_SET(*ctx, ring->dequeue);
123
124 /* Set to linear stream array */
125 XHCI_STREAM_SCT_SET(*ctx, 1);
126 }
127}
128
129static void setup_stream_context(xhci_endpoint_t *xhci_ep, xhci_ep_ctx_t *ctx, unsigned pstreams) {
130 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(xhci_ep));
131 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, xhci_ep->base.max_packet_size);
132 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, xhci_ep->max_burst);
133 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
134
135 XHCI_EP_MAX_P_STREAMS_SET(*ctx, pstreams);
136 XHCI_EP_TR_DPTR_SET(*ctx, xhci_ep->primary_stream_ctx_dma.phys);
137 // TODO: set HID?
138 XHCI_EP_LSA_SET(*ctx, 1);
139}
140
141int xhci_endpoint_request_streams(xhci_hc_t *hc, xhci_device_t *dev, xhci_endpoint_t *xhci_ep, unsigned count) {
142 if (xhci_ep->base.transfer_type != USB_TRANSFER_BULK
143 || dev->base.speed != USB_SPEED_SUPER) {
144 usb_log_error("Streams are only supported by superspeed bulk endpoints.");
145 return EINVAL;
146 }
147
148 if (!primary_stream_ctx_array_max_size(xhci_ep)) {
149 usb_log_error("Streams are not supported by endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
150 return EINVAL;
151 }
152
153 uint8_t max_psa_size = 2 << XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_PSA_SIZE);
154 if (count > max_psa_size) {
155 // FIXME: We don't support secondary stream arrays yet, so we just give up for this
156 return ENOTSUP;
157 }
158
159 if (count > (unsigned) (1 << xhci_ep->max_streams)) {
160 usb_log_error("Endpoint " XHCI_EP_FMT " supports only %u streams.",
161 XHCI_EP_ARGS(*xhci_ep), (1 << xhci_ep->max_streams));
162 return EINVAL;
163 }
164
165 if (count <= 1024) {
166 usb_log_debug2("Allocating primary stream context array of size %u for endpoint " XHCI_EP_FMT,
167 count, XHCI_EP_ARGS(*xhci_ep));
168 if ((dma_buffer_alloc(&xhci_ep->primary_stream_ctx_dma, count * sizeof(xhci_stream_ctx_t))))
169 return ENOMEM;
170 xhci_ep->primary_stream_ctx_array = xhci_ep->primary_stream_ctx_dma.virt;
171
172 xhci_ep->primary_stream_rings = calloc(count, sizeof(xhci_trb_ring_t));
173 if (!xhci_ep->primary_stream_rings) {
174 dma_buffer_free(&xhci_ep->primary_stream_ctx_dma);
175 return ENOMEM;
176 }
177
178 // FIXME: count should be rounded to nearest power of 2 for xHC, workaround for now
179 count = 1024;
180 // FIXME: pstreams are "log2(count) - 1"
181 const size_t pstreams = 9;
182 xhci_ep->primary_stream_ctx_array_size = count;
183
184 memset(xhci_ep->primary_stream_ctx_array, 0, count * sizeof(xhci_stream_ctx_t));
185 initialize_primary_streams(hc, xhci_ep, count);
186
187 xhci_ep_ctx_t ep_ctx;
188 setup_stream_context(xhci_ep, &ep_ctx, pstreams);
189 return hc_add_endpoint(hc, dev->slot_id, xhci_endpoint_index(xhci_ep), &ep_ctx);
190 }
191 // FIXME: Complex stuff not supported yet
192 return ENOTSUP;
193}
194
195static int xhci_isoch_alloc_transfers(xhci_endpoint_t *xhci_ep) {
196 int i = 0;
197 int err = EOK;
198 while (i < XHCI_ISOCH_BUFFER_COUNT) {
199 xhci_isoch_transfer_t *transfer = xhci_ep->isoch_transfers[i];
200 if (dma_buffer_alloc(&transfer->data, xhci_ep->isoch_max_size)) {
201 err = ENOMEM;
202 break;
203 }
204 transfer->size = 0;
205 ++i;
206 }
207
208 if (err) {
209 --i;
210 while(i >= 0) {
211 dma_buffer_free(&xhci_ep->isoch_transfers[i]->data);
212 --i;
213 }
214 }
215
216 return err;
217}
218
219int xhci_endpoint_alloc_transfer_ds(xhci_endpoint_t *xhci_ep)
220{
221 /* Can't use XHCI_EP_FMT because the endpoint may not have device. */
222 usb_log_debug2("Allocating main transfer ring for endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
223
224 xhci_ep->primary_stream_ctx_array = NULL;
225
226 int err;
227 if ((err = xhci_trb_ring_init(&xhci_ep->ring))) {
228 return err;
229 }
230
231 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
232 if((err = xhci_isoch_alloc_transfers(xhci_ep))) {
233 xhci_trb_ring_fini(&xhci_ep->ring);
234 return err;
235 }
236 }
237
238 return EOK;
239}
240
241void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *xhci_ep)
242{
243 if (endpoint_using_streams(xhci_ep)) {
244 usb_log_debug2("Freeing primary stream context array of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
245
246 // maybe check if LSA, then skip?
247 // for (size_t index = 0; index < primary_stream_ctx_array_size(xhci_ep); ++index) {
248 // xhci_stream_ctx_t *primary_ctx = xhci_ep->primary_stream_ctx_array + index;
249 // if (primary_stream_ctx_has_secondary_array(primary_ctx)) {
250 // // uintptr_t phys = XHCI_STREAM_DEQ_PTR(*primary_ctx);
251 // /* size_t size = */ secondary_stream_ctx_array_size(primary_ctx);
252 // // TODO: somehow map the address to virtual and free the secondary array
253 // }
254 // }
255 for (size_t index = 0; index < xhci_ep->primary_stream_ctx_array_size; ++index) {
256 // FIXME: Get the trb ring associated with stream [index] and fini it
257 }
258 dma_buffer_free(&xhci_ep->primary_stream_ctx_dma);
259 } else {
260 usb_log_debug2("Freeing main transfer ring of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
261
262 xhci_trb_ring_fini(&xhci_ep->ring);
263 }
264}
265
266/** See section 4.5.1 of the xHCI spec.
267 */
268uint8_t xhci_endpoint_dci(xhci_endpoint_t *ep)
269{
270 return (2 * ep->base.endpoint) +
271 (ep->base.transfer_type == USB_TRANSFER_CONTROL
272 || ep->base.direction == USB_DIRECTION_IN);
273}
274
275/** Return an index to the endpoint array. The indices are assigned as follows:
276 * 0 EP0 BOTH
277 * 1 EP1 OUT
278 * 2 EP1 IN
279 *
280 * For control endpoints >0, the IN endpoint index is used.
281 *
282 * The index returned must be usually offset by a number of contexts preceding
283 * the endpoint contexts themselves.
284 */
285uint8_t xhci_endpoint_index(xhci_endpoint_t *ep)
286{
287 return xhci_endpoint_dci(ep) - 1;
288}
289
290static void setup_control_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
291{
292 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
293 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
294 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
295 XHCI_EP_MULT_SET(*ctx, ep->mult);
296 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
297 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
298 XHCI_EP_DCS_SET(*ctx, 1);
299}
300
301static void setup_bulk_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
302{
303 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
304 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
305 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
306 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
307
308 XHCI_EP_MAX_P_STREAMS_SET(*ctx, 0);
309 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
310 XHCI_EP_DCS_SET(*ctx, 1);
311}
312
313static void setup_isoch_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
314{
315 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
316 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
317 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
318 XHCI_EP_MULT_SET(*ctx, ep->mult);
319 XHCI_EP_ERROR_COUNT_SET(*ctx, 0);
320 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
321 XHCI_EP_DCS_SET(*ctx, 1);
322
323 XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(*ctx, ep->isoch_max_size & 0xFFFF);
324 XHCI_EP_MAX_ESIT_PAYLOAD_HI_SET(*ctx, (ep->isoch_max_size >> 16) & 0xFF);
325}
326
327static void setup_interrupt_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
328{
329 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
330 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
331 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
332 XHCI_EP_MULT_SET(*ctx, 0);
333 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
334 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
335 XHCI_EP_DCS_SET(*ctx, 1);
336 // TODO: max ESIT payload
337}
338
339typedef void (*setup_ep_ctx_helper)(xhci_endpoint_t *, xhci_ep_ctx_t *);
340
341static const setup_ep_ctx_helper setup_ep_ctx_helpers[] = {
342 [USB_TRANSFER_CONTROL] = setup_control_ep_ctx,
343 [USB_TRANSFER_ISOCHRONOUS] = setup_isoch_ep_ctx,
344 [USB_TRANSFER_BULK] = setup_bulk_ep_ctx,
345 [USB_TRANSFER_INTERRUPT] = setup_interrupt_ep_ctx,
346};
347
348void xhci_setup_endpoint_context(xhci_endpoint_t *ep, xhci_ep_ctx_t *ep_ctx)
349{
350 assert(ep);
351 assert(ep_ctx);
352
353 usb_transfer_type_t tt = ep->base.transfer_type;
354 assert(tt < ARRAY_SIZE(setup_ep_ctx_helpers));
355
356 memset(ep_ctx, 0, sizeof(*ep_ctx));
357 setup_ep_ctx_helpers[tt](ep, ep_ctx);
358}
359
360int xhci_device_add_endpoint(xhci_device_t *dev, xhci_endpoint_t *ep)
361{
362 assert(dev);
363 assert(ep);
364
365 /* Offline devices don't create new endpoints other than EP0. */
366 if (!dev->online && ep->base.endpoint > 0) {
367 return EAGAIN;
368 }
369
370 const usb_endpoint_t ep_num = ep->base.endpoint;
371
372 if (dev->endpoints[ep_num])
373 return EEXIST;
374
375 /* Device reference */
376 endpoint_add_ref(&ep->base);
377 ep->base.device = &dev->base;
378 dev->endpoints[ep_num] = ep;
379
380 return EOK;
381}
382
383void xhci_device_remove_endpoint(xhci_endpoint_t *ep)
384{
385 assert(ep);
386 xhci_device_t *dev = xhci_device_get(ep->base.device);
387
388 assert(dev->endpoints[ep->base.endpoint]);
389 dev->endpoints[ep->base.endpoint] = NULL;
390 ep->base.device = NULL;
391
392 endpoint_del_ref(&ep->base);
393}
394
395xhci_endpoint_t *xhci_device_get_endpoint(xhci_device_t *dev, usb_endpoint_t ep)
396{
397 return dev->endpoints[ep];
398}
399
400/**
401 * @}
402 */
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