source: mainline/uspace/drv/bus/usb/xhci/endpoint.c@ ef1a3a8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ef1a3a8 was ef1a3a8, checked in by Petr Manek <petr.manek@…>, 8 years ago

Added memory structure for stream TRB rings. Implemented their initialization. Fixed white space.
  • Property mode set to 100644
File size: 11.1 KB
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1/*
2 * Copyright (c) 2017 Petr Manek
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller endpoint management.
34 */
35
36#include <usb/host/utils/malloc32.h>
37#include <usb/host/endpoint.h>
38#include <usb/descriptor.h>
39
40#include <errno.h>
41#include <macros.h>
42
43#include "hc.h"
44#include "bus.h"
45#include "commands.h"
46#include "endpoint.h"
47
48int xhci_endpoint_init(xhci_endpoint_t *xhci_ep, xhci_bus_t *xhci_bus)
49{
50 assert(xhci_ep);
51 assert(xhci_bus);
52
53 bus_t *bus = &xhci_bus->base;
54 endpoint_t *ep = &xhci_ep->base;
55
56 endpoint_init(ep, bus);
57
58 return EOK;
59}
60
61void xhci_endpoint_fini(xhci_endpoint_t *xhci_ep)
62{
63 assert(xhci_ep);
64
65 // TODO: Something missed?
66}
67
68static int xhci_endpoint_type(xhci_endpoint_t *ep)
69{
70 const bool in = ep->base.direction == USB_DIRECTION_IN;
71
72 switch (ep->base.transfer_type) {
73 case USB_TRANSFER_CONTROL:
74 return EP_TYPE_CONTROL;
75
76 case USB_TRANSFER_ISOCHRONOUS:
77 return in ? EP_TYPE_ISOCH_IN
78 : EP_TYPE_ISOCH_OUT;
79
80 case USB_TRANSFER_BULK:
81 return in ? EP_TYPE_BULK_IN
82 : EP_TYPE_BULK_OUT;
83
84 case USB_TRANSFER_INTERRUPT:
85 return in ? EP_TYPE_INTERRUPT_IN
86 : EP_TYPE_INTERRUPT_OUT;
87 }
88
89 return EP_TYPE_INVALID;
90}
91
92static bool endpoint_using_streams(xhci_endpoint_t *xhci_ep)
93{
94 return xhci_ep->primary_stream_ctx_array != NULL;
95}
96
97static size_t primary_stream_ctx_array_max_size(xhci_endpoint_t *xhci_ep)
98{
99 if (!xhci_ep->max_streams)
100 return 0;
101
102 /* Section 6.2.3, Table 61 */
103 return 1 << (xhci_ep->max_streams + 1);
104}
105
106// static bool primary_stream_ctx_has_secondary_array(xhci_stream_ctx_t *primary_ctx) {
107// /* Section 6.2.4.1, SCT values */
108// return XHCI_STREAM_SCT(*primary_ctx) >= 2;
109// }
110//
111// static size_t secondary_stream_ctx_array_size(xhci_stream_ctx_t *primary_ctx) {
112// if (XHCI_STREAM_SCT(*primary_ctx) < 2) return 0;
113// return 2 << XHCI_STREAM_SCT(*primary_ctx);
114// }
115
116static void initialize_primary_streams(xhci_hc_t *hc, xhci_endpoint_t *xhci_ep, unsigned count) {
117 for (size_t index = 0; index < count; ++index) {
118 xhci_stream_ctx_t *ctx = &xhci_ep->primary_stream_ctx_array[index];
119 xhci_trb_ring_t *ring = &xhci_ep->primary_stream_rings[index];
120
121 /* Init and register TRB ring for every primary stream */
122 xhci_trb_ring_init(ring);
123 XHCI_STREAM_DEQ_PTR_SET(*ctx, ring->dequeue);
124
125 /* Set to linear stream array */
126 XHCI_STREAM_SCT_SET(*ctx, 1);
127 }
128}
129
130static void setup_stream_context(xhci_endpoint_t *xhci_ep, xhci_ep_ctx_t *ctx, unsigned pstreams) {
131 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(xhci_ep));
132 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, xhci_ep->base.max_packet_size);
133 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, xhci_ep->max_burst);
134 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
135
136 XHCI_EP_MAX_P_STREAMS_SET(*ctx, pstreams);
137 XHCI_EP_TR_DPTR_SET(*ctx, addr_to_phys(xhci_ep->primary_stream_ctx_array));
138 // TODO: set HID?
139 XHCI_EP_LSA_SET(*ctx, 1);
140}
141
142int xhci_endpoint_request_streams(xhci_hc_t *hc, xhci_device_t *dev, xhci_endpoint_t *xhci_ep, unsigned count) {
143 if (xhci_ep->base.transfer_type != USB_TRANSFER_BULK
144 || xhci_ep->base.speed != USB_SPEED_SUPER) {
145 usb_log_error("Streams are only supported by superspeed bulk endpoints.");
146 return EINVAL;
147 }
148
149 if (!primary_stream_ctx_array_max_size(xhci_ep)) {
150 usb_log_error("Streams are not supported by endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
151 return EINVAL;
152 }
153
154 uint8_t max_psa_size = 2 << XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_PSA_SIZE);
155 if (count > max_psa_size) {
156 // FIXME: We don't support secondary stream arrays yet, so we just give up for this
157 return ENOTSUP;
158 }
159
160 if (count > (unsigned) (1 << xhci_ep->max_streams)) {
161 usb_log_error("Endpoint " XHCI_EP_FMT " supports only %u streams.",
162 XHCI_EP_ARGS(*xhci_ep), (1 << xhci_ep->max_streams));
163 return EINVAL;
164 }
165
166 if (count <= 1024) {
167 usb_log_debug2("Allocating primary stream context array of size %u for endpoint " XHCI_EP_FMT,
168 count, XHCI_EP_ARGS(*xhci_ep));
169 xhci_ep->primary_stream_ctx_array = malloc32(count * sizeof(xhci_stream_ctx_t));
170 if (!xhci_ep->primary_stream_ctx_array) {
171 return ENOMEM;
172 }
173
174 xhci_ep->primary_stream_rings = calloc(count, sizeof(xhci_trb_ring_t));
175 if (!xhci_ep->primary_stream_rings) {
176 free32(xhci_ep->primary_stream_ctx_array);
177 return ENOMEM;
178 }
179
180 // FIXME: count should be rounded to nearest power of 2 for xHC, workaround for now
181 count = 1024;
182 // FIXME: pstreams are "log2(count) - 1"
183 const size_t pstreams = 9;
184 xhci_ep->primary_stream_ctx_array_size = count;
185
186 memset(xhci_ep->primary_stream_ctx_array, 0, count * sizeof(xhci_stream_ctx_t));
187 initialize_primary_streams(hc, xhci_ep, count);
188
189 xhci_ep_ctx_t ep_ctx;
190 setup_stream_context(xhci_ep, &ep_ctx, pstreams);
191 return hc_add_endpoint(hc, dev->slot_id, xhci_endpoint_index(xhci_ep), &ep_ctx);
192 }
193 // FIXME: Complex stuff not supported yet
194 return ENOTSUP;
195}
196
197int xhci_endpoint_alloc_transfer_ds(xhci_endpoint_t *xhci_ep)
198{
199 /* Can't use XHCI_EP_FMT because the endpoint may not have device. */
200 usb_log_debug2("Allocating main transfer ring for endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
201
202 xhci_ep->primary_stream_ctx_array = NULL;
203
204 int err;
205 if ((err = xhci_trb_ring_init(&xhci_ep->ring))) {
206 return err;
207 }
208
209 return EOK;
210}
211
212void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *xhci_ep)
213{
214 if (endpoint_using_streams(xhci_ep)) {
215 usb_log_debug2("Freeing primary stream context array of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
216
217 // maybe check if LSA, then skip?
218 // for (size_t index = 0; index < primary_stream_ctx_array_size(xhci_ep); ++index) {
219 // xhci_stream_ctx_t *primary_ctx = xhci_ep->primary_stream_ctx_array + index;
220 // if (primary_stream_ctx_has_secondary_array(primary_ctx)) {
221 // // uintptr_t phys = XHCI_STREAM_DEQ_PTR(*primary_ctx);
222 // /* size_t size = */ secondary_stream_ctx_array_size(primary_ctx);
223 // // TODO: somehow map the address to virtual and free the secondary array
224 // }
225 // }
226 for (size_t index = 0; index < xhci_ep->primary_stream_ctx_array_size; ++index) {
227 // FIXME: Get the trb ring associated with stream [index] and fini it
228 }
229 free32(xhci_ep->primary_stream_ctx_array);
230 } else {
231 usb_log_debug2("Freeing main transfer ring of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
232
233 xhci_trb_ring_fini(&xhci_ep->ring);
234 }
235}
236
237/** See section 4.5.1 of the xHCI spec.
238 */
239uint8_t xhci_endpoint_dci(xhci_endpoint_t *ep)
240{
241 return (2 * ep->base.endpoint) +
242 (ep->base.transfer_type == USB_TRANSFER_CONTROL
243 || ep->base.direction == USB_DIRECTION_IN);
244}
245
246/** Return an index to the endpoint array. The indices are assigned as follows:
247 * 0 EP0 BOTH
248 * 1 EP1 OUT
249 * 2 EP1 IN
250 *
251 * For control endpoints >0, the IN endpoint index is used.
252 *
253 * The index returned must be usually offset by a number of contexts preceding
254 * the endpoint contexts themselves.
255 */
256uint8_t xhci_endpoint_index(xhci_endpoint_t *ep)
257{
258 return xhci_endpoint_dci(ep) - 1;
259}
260
261static void setup_control_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
262{
263 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
264 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
265 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
266 XHCI_EP_MULT_SET(*ctx, ep->mult);
267 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
268 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
269 XHCI_EP_DCS_SET(*ctx, 1);
270}
271
272static void setup_bulk_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
273{
274 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
275 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
276 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
277 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
278
279 XHCI_EP_MAX_P_STREAMS_SET(*ctx, 0);
280 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
281 XHCI_EP_DCS_SET(*ctx, 1);
282}
283
284static void setup_isoch_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
285{
286 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
287 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
288 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
289 XHCI_EP_MULT_SET(*ctx, ep->mult);
290 XHCI_EP_ERROR_COUNT_SET(*ctx, 0);
291 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
292 XHCI_EP_DCS_SET(*ctx, 1);
293 // TODO: max ESIT payload
294}
295
296static void setup_interrupt_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
297{
298 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
299 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
300 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
301 XHCI_EP_MULT_SET(*ctx, 0);
302 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
303 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
304 XHCI_EP_DCS_SET(*ctx, 1);
305 // TODO: max ESIT payload
306}
307
308typedef void (*setup_ep_ctx_helper)(xhci_endpoint_t *, xhci_ep_ctx_t *);
309
310static const setup_ep_ctx_helper setup_ep_ctx_helpers[] = {
311 [USB_TRANSFER_CONTROL] = setup_control_ep_ctx,
312 [USB_TRANSFER_ISOCHRONOUS] = setup_isoch_ep_ctx,
313 [USB_TRANSFER_BULK] = setup_bulk_ep_ctx,
314 [USB_TRANSFER_INTERRUPT] = setup_interrupt_ep_ctx,
315};
316
317void xhci_setup_endpoint_context(xhci_endpoint_t *ep, xhci_ep_ctx_t *ep_ctx)
318{
319 assert(ep);
320 assert(ep_ctx);
321
322 usb_transfer_type_t tt = ep->base.transfer_type;
323 assert(tt < ARRAY_SIZE(setup_ep_ctx_helpers));
324
325 memset(ep_ctx, 0, sizeof(*ep_ctx));
326 setup_ep_ctx_helpers[tt](ep, ep_ctx);
327}
328
329int xhci_device_add_endpoint(xhci_device_t *dev, xhci_endpoint_t *ep)
330{
331 assert(dev);
332 assert(ep);
333
334 /* Offline devices don't create new endpoints other than EP0. */
335 if (!dev->online && ep->base.endpoint > 0) {
336 return EAGAIN;
337 }
338
339 const usb_endpoint_t ep_num = ep->base.endpoint;
340
341 if (dev->endpoints[ep_num])
342 return EEXIST;
343
344 /* Device reference */
345 endpoint_add_ref(&ep->base);
346 ep->base.device = &dev->base;
347 dev->endpoints[ep_num] = ep;
348
349 return EOK;
350}
351
352void xhci_device_remove_endpoint(xhci_endpoint_t *ep)
353{
354 assert(ep);
355 xhci_device_t *dev = xhci_device_get(ep->base.device);
356
357 assert(dev->endpoints[ep->base.endpoint]);
358 dev->endpoints[ep->base.endpoint] = NULL;
359 ep->base.device = NULL;
360
361 endpoint_del_ref(&ep->base);
362}
363
364xhci_endpoint_t *xhci_device_get_endpoint(xhci_device_t *dev, usb_endpoint_t ep)
365{
366 return dev->endpoints[ep];
367}
368
369/**
370 * @}
371 */
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