source: mainline/uspace/drv/bus/usb/xhci/commands.c@ d1d7a92

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d1d7a92 was d1d7a92, checked in by Petr Manek <petr.manek@…>, 8 years ago

Added option to enqueue multiple TDs at once. Demoted some log messages.
  • Property mode set to 100644
File size: 13.4 KB
Line 
1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "commands.h"
41#include "debug.h"
42#include "hc.h"
43#include "hw_struct/context.h"
44#include "hw_struct/trb.h"
45
46#define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
47#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
48#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
49#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
50#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
51#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
52#define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
53
54/**
55 * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
56 */
57#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
58#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
59
60#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
61#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
62#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
63
64int xhci_init_commands(xhci_hc_t *hc)
65{
66 assert(hc);
67
68 list_initialize(&hc->commands);
69 return EOK;
70}
71
72void xhci_fini_commands(xhci_hc_t *hc)
73{
74 // Note: Untested.
75 assert(hc);
76}
77
78int xhci_cmd_wait(xhci_cmd_t *cmd, suseconds_t timeout)
79{
80 int rv = EOK;
81
82 fibril_mutex_lock(&cmd->completed_mtx);
83 while (!cmd->completed) {
84 usb_log_debug2("Waiting for event completion: going to sleep.");
85 rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
86
87 usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
88 if (rv == ETIMEOUT)
89 break;
90 }
91 fibril_mutex_unlock(&cmd->completed_mtx);
92
93 return rv;
94}
95
96xhci_cmd_t *xhci_cmd_alloc(void)
97{
98 xhci_cmd_t *cmd = malloc(sizeof(xhci_cmd_t));
99 xhci_cmd_init(cmd);
100
101 usb_log_debug2("Allocating cmd on the heap. Don't forget to deallocate it!");
102 return cmd;
103}
104
105void xhci_cmd_init(xhci_cmd_t *cmd)
106{
107 memset(cmd, 0, sizeof(*cmd));
108
109 link_initialize(&cmd->link);
110
111 fibril_mutex_initialize(&cmd->completed_mtx);
112 fibril_condvar_initialize(&cmd->completed_cv);
113}
114
115void xhci_cmd_fini(xhci_cmd_t *cmd)
116{
117 list_remove(&cmd->link);
118}
119
120void xhci_cmd_free(xhci_cmd_t *cmd)
121{
122 xhci_cmd_fini(cmd);
123 free(cmd);
124}
125
126static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
127{
128 link_t *cmd_link = list_first(&hc->commands);
129
130 while (cmd_link != NULL) {
131 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
132
133 if (cmd->trb_phys == phys)
134 break;
135
136 cmd_link = list_next(cmd_link, &hc->commands);
137 }
138
139 if (cmd_link != NULL) {
140 list_remove(cmd_link);
141
142 return list_get_instance(cmd_link, xhci_cmd_t, link);
143 }
144
145 return NULL;
146}
147
148static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
149{
150 assert(hc);
151 assert(cmd);
152
153 list_append(&cmd->link, &hc->commands);
154
155 xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
156 hc_ring_doorbell(hc, doorbell, target);
157
158 usb_log_debug2("HC(%p): Sent command:", hc);
159 xhci_dump_trb(&cmd->trb);
160
161 return EOK;
162}
163
164void xhci_stop_command_ring(xhci_hc_t *hc)
165{
166 assert(hc);
167
168 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
169
170 /**
171 * Note: There is a bug in qemu that checks CS only when CRCR_HI
172 * is written, this (and the read/write in abort) ensures
173 * the command rings stops.
174 */
175 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
176}
177
178void xhci_abort_command_ring(xhci_hc_t *hc)
179{
180 assert(hc);
181
182 XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
183 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
184}
185
186void xhci_start_command_ring(xhci_hc_t *hc)
187{
188 assert(hc);
189
190 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
191 hc_ring_doorbell(hc, 0, 0);
192}
193
194static const char *trb_codes [] = {
195#define TRBC(t) [XHCI_TRBC_##t] = #t
196 TRBC(INVALID),
197 TRBC(SUCCESS),
198 TRBC(DATA_BUFFER_ERROR),
199 TRBC(BABBLE_DETECTED_ERROR),
200 TRBC(USB_TRANSACTION_ERROR),
201 TRBC(TRB_ERROR),
202 TRBC(STALL_ERROR),
203 TRBC(RESOURCE_ERROR),
204 TRBC(BANDWIDTH_ERROR),
205 TRBC(NO_SLOTS_ERROR),
206 TRBC(INVALID_STREAM_ERROR),
207 TRBC(SLOT_NOT_ENABLED_ERROR),
208 TRBC(EP_NOT_ENABLED_ERROR),
209 TRBC(SHORT_PACKET),
210 TRBC(RING_UNDERRUN),
211 TRBC(RING_OVERRUN),
212 TRBC(VF_EVENT_RING_FULL),
213 TRBC(PARAMETER_ERROR),
214 TRBC(BANDWIDTH_OVERRUN_ERROR),
215 TRBC(CONTEXT_STATE_ERROR),
216 TRBC(NO_PING_RESPONSE_ERROR),
217 TRBC(EVENT_RING_FULL_ERROR),
218 TRBC(INCOMPATIBLE_DEVICE_ERROR),
219 TRBC(MISSED_SERVICE_ERROR),
220 TRBC(COMMAND_RING_STOPPED),
221 TRBC(COMMAND_ABORTED),
222 TRBC(STOPPED),
223 TRBC(STOPPED_LENGTH_INVALID),
224 TRBC(STOPPED_SHORT_PACKET),
225 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
226 [30] = "<reserved>",
227 TRBC(ISOCH_BUFFER_OVERRUN),
228 TRBC(EVENT_LOST_ERROR),
229 TRBC(UNDEFINED_ERROR),
230 TRBC(INVALID_STREAM_ID_ERROR),
231 TRBC(SECONDARY_BANDWIDTH_ERROR),
232 TRBC(SPLIT_TRANSACTION_ERROR),
233 [XHCI_TRBC_MAX] = NULL
234#undef TRBC
235};
236
237static void report_error(int code)
238{
239 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
240 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
241 else
242 usb_log_error("Command resulted in reserved or vendor specific error.");
243}
244
245int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
246{
247 assert(hc);
248
249 xhci_trb_clean(&cmd->trb);
250
251 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
252
253 return enqueue_command(hc, cmd, 0, 0);
254}
255
256int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
257{
258 assert(hc);
259
260 xhci_trb_clean(&cmd->trb);
261
262 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
263 cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
264
265 return enqueue_command(hc, cmd, 0, 0);
266}
267
268int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
269{
270 assert(hc);
271 assert(cmd);
272
273 xhci_trb_clean(&cmd->trb);
274
275 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
276 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
277
278 return enqueue_command(hc, cmd, 0, 0);
279}
280
281int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
282{
283 assert(hc);
284 assert(cmd);
285 assert(ictx);
286
287 /**
288 * TODO: Requirements for this command:
289 * dcbaa[slot_id] is properly sized and initialized
290 * ictx has valids slot context and endpoint 0, all
291 * other should be ignored at this point (see section 4.6.5).
292 */
293
294 xhci_trb_clean(&cmd->trb);
295
296 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
297 TRB_SET_ICTX(cmd->trb, phys_addr);
298
299 /**
300 * Note: According to section 6.4.3.4, we can set the 9th bit
301 * of the control field of the trb (BSR) to 1 and then the xHC
302 * will not issue the SET_ADDRESS request to the USB device.
303 * This can be used to provide compatibility with legacy USB devices
304 * that require their device descriptor to be read before such request.
305 */
306 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
307 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
308
309 return enqueue_command(hc, cmd, 0, 0);
310}
311
312int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
313{
314 assert(hc);
315 assert(cmd);
316 assert(ictx);
317
318 xhci_trb_clean(&cmd->trb);
319
320 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
321 TRB_SET_ICTX(cmd->trb, phys_addr);
322
323 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
324 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
325
326 return enqueue_command(hc, cmd, 0, 0);
327}
328
329int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
330{
331 assert(hc);
332 assert(cmd);
333 assert(ictx);
334
335 /**
336 * Note: All Drop Context flags of the input context shall be 0,
337 * all Add Context flags shall be initialize to indicate IDs
338 * of the contexts affected by the command.
339 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
340 */
341 xhci_trb_clean(&cmd->trb);
342
343 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
344 TRB_SET_ICTX(cmd->trb, phys_addr);
345
346 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
347 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
348
349 return enqueue_command(hc, cmd, 0, 0);
350}
351
352int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
353{
354 assert(hc);
355 assert(cmd);
356
357 /**
358 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
359 * information about this flag.
360 */
361 xhci_trb_clean(&cmd->trb);
362
363 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
364 TRB_SET_TCS(cmd->trb, tcs);
365 TRB_SET_EP(cmd->trb, ep_id);
366 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
367
368 return enqueue_command(hc, cmd, 0, 0);
369}
370
371int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
372{
373 assert(hc);
374 assert(cmd);
375
376 xhci_trb_clean(&cmd->trb);
377
378 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
379 TRB_SET_EP(cmd->trb, ep_id);
380 TRB_SET_SUSP(cmd->trb, susp);
381 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
382
383 return enqueue_command(hc, cmd, 0, 0);
384}
385
386int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
387 uintptr_t dequeue_ptr, uint16_t stream_id,
388 uint32_t ep_id)
389{
390 assert(hc);
391 assert(cmd);
392
393 xhci_trb_clean(&cmd->trb);
394
395 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
396 TRB_SET_EP(cmd->trb, ep_id);
397 TRB_SET_STREAM(cmd->trb, stream_id);
398 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
399 TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
400
401 /**
402 * TODO: Set DCS (see section 4.6.10).
403 */
404
405 return enqueue_command(hc, cmd, 0, 0);
406}
407
408int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
409{
410 assert(hc);
411 assert(cmd);
412
413 xhci_trb_clean(&cmd->trb);
414
415 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
416 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
417
418 return enqueue_command(hc, cmd, 0, 0);
419}
420
421int xhci_get_port_bandwidth_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
422 xhci_port_bandwidth_ctx_t *ctx, uint8_t device_speed)
423{
424 assert(hc);
425 assert(cmd);
426
427 xhci_trb_clean(&cmd->trb);
428
429 uint64_t phys_addr = (uint64_t) addr_to_phys(ctx);
430 TRB_SET_ICTX(cmd->trb, phys_addr);
431
432 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
433 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
434 TRB_SET_DEV_SPEED(cmd->trb, device_speed);
435
436 return enqueue_command(hc, cmd, 0, 0);
437}
438
439int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
440{
441 // TODO: Update dequeue ptrs.
442 assert(hc);
443 assert(trb);
444
445 usb_log_debug2("HC(%p) Command completed.", hc);
446
447 int code;
448 uint64_t phys;
449 xhci_cmd_t *command;
450
451 code = TRB_GET_CODE(*trb);
452 phys = TRB_GET_PHYS(*trb);;
453 command = get_command(hc, phys);
454 if (command == NULL) {
455 // TODO: STOP & ABORT may not have command structs in the list!
456 usb_log_warning("No command struct for this completion event found.");
457
458 if (code != XHCI_TRBC_SUCCESS)
459 report_error(code);
460
461 return EOK;
462 }
463
464 command->status = code;
465 command->slot_id = TRB_GET_SLOT(*trb);
466
467 usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
468 if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
469 if (code != XHCI_TRBC_SUCCESS) {
470 report_error(code);
471 xhci_dump_trb(&command->trb);
472 }
473 }
474
475 switch (TRB_TYPE(command->trb)) {
476 case XHCI_TRB_TYPE_NO_OP_CMD:
477 assert(code == XHCI_TRBC_TRB_ERROR);
478 break;
479 case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
480 break;
481 case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
482 break;
483 case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
484 break;
485 case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
486 break;
487 case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
488 break;
489 case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
490 break;
491 case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
492 // Note: If the endpoint was in the middle of a transfer, then the xHC
493 // will add a Transfer TRB before the Event TRB, research that and
494 // handle it appropriately!
495 break;
496 case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
497 break;
498 default:
499 usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
500
501 command->completed = true;
502 return ENAK;
503 }
504
505 fibril_mutex_lock(&command->completed_mtx);
506 command->completed = true;
507 fibril_condvar_broadcast(&command->completed_cv);
508 fibril_mutex_unlock(&command->completed_mtx);
509
510 return EOK;
511}
512
513
514/**
515 * @}
516 */
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