source: mainline/uspace/drv/bus/usb/xhci/commands.c@ 894f58c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 894f58c was b724494, checked in by Petr Manek <petr.manek@…>, 8 years ago

Moved some code from RH to HC. Simplified device address process. Issuing deconfigure device command.
  • Property mode set to 100644
File size: 13.8 KB
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1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "commands.h"
41#include "debug.h"
42#include "hc.h"
43#include "hw_struct/context.h"
44#include "hw_struct/trb.h"
45
46#define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
47#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
48#define TRB_SET_DC(trb, dc) (trb).control |= host2xhci(32, (dc) << 9)
49#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
50#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
51#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
52#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
53#define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
54
55/**
56 * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
57 */
58#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
59#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
60
61#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
62#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
63#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
64
65int xhci_init_commands(xhci_hc_t *hc)
66{
67 assert(hc);
68
69 list_initialize(&hc->commands);
70
71 fibril_mutex_initialize(&hc->commands_mtx);
72
73 return EOK;
74}
75
76void xhci_fini_commands(xhci_hc_t *hc)
77{
78 // Note: Untested.
79 assert(hc);
80}
81
82int xhci_cmd_wait(xhci_cmd_t *cmd, suseconds_t timeout)
83{
84 int rv = EOK;
85
86 fibril_mutex_lock(&cmd->completed_mtx);
87 while (!cmd->completed) {
88 usb_log_debug2("Waiting for event completion: going to sleep.");
89 rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
90
91 usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
92 if (rv == ETIMEOUT)
93 break;
94 }
95 fibril_mutex_unlock(&cmd->completed_mtx);
96
97 return rv;
98}
99
100xhci_cmd_t *xhci_cmd_alloc(void)
101{
102 xhci_cmd_t *cmd = malloc(sizeof(xhci_cmd_t));
103 xhci_cmd_init(cmd);
104
105 usb_log_debug2("Allocating cmd on the heap. Don't forget to deallocate it!");
106 return cmd;
107}
108
109void xhci_cmd_init(xhci_cmd_t *cmd)
110{
111 memset(cmd, 0, sizeof(*cmd));
112
113 link_initialize(&cmd->link);
114
115 fibril_mutex_initialize(&cmd->completed_mtx);
116 fibril_condvar_initialize(&cmd->completed_cv);
117}
118
119void xhci_cmd_fini(xhci_cmd_t *cmd)
120{
121 list_remove(&cmd->link);
122}
123
124void xhci_cmd_free(xhci_cmd_t *cmd)
125{
126 xhci_cmd_fini(cmd);
127 free(cmd);
128}
129
130static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
131{
132 fibril_mutex_lock(&hc->commands_mtx);
133
134 link_t *cmd_link = list_first(&hc->commands);
135
136 while (cmd_link != NULL) {
137 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
138
139 if (cmd->trb_phys == phys)
140 break;
141
142 cmd_link = list_next(cmd_link, &hc->commands);
143 }
144
145 if (cmd_link != NULL) {
146 list_remove(cmd_link);
147 fibril_mutex_unlock(&hc->commands_mtx);
148
149 return list_get_instance(cmd_link, xhci_cmd_t, link);
150 }
151
152 fibril_mutex_unlock(&hc->commands_mtx);
153 return NULL;
154}
155
156static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
157{
158 assert(hc);
159 assert(cmd);
160
161 fibril_mutex_lock(&hc->commands_mtx);
162 list_append(&cmd->link, &hc->commands);
163 fibril_mutex_unlock(&hc->commands_mtx);
164
165 xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
166 hc_ring_doorbell(hc, doorbell, target);
167
168 usb_log_debug2("HC(%p): Sent command:", hc);
169 xhci_dump_trb(&cmd->trb);
170
171 return EOK;
172}
173
174void xhci_stop_command_ring(xhci_hc_t *hc)
175{
176 assert(hc);
177
178 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
179
180 /**
181 * Note: There is a bug in qemu that checks CS only when CRCR_HI
182 * is written, this (and the read/write in abort) ensures
183 * the command rings stops.
184 */
185 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
186}
187
188void xhci_abort_command_ring(xhci_hc_t *hc)
189{
190 assert(hc);
191
192 XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
193 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
194}
195
196void xhci_start_command_ring(xhci_hc_t *hc)
197{
198 assert(hc);
199
200 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
201 hc_ring_doorbell(hc, 0, 0);
202}
203
204static const char *trb_codes [] = {
205#define TRBC(t) [XHCI_TRBC_##t] = #t
206 TRBC(INVALID),
207 TRBC(SUCCESS),
208 TRBC(DATA_BUFFER_ERROR),
209 TRBC(BABBLE_DETECTED_ERROR),
210 TRBC(USB_TRANSACTION_ERROR),
211 TRBC(TRB_ERROR),
212 TRBC(STALL_ERROR),
213 TRBC(RESOURCE_ERROR),
214 TRBC(BANDWIDTH_ERROR),
215 TRBC(NO_SLOTS_ERROR),
216 TRBC(INVALID_STREAM_ERROR),
217 TRBC(SLOT_NOT_ENABLED_ERROR),
218 TRBC(EP_NOT_ENABLED_ERROR),
219 TRBC(SHORT_PACKET),
220 TRBC(RING_UNDERRUN),
221 TRBC(RING_OVERRUN),
222 TRBC(VF_EVENT_RING_FULL),
223 TRBC(PARAMETER_ERROR),
224 TRBC(BANDWIDTH_OVERRUN_ERROR),
225 TRBC(CONTEXT_STATE_ERROR),
226 TRBC(NO_PING_RESPONSE_ERROR),
227 TRBC(EVENT_RING_FULL_ERROR),
228 TRBC(INCOMPATIBLE_DEVICE_ERROR),
229 TRBC(MISSED_SERVICE_ERROR),
230 TRBC(COMMAND_RING_STOPPED),
231 TRBC(COMMAND_ABORTED),
232 TRBC(STOPPED),
233 TRBC(STOPPED_LENGTH_INVALID),
234 TRBC(STOPPED_SHORT_PACKET),
235 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
236 [30] = "<reserved>",
237 TRBC(ISOCH_BUFFER_OVERRUN),
238 TRBC(EVENT_LOST_ERROR),
239 TRBC(UNDEFINED_ERROR),
240 TRBC(INVALID_STREAM_ID_ERROR),
241 TRBC(SECONDARY_BANDWIDTH_ERROR),
242 TRBC(SPLIT_TRANSACTION_ERROR),
243 [XHCI_TRBC_MAX] = NULL
244#undef TRBC
245};
246
247static void report_error(int code)
248{
249 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
250 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
251 else
252 usb_log_error("Command resulted in reserved or vendor specific error.");
253}
254
255int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
256{
257 assert(hc);
258
259 xhci_trb_clean(&cmd->trb);
260
261 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
262
263 return enqueue_command(hc, cmd, 0, 0);
264}
265
266int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
267{
268 assert(hc);
269
270 xhci_trb_clean(&cmd->trb);
271
272 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
273 cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
274
275 return enqueue_command(hc, cmd, 0, 0);
276}
277
278int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
279{
280 assert(hc);
281 assert(cmd);
282
283 xhci_trb_clean(&cmd->trb);
284
285 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
286 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
287
288 return enqueue_command(hc, cmd, 0, 0);
289}
290
291int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
292{
293 assert(hc);
294 assert(cmd);
295 assert(ictx);
296
297 /**
298 * TODO: Requirements for this command:
299 * dcbaa[slot_id] is properly sized and initialized
300 * ictx has valids slot context and endpoint 0, all
301 * other should be ignored at this point (see section 4.6.5).
302 */
303
304 xhci_trb_clean(&cmd->trb);
305
306 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
307 TRB_SET_ICTX(cmd->trb, phys_addr);
308
309 /**
310 * Note: According to section 6.4.3.4, we can set the 9th bit
311 * of the control field of the trb (BSR) to 1 and then the xHC
312 * will not issue the SET_ADDRESS request to the USB device.
313 * This can be used to provide compatibility with legacy USB devices
314 * that require their device descriptor to be read before such request.
315 */
316 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
317 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
318
319 return enqueue_command(hc, cmd, 0, 0);
320}
321
322int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
323{
324 assert(hc);
325 assert(cmd);
326
327 xhci_trb_clean(&cmd->trb);
328
329 if (!cmd->deconfigure) {
330 /* If the DC flag is on, input context is not evaluated. */
331 assert(ictx);
332
333 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
334 TRB_SET_ICTX(cmd->trb, phys_addr);
335 }
336
337 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
338 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
339 TRB_SET_DC(cmd->trb, cmd->deconfigure);
340
341 return enqueue_command(hc, cmd, 0, 0);
342}
343
344int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
345{
346 assert(hc);
347 assert(cmd);
348 assert(ictx);
349
350 /**
351 * Note: All Drop Context flags of the input context shall be 0,
352 * all Add Context flags shall be initialize to indicate IDs
353 * of the contexts affected by the command.
354 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
355 */
356 xhci_trb_clean(&cmd->trb);
357
358 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
359 TRB_SET_ICTX(cmd->trb, phys_addr);
360
361 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
362 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
363
364 return enqueue_command(hc, cmd, 0, 0);
365}
366
367int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
368{
369 assert(hc);
370 assert(cmd);
371
372 /**
373 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
374 * information about this flag.
375 */
376 xhci_trb_clean(&cmd->trb);
377
378 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
379 TRB_SET_TCS(cmd->trb, tcs);
380 TRB_SET_EP(cmd->trb, ep_id);
381 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
382
383 return enqueue_command(hc, cmd, 0, 0);
384}
385
386int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
387{
388 assert(hc);
389 assert(cmd);
390
391 xhci_trb_clean(&cmd->trb);
392
393 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
394 TRB_SET_EP(cmd->trb, ep_id);
395 TRB_SET_SUSP(cmd->trb, susp);
396 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
397
398 return enqueue_command(hc, cmd, 0, 0);
399}
400
401int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
402 uintptr_t dequeue_ptr, uint16_t stream_id,
403 uint32_t ep_id)
404{
405 assert(hc);
406 assert(cmd);
407
408 xhci_trb_clean(&cmd->trb);
409
410 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
411 TRB_SET_EP(cmd->trb, ep_id);
412 TRB_SET_STREAM(cmd->trb, stream_id);
413 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
414 TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
415
416 /**
417 * TODO: Set DCS (see section 4.6.10).
418 */
419
420 return enqueue_command(hc, cmd, 0, 0);
421}
422
423int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
424{
425 assert(hc);
426 assert(cmd);
427
428 xhci_trb_clean(&cmd->trb);
429
430 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
431 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
432
433 return enqueue_command(hc, cmd, 0, 0);
434}
435
436int xhci_get_port_bandwidth_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
437 xhci_port_bandwidth_ctx_t *ctx, uint8_t device_speed)
438{
439 assert(hc);
440 assert(cmd);
441
442 xhci_trb_clean(&cmd->trb);
443
444 uint64_t phys_addr = (uint64_t) addr_to_phys(ctx);
445 TRB_SET_ICTX(cmd->trb, phys_addr);
446
447 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
448 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
449 TRB_SET_DEV_SPEED(cmd->trb, device_speed);
450
451 return enqueue_command(hc, cmd, 0, 0);
452}
453
454int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
455{
456 // TODO: Update dequeue ptrs.
457 assert(hc);
458 assert(trb);
459
460 usb_log_debug2("HC(%p) Command completed.", hc);
461
462 int code;
463 uint64_t phys;
464 xhci_cmd_t *command;
465
466 code = TRB_GET_CODE(*trb);
467 phys = TRB_GET_PHYS(*trb);;
468 command = get_command(hc, phys);
469 if (command == NULL) {
470 // TODO: STOP & ABORT may not have command structs in the list!
471 usb_log_warning("No command struct for this completion event found.");
472
473 if (code != XHCI_TRBC_SUCCESS)
474 report_error(code);
475
476 return EOK;
477 }
478
479 command->status = code;
480 command->slot_id = TRB_GET_SLOT(*trb);
481
482 usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
483 if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
484 if (code != XHCI_TRBC_SUCCESS) {
485 report_error(code);
486 xhci_dump_trb(&command->trb);
487 }
488 }
489
490 switch (TRB_TYPE(command->trb)) {
491 case XHCI_TRB_TYPE_NO_OP_CMD:
492 assert(code == XHCI_TRBC_TRB_ERROR);
493 break;
494 case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
495 break;
496 case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
497 break;
498 case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
499 break;
500 case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
501 break;
502 case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
503 break;
504 case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
505 break;
506 case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
507 // Note: If the endpoint was in the middle of a transfer, then the xHC
508 // will add a Transfer TRB before the Event TRB, research that and
509 // handle it appropriately!
510 break;
511 case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
512 break;
513 default:
514 usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
515
516 command->completed = true;
517 return ENAK;
518 }
519
520 fibril_mutex_lock(&command->completed_mtx);
521 command->completed = true;
522 fibril_condvar_broadcast(&command->completed_cv);
523 fibril_mutex_unlock(&command->completed_mtx);
524
525 return EOK;
526}
527
528
529/**
530 * @}
531 */
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