source: mainline/uspace/drv/bus/usb/xhci/commands.c@ 81487c4a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 81487c4a was 74b852b, checked in by Jaroslav Jindrak <dzejrou@…>, 8 years ago

Added synchronization to command list.
  • Property mode set to 100644
File size: 13.6 KB
Line 
1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "commands.h"
41#include "debug.h"
42#include "hc.h"
43#include "hw_struct/context.h"
44#include "hw_struct/trb.h"
45
46#define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
47#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
48#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
49#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
50#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
51#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
52#define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
53
54/**
55 * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
56 */
57#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
58#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
59
60#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
61#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
62#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
63
64int xhci_init_commands(xhci_hc_t *hc)
65{
66 assert(hc);
67
68 list_initialize(&hc->commands);
69
70 fibril_mutex_initialize(&hc->commands_mtx);
71
72 return EOK;
73}
74
75void xhci_fini_commands(xhci_hc_t *hc)
76{
77 // Note: Untested.
78 assert(hc);
79}
80
81int xhci_cmd_wait(xhci_cmd_t *cmd, suseconds_t timeout)
82{
83 int rv = EOK;
84
85 fibril_mutex_lock(&cmd->completed_mtx);
86 while (!cmd->completed) {
87 usb_log_debug2("Waiting for event completion: going to sleep.");
88 rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
89
90 usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
91 if (rv == ETIMEOUT)
92 break;
93 }
94 fibril_mutex_unlock(&cmd->completed_mtx);
95
96 return rv;
97}
98
99xhci_cmd_t *xhci_cmd_alloc(void)
100{
101 xhci_cmd_t *cmd = malloc(sizeof(xhci_cmd_t));
102 xhci_cmd_init(cmd);
103
104 usb_log_debug2("Allocating cmd on the heap. Don't forget to deallocate it!");
105 return cmd;
106}
107
108void xhci_cmd_init(xhci_cmd_t *cmd)
109{
110 memset(cmd, 0, sizeof(*cmd));
111
112 link_initialize(&cmd->link);
113
114 fibril_mutex_initialize(&cmd->completed_mtx);
115 fibril_condvar_initialize(&cmd->completed_cv);
116}
117
118void xhci_cmd_fini(xhci_cmd_t *cmd)
119{
120 list_remove(&cmd->link);
121}
122
123void xhci_cmd_free(xhci_cmd_t *cmd)
124{
125 xhci_cmd_fini(cmd);
126 free(cmd);
127}
128
129static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
130{
131 fibril_mutex_lock(&hc->commands_mtx);
132
133 link_t *cmd_link = list_first(&hc->commands);
134
135 while (cmd_link != NULL) {
136 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
137
138 if (cmd->trb_phys == phys)
139 break;
140
141 cmd_link = list_next(cmd_link, &hc->commands);
142 }
143
144 if (cmd_link != NULL) {
145 list_remove(cmd_link);
146 fibril_mutex_unlock(&hc->commands_mtx);
147
148 return list_get_instance(cmd_link, xhci_cmd_t, link);
149 }
150
151 fibril_mutex_unlock(&hc->commands_mtx);
152 return NULL;
153}
154
155static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
156{
157 assert(hc);
158 assert(cmd);
159
160 fibril_mutex_lock(&hc->commands_mtx);
161 list_append(&cmd->link, &hc->commands);
162 fibril_mutex_unlock(&hc->commands_mtx);
163
164 xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
165 hc_ring_doorbell(hc, doorbell, target);
166
167 usb_log_debug2("HC(%p): Sent command:", hc);
168 xhci_dump_trb(&cmd->trb);
169
170 return EOK;
171}
172
173void xhci_stop_command_ring(xhci_hc_t *hc)
174{
175 assert(hc);
176
177 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
178
179 /**
180 * Note: There is a bug in qemu that checks CS only when CRCR_HI
181 * is written, this (and the read/write in abort) ensures
182 * the command rings stops.
183 */
184 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
185}
186
187void xhci_abort_command_ring(xhci_hc_t *hc)
188{
189 assert(hc);
190
191 XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
192 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
193}
194
195void xhci_start_command_ring(xhci_hc_t *hc)
196{
197 assert(hc);
198
199 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
200 hc_ring_doorbell(hc, 0, 0);
201}
202
203static const char *trb_codes [] = {
204#define TRBC(t) [XHCI_TRBC_##t] = #t
205 TRBC(INVALID),
206 TRBC(SUCCESS),
207 TRBC(DATA_BUFFER_ERROR),
208 TRBC(BABBLE_DETECTED_ERROR),
209 TRBC(USB_TRANSACTION_ERROR),
210 TRBC(TRB_ERROR),
211 TRBC(STALL_ERROR),
212 TRBC(RESOURCE_ERROR),
213 TRBC(BANDWIDTH_ERROR),
214 TRBC(NO_SLOTS_ERROR),
215 TRBC(INVALID_STREAM_ERROR),
216 TRBC(SLOT_NOT_ENABLED_ERROR),
217 TRBC(EP_NOT_ENABLED_ERROR),
218 TRBC(SHORT_PACKET),
219 TRBC(RING_UNDERRUN),
220 TRBC(RING_OVERRUN),
221 TRBC(VF_EVENT_RING_FULL),
222 TRBC(PARAMETER_ERROR),
223 TRBC(BANDWIDTH_OVERRUN_ERROR),
224 TRBC(CONTEXT_STATE_ERROR),
225 TRBC(NO_PING_RESPONSE_ERROR),
226 TRBC(EVENT_RING_FULL_ERROR),
227 TRBC(INCOMPATIBLE_DEVICE_ERROR),
228 TRBC(MISSED_SERVICE_ERROR),
229 TRBC(COMMAND_RING_STOPPED),
230 TRBC(COMMAND_ABORTED),
231 TRBC(STOPPED),
232 TRBC(STOPPED_LENGTH_INVALID),
233 TRBC(STOPPED_SHORT_PACKET),
234 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
235 [30] = "<reserved>",
236 TRBC(ISOCH_BUFFER_OVERRUN),
237 TRBC(EVENT_LOST_ERROR),
238 TRBC(UNDEFINED_ERROR),
239 TRBC(INVALID_STREAM_ID_ERROR),
240 TRBC(SECONDARY_BANDWIDTH_ERROR),
241 TRBC(SPLIT_TRANSACTION_ERROR),
242 [XHCI_TRBC_MAX] = NULL
243#undef TRBC
244};
245
246static void report_error(int code)
247{
248 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
249 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
250 else
251 usb_log_error("Command resulted in reserved or vendor specific error.");
252}
253
254int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
255{
256 assert(hc);
257
258 xhci_trb_clean(&cmd->trb);
259
260 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
261
262 return enqueue_command(hc, cmd, 0, 0);
263}
264
265int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
266{
267 assert(hc);
268
269 xhci_trb_clean(&cmd->trb);
270
271 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
272 cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
273
274 return enqueue_command(hc, cmd, 0, 0);
275}
276
277int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
278{
279 assert(hc);
280 assert(cmd);
281
282 xhci_trb_clean(&cmd->trb);
283
284 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
285 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
286
287 return enqueue_command(hc, cmd, 0, 0);
288}
289
290int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
291{
292 assert(hc);
293 assert(cmd);
294 assert(ictx);
295
296 /**
297 * TODO: Requirements for this command:
298 * dcbaa[slot_id] is properly sized and initialized
299 * ictx has valids slot context and endpoint 0, all
300 * other should be ignored at this point (see section 4.6.5).
301 */
302
303 xhci_trb_clean(&cmd->trb);
304
305 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
306 TRB_SET_ICTX(cmd->trb, phys_addr);
307
308 /**
309 * Note: According to section 6.4.3.4, we can set the 9th bit
310 * of the control field of the trb (BSR) to 1 and then the xHC
311 * will not issue the SET_ADDRESS request to the USB device.
312 * This can be used to provide compatibility with legacy USB devices
313 * that require their device descriptor to be read before such request.
314 */
315 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
316 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
317
318 return enqueue_command(hc, cmd, 0, 0);
319}
320
321int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
322{
323 assert(hc);
324 assert(cmd);
325 assert(ictx);
326
327 xhci_trb_clean(&cmd->trb);
328
329 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
330 TRB_SET_ICTX(cmd->trb, phys_addr);
331
332 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
333 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
334
335 return enqueue_command(hc, cmd, 0, 0);
336}
337
338int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
339{
340 assert(hc);
341 assert(cmd);
342 assert(ictx);
343
344 /**
345 * Note: All Drop Context flags of the input context shall be 0,
346 * all Add Context flags shall be initialize to indicate IDs
347 * of the contexts affected by the command.
348 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
349 */
350 xhci_trb_clean(&cmd->trb);
351
352 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
353 TRB_SET_ICTX(cmd->trb, phys_addr);
354
355 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
356 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
357
358 return enqueue_command(hc, cmd, 0, 0);
359}
360
361int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
362{
363 assert(hc);
364 assert(cmd);
365
366 /**
367 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
368 * information about this flag.
369 */
370 xhci_trb_clean(&cmd->trb);
371
372 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
373 TRB_SET_TCS(cmd->trb, tcs);
374 TRB_SET_EP(cmd->trb, ep_id);
375 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
376
377 return enqueue_command(hc, cmd, 0, 0);
378}
379
380int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
381{
382 assert(hc);
383 assert(cmd);
384
385 xhci_trb_clean(&cmd->trb);
386
387 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
388 TRB_SET_EP(cmd->trb, ep_id);
389 TRB_SET_SUSP(cmd->trb, susp);
390 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
391
392 return enqueue_command(hc, cmd, 0, 0);
393}
394
395int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
396 uintptr_t dequeue_ptr, uint16_t stream_id,
397 uint32_t ep_id)
398{
399 assert(hc);
400 assert(cmd);
401
402 xhci_trb_clean(&cmd->trb);
403
404 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
405 TRB_SET_EP(cmd->trb, ep_id);
406 TRB_SET_STREAM(cmd->trb, stream_id);
407 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
408 TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
409
410 /**
411 * TODO: Set DCS (see section 4.6.10).
412 */
413
414 return enqueue_command(hc, cmd, 0, 0);
415}
416
417int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
418{
419 assert(hc);
420 assert(cmd);
421
422 xhci_trb_clean(&cmd->trb);
423
424 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
425 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
426
427 return enqueue_command(hc, cmd, 0, 0);
428}
429
430int xhci_get_port_bandwidth_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
431 xhci_port_bandwidth_ctx_t *ctx, uint8_t device_speed)
432{
433 assert(hc);
434 assert(cmd);
435
436 xhci_trb_clean(&cmd->trb);
437
438 uint64_t phys_addr = (uint64_t) addr_to_phys(ctx);
439 TRB_SET_ICTX(cmd->trb, phys_addr);
440
441 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
442 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
443 TRB_SET_DEV_SPEED(cmd->trb, device_speed);
444
445 return enqueue_command(hc, cmd, 0, 0);
446}
447
448int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
449{
450 // TODO: Update dequeue ptrs.
451 assert(hc);
452 assert(trb);
453
454 usb_log_debug2("HC(%p) Command completed.", hc);
455
456 int code;
457 uint64_t phys;
458 xhci_cmd_t *command;
459
460 code = TRB_GET_CODE(*trb);
461 phys = TRB_GET_PHYS(*trb);;
462 command = get_command(hc, phys);
463 if (command == NULL) {
464 // TODO: STOP & ABORT may not have command structs in the list!
465 usb_log_warning("No command struct for this completion event found.");
466
467 if (code != XHCI_TRBC_SUCCESS)
468 report_error(code);
469
470 return EOK;
471 }
472
473 command->status = code;
474 command->slot_id = TRB_GET_SLOT(*trb);
475
476 usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
477 if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
478 if (code != XHCI_TRBC_SUCCESS) {
479 report_error(code);
480 xhci_dump_trb(&command->trb);
481 }
482 }
483
484 switch (TRB_TYPE(command->trb)) {
485 case XHCI_TRB_TYPE_NO_OP_CMD:
486 assert(code == XHCI_TRBC_TRB_ERROR);
487 break;
488 case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
489 break;
490 case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
491 break;
492 case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
493 break;
494 case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
495 break;
496 case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
497 break;
498 case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
499 break;
500 case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
501 // Note: If the endpoint was in the middle of a transfer, then the xHC
502 // will add a Transfer TRB before the Event TRB, research that and
503 // handle it appropriately!
504 break;
505 case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
506 break;
507 default:
508 usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
509
510 command->completed = true;
511 return ENAK;
512 }
513
514 fibril_mutex_lock(&command->completed_mtx);
515 command->completed = true;
516 fibril_condvar_broadcast(&command->completed_cv);
517 fibril_mutex_unlock(&command->completed_mtx);
518
519 return EOK;
520}
521
522
523/**
524 * @}
525 */
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