source: mainline/uspace/drv/bus/usb/xhci/commands.c@ d14ca59

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d14ca59 was 472235a, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci: refactoring

Revise error paths, refactor some code.
  • Property mode set to 100644
File size: 13.0 KB
Line 
1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "commands.h"
41#include "debug.h"
42#include "hc.h"
43#include "hw_struct/context.h"
44#include "hw_struct/trb.h"
45
46#define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
47#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
48#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
49#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
50#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
51#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
52
53/**
54 * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
55 */
56#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
57#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
58
59#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
60#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
61#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
62
63int xhci_init_commands(xhci_hc_t *hc)
64{
65 assert(hc);
66
67 list_initialize(&hc->commands);
68 return EOK;
69}
70
71void xhci_fini_commands(xhci_hc_t *hc)
72{
73 // Note: Untested.
74 assert(hc);
75}
76
77int xhci_cmd_wait(xhci_cmd_t *cmd, suseconds_t timeout)
78{
79 int rv = EOK;
80
81 fibril_mutex_lock(&cmd->completed_mtx);
82 while (!cmd->completed) {
83 usb_log_debug2("Waiting for event completion: going to sleep.");
84 rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
85
86 usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
87 if (rv == ETIMEOUT)
88 break;
89 }
90 fibril_mutex_unlock(&cmd->completed_mtx);
91
92 return rv;
93}
94
95xhci_cmd_t *xhci_cmd_alloc(void)
96{
97 xhci_cmd_t *cmd = malloc32(sizeof(xhci_cmd_t));
98 xhci_cmd_init(cmd);
99
100 usb_log_debug2("Allocating cmd on the heap. Don't forget to deallocate it!");
101 return cmd;
102}
103
104void xhci_cmd_init(xhci_cmd_t *cmd)
105{
106 memset(cmd, 0, sizeof(*cmd));
107
108 link_initialize(&cmd->link);
109
110 fibril_mutex_initialize(&cmd->completed_mtx);
111 fibril_condvar_initialize(&cmd->completed_cv);
112}
113
114void xhci_cmd_fini(xhci_cmd_t *cmd)
115{
116 list_remove(&cmd->link);
117}
118
119void xhci_cmd_free(xhci_cmd_t *cmd)
120{
121 xhci_cmd_fini(cmd);
122 free32(cmd);
123}
124
125static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
126{
127 link_t *cmd_link = list_first(&hc->commands);
128
129 while (cmd_link != NULL) {
130 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
131
132 if (cmd->trb_phys == phys)
133 break;
134
135 cmd_link = list_next(cmd_link, &hc->commands);
136 }
137
138 if (cmd_link != NULL) {
139 list_remove(cmd_link);
140
141 return list_get_instance(cmd_link, xhci_cmd_t, link);
142 }
143
144 return NULL;
145}
146
147static inline int ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
148{
149 assert(hc);
150 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
151 pio_write_32(&hc->db_arry[doorbell], v);
152 return EOK;
153}
154
155static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
156{
157 assert(hc);
158 assert(cmd);
159
160 list_append(&cmd->link, &hc->commands);
161
162 xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
163 ring_doorbell(hc, doorbell, target);
164
165 usb_log_debug2("HC(%p): Sent command:", hc);
166 xhci_dump_trb(&cmd->trb);
167
168 return EOK;
169}
170
171void xhci_stop_command_ring(xhci_hc_t *hc)
172{
173 assert(hc);
174
175 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
176
177 /**
178 * Note: There is a bug in qemu that checks CS only when CRCR_HI
179 * is written, this (and the read/write in abort) ensures
180 * the command rings stops.
181 */
182 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
183}
184
185void xhci_abort_command_ring(xhci_hc_t *hc)
186{
187 assert(hc);
188
189 XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
190 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
191}
192
193void xhci_start_command_ring(xhci_hc_t *hc)
194{
195 assert(hc);
196
197 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
198 ring_doorbell(hc, 0, 0);
199}
200
201static const char *trb_codes [] = {
202#define TRBC(t) [XHCI_TRBC_##t] = #t
203 TRBC(INVALID),
204 TRBC(SUCCESS),
205 TRBC(DATA_BUFFER_ERROR),
206 TRBC(BABBLE_DETECTED_ERROR),
207 TRBC(USB_TRANSACTION_ERROR),
208 TRBC(TRB_ERROR),
209 TRBC(STALL_ERROR),
210 TRBC(RESOURCE_ERROR),
211 TRBC(BANDWIDTH_ERROR),
212 TRBC(NO_SLOTS_ERROR),
213 TRBC(INVALID_STREAM_ERROR),
214 TRBC(SLOT_NOT_ENABLED_ERROR),
215 TRBC(EP_NOT_ENABLED_ERROR),
216 TRBC(SHORT_PACKET),
217 TRBC(RING_UNDERRUN),
218 TRBC(RING_OVERRUN),
219 TRBC(VF_EVENT_RING_FULL),
220 TRBC(PARAMETER_ERROR),
221 TRBC(BANDWIDTH_OVERRUN_ERROR),
222 TRBC(CONTEXT_STATE_ERROR),
223 TRBC(NO_PING_RESPONSE_ERROR),
224 TRBC(EVENT_RING_FULL_ERROR),
225 TRBC(INCOMPATIBLE_DEVICE_ERROR),
226 TRBC(MISSED_SERVICE_ERROR),
227 TRBC(COMMAND_RING_STOPPED),
228 TRBC(COMMAND_ABORTED),
229 TRBC(STOPPED),
230 TRBC(STOPPED_LENGTH_INVALID),
231 TRBC(STOPPED_SHORT_PACKET),
232 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
233 [30] = "<reserved>",
234 TRBC(ISOCH_BUFFER_OVERRUN),
235 TRBC(EVENT_LOST_ERROR),
236 TRBC(UNDEFINED_ERROR),
237 TRBC(INVALID_STREAM_ID_ERROR),
238 TRBC(SECONDARY_BANDWIDTH_ERROR),
239 TRBC(SPLIT_TRANSACTION_ERROR),
240 [XHCI_TRBC_MAX] = NULL
241#undef TRBC
242};
243
244static void report_error(int code)
245{
246 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
247 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
248 else
249 usb_log_error("Command resulted in reserved or vendor specific error.");
250}
251
252int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
253{
254 assert(hc);
255
256 xhci_trb_clean(&cmd->trb);
257
258 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
259
260 return enqueue_command(hc, cmd, 0, 0);
261}
262
263int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
264{
265 assert(hc);
266
267 xhci_trb_clean(&cmd->trb);
268
269 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
270 cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
271
272 return enqueue_command(hc, cmd, 0, 0);
273}
274
275int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
276{
277 assert(hc);
278 assert(cmd);
279
280 xhci_trb_clean(&cmd->trb);
281
282 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
283 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
284
285 return enqueue_command(hc, cmd, 0, 0);
286}
287
288int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
289{
290 assert(hc);
291 assert(cmd);
292 assert(ictx);
293
294 /**
295 * TODO: Requirements for this command:
296 * dcbaa[slot_id] is properly sized and initialized
297 * ictx has valids slot context and endpoint 0, all
298 * other should be ignored at this point (see section 4.6.5).
299 */
300
301 xhci_trb_clean(&cmd->trb);
302
303 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
304 TRB_SET_ICTX(cmd->trb, phys_addr);
305
306 /**
307 * Note: According to section 6.4.3.4, we can set the 9th bit
308 * of the control field of the trb (BSR) to 1 and then the xHC
309 * will not issue the SET_ADDRESS request to the USB device.
310 * This can be used to provide compatibility with legacy USB devices
311 * that require their device descriptor to be read before such request.
312 */
313 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
314 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
315
316 return enqueue_command(hc, cmd, 0, 0);
317}
318
319int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
320{
321 assert(hc);
322 assert(cmd);
323 assert(ictx);
324
325 xhci_trb_clean(&cmd->trb);
326
327 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
328 TRB_SET_ICTX(cmd->trb, phys_addr);
329
330 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
331 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
332
333 return enqueue_command(hc, cmd, 0, 0);
334}
335
336int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
337{
338 assert(hc);
339 assert(cmd);
340 assert(ictx);
341
342 /**
343 * Note: All Drop Context flags of the input context shall be 0,
344 * all Add Context flags shall be initialize to indicate IDs
345 * of the contexts affected by the command.
346 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
347 */
348 xhci_trb_clean(&cmd->trb);
349
350 uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
351 TRB_SET_ICTX(cmd->trb, phys_addr);
352
353 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
354 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
355
356 return enqueue_command(hc, cmd, 0, 0);
357}
358
359int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
360{
361 assert(hc);
362 assert(cmd);
363
364 /**
365 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
366 * information about this flag.
367 */
368 xhci_trb_clean(&cmd->trb);
369
370 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
371 TRB_SET_TCS(cmd->trb, tcs);
372 TRB_SET_EP(cmd->trb, ep_id);
373 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
374
375 return enqueue_command(hc, cmd, 0, 0);
376}
377
378int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
379{
380 assert(hc);
381 assert(cmd);
382
383 xhci_trb_clean(&cmd->trb);
384
385 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
386 TRB_SET_EP(cmd->trb, ep_id);
387 TRB_SET_SUSP(cmd->trb, susp);
388 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
389
390 return enqueue_command(hc, cmd, 0, 0);
391}
392
393int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
394 uintptr_t dequeue_ptr, uint16_t stream_id,
395 uint32_t ep_id)
396{
397 assert(hc);
398 assert(cmd);
399
400 xhci_trb_clean(&cmd->trb);
401
402 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
403 TRB_SET_EP(cmd->trb, ep_id);
404 TRB_SET_STREAM(cmd->trb, stream_id);
405 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
406 TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
407
408 /**
409 * TODO: Set DCS (see section 4.6.10).
410 */
411
412 return enqueue_command(hc, cmd, 0, 0);
413}
414
415int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
416{
417 assert(hc);
418 assert(cmd);
419
420 xhci_trb_clean(&cmd->trb);
421
422 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
423 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
424
425 return enqueue_command(hc, cmd, 0, 0);
426}
427
428int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
429{
430 // TODO: Update dequeue ptrs.
431 assert(hc);
432 assert(trb);
433
434 usb_log_debug("HC(%p) Command completed.", hc);
435
436 int code;
437 uint64_t phys;
438 xhci_cmd_t *command;
439
440 code = TRB_GET_CODE(*trb);
441 phys = TRB_GET_PHYS(*trb);;
442 command = get_command(hc, phys);
443 if (command == NULL) {
444 // TODO: STOP & ABORT may not have command structs in the list!
445 usb_log_debug("No command struct for this completion event found.");
446
447 if (code != XHCI_TRBC_SUCCESS)
448 report_error(code);
449
450 return EOK;
451 }
452
453 command->status = code;
454 command->slot_id = TRB_GET_SLOT(*trb);
455
456 usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
457 if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
458 if (code != XHCI_TRBC_SUCCESS) {
459 report_error(code);
460 xhci_dump_trb(&command->trb);
461 }
462 }
463
464 switch (TRB_TYPE(command->trb)) {
465 case XHCI_TRB_TYPE_NO_OP_CMD:
466 assert(code == XHCI_TRBC_TRB_ERROR);
467 break;
468 case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
469 break;
470 case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
471 break;
472 case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
473 break;
474 case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
475 break;
476 case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
477 break;
478 case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
479 break;
480 case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
481 // Note: If the endpoint was in the middle of a transfer, then the xHC
482 // will add a Transfer TRB before the Event TRB, research that and
483 // handle it appropriately!
484 break;
485 case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
486 break;
487 default:
488 usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
489
490 command->completed = true;
491 return ENAK;
492 }
493
494 fibril_mutex_lock(&command->completed_mtx);
495 command->completed = true;
496 fibril_condvar_broadcast(&command->completed_cv);
497 fibril_mutex_unlock(&command->completed_mtx);
498
499 return EOK;
500}
501
502
503/**
504 * @}
505 */
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