source: mainline/uspace/drv/bus/usb/xhci/commands.c@ 5ef3afd

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5ef3afd was 1d758fc, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

usb: rethinking DMA buffers
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File size: 22.1 KB
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1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include "commands.h"
40#include "debug.h"
41#include "hc.h"
42#include "hw_struct/context.h"
43#include "hw_struct/trb.h"
44
45#define TRB_SET_TSP(trb, tsp) (trb).control |= host2xhci(32, (((tsp) & 0x1) << 9))
46#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
47#define TRB_SET_DC(trb, dc) (trb).control |= host2xhci(32, (dc) << 9)
48#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
49#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
50#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
51#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
52#define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
53#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
54#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, (phys) & (~0xF))
55
56#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
57#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
58#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
59
60/* Control functions */
61
62static xhci_cmd_ring_t *get_cmd_ring(xhci_hc_t *hc)
63{
64 assert(hc);
65 return &hc->cr;
66}
67
68/**
69 * Initialize the command subsystem. Allocates the comand ring.
70 *
71 * Does not configure the CR pointer to the hardware, because the xHC will be
72 * reset before starting.
73 */
74errno_t xhci_init_commands(xhci_hc_t *hc)
75{
76 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
77 errno_t err;
78
79 if ((err = xhci_trb_ring_init(&cr->trb_ring, 0)))
80 return err;
81
82 fibril_mutex_initialize(&cr->guard);
83 fibril_condvar_initialize(&cr->state_cv);
84 fibril_condvar_initialize(&cr->stopped_cv);
85
86 list_initialize(&cr->cmd_list);
87
88 return EOK;
89}
90
91/**
92 * Finish the command subsystem. Stops the hardware from running commands, then
93 * deallocates the ring.
94 */
95void xhci_fini_commands(xhci_hc_t *hc)
96{
97 assert(hc);
98 xhci_stop_command_ring(hc);
99
100 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
101
102 fibril_mutex_lock(&cr->guard);
103 xhci_trb_ring_fini(&cr->trb_ring);
104 fibril_mutex_unlock(&cr->guard);
105}
106
107/**
108 * Initialize a command structure for the given command.
109 */
110void xhci_cmd_init(xhci_cmd_t *cmd, xhci_cmd_type_t type)
111{
112 memset(cmd, 0, sizeof(*cmd));
113
114 link_initialize(&cmd->_header.link);
115
116 fibril_mutex_initialize(&cmd->_header.completed_mtx);
117 fibril_condvar_initialize(&cmd->_header.completed_cv);
118
119 cmd->_header.cmd = type;
120}
121
122/**
123 * Finish the command structure. Some command invocation includes allocating
124 * a context structure. To have the convenience in calling commands, this
125 * method deallocates all resources.
126 */
127void xhci_cmd_fini(xhci_cmd_t *cmd)
128{
129 list_remove(&cmd->_header.link);
130
131 dma_buffer_free(&cmd->input_ctx);
132 dma_buffer_free(&cmd->bandwidth_ctx);
133
134 if (cmd->_header.async) {
135 free(cmd);
136 }
137}
138
139/**
140 * Find a command issued by TRB at @c phys inside the command list.
141 *
142 * Call with guard locked only.
143 */
144static inline xhci_cmd_t *find_command(xhci_hc_t *hc, uint64_t phys)
145{
146 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
147 assert(fibril_mutex_is_locked(&cr->guard));
148
149 link_t *cmd_link = list_first(&cr->cmd_list);
150
151 while (cmd_link != NULL) {
152 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, _header.link);
153
154 if (cmd->_header.trb_phys == phys)
155 break;
156
157 cmd_link = list_next(cmd_link, &cr->cmd_list);
158 }
159
160 return cmd_link ? list_get_instance(cmd_link, xhci_cmd_t, _header.link)
161 : NULL;
162}
163
164static void cr_set_state(xhci_cmd_ring_t *cr, xhci_cr_state_t state)
165{
166 assert(fibril_mutex_is_locked(&cr->guard));
167
168 cr->state = state;
169 if (state == XHCI_CR_STATE_OPEN
170 || state == XHCI_CR_STATE_CLOSED)
171 fibril_condvar_broadcast(&cr->state_cv);
172}
173
174static errno_t wait_for_ring_open(xhci_cmd_ring_t *cr)
175{
176 assert(fibril_mutex_is_locked(&cr->guard));
177
178 while (true) {
179 switch (cr->state) {
180 case XHCI_CR_STATE_CHANGING:
181 case XHCI_CR_STATE_FULL:
182 fibril_condvar_wait(&cr->state_cv, &cr->guard);
183 break;
184 case XHCI_CR_STATE_OPEN:
185 return EOK;
186 case XHCI_CR_STATE_CLOSED:
187 return ENAK;
188 }
189 }
190}
191
192/**
193 * Enqueue a command on the TRB ring. Ring the doorbell to initiate processing.
194 * Register the command as waiting for completion inside the command list.
195 */
196static inline errno_t enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
197{
198 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
199 assert(cmd);
200
201 fibril_mutex_lock(&cr->guard);
202
203 if (wait_for_ring_open(cr)) {
204 fibril_mutex_unlock(&cr->guard);
205 return ENAK;
206 }
207
208 usb_log_debug("Sending command %s", xhci_trb_str_type(TRB_TYPE(cmd->_header.trb)));
209
210 list_append(&cmd->_header.link, &cr->cmd_list);
211
212 errno_t err = EOK;
213 while (err == EOK) {
214 err = xhci_trb_ring_enqueue(&cr->trb_ring,
215 &cmd->_header.trb, &cmd->_header.trb_phys);
216 if (err != EAGAIN)
217 break;
218
219 cr_set_state(cr, XHCI_CR_STATE_FULL);
220 err = wait_for_ring_open(cr);
221 }
222
223 if (err == EOK)
224 hc_ring_doorbell(hc, 0, 0);
225
226 fibril_mutex_unlock(&cr->guard);
227
228 return err;
229}
230
231/**
232 * Stop the command ring. Stop processing commands, block issuing new ones.
233 * Wait until hardware acknowledges it is stopped.
234 */
235void xhci_stop_command_ring(xhci_hc_t *hc)
236{
237 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
238
239 fibril_mutex_lock(&cr->guard);
240
241 // Prevent others from starting CR again.
242 cr_set_state(cr, XHCI_CR_STATE_CLOSED);
243
244 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
245
246 while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR))
247 fibril_condvar_wait(&cr->stopped_cv, &cr->guard);
248
249 fibril_mutex_unlock(&cr->guard);
250}
251
252/**
253 * Mark the command ring as stopped. NAK new commands, abort running, do not
254 * touch the HC as it's probably broken.
255 */
256void xhci_nuke_command_ring(xhci_hc_t *hc)
257{
258 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
259 fibril_mutex_lock(&cr->guard);
260 // Prevent others from starting CR again.
261 cr_set_state(cr, XHCI_CR_STATE_CLOSED);
262
263 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
264 fibril_mutex_unlock(&cr->guard);
265}
266
267/**
268 * Mark the command ring as working again.
269 */
270void xhci_start_command_ring(xhci_hc_t *hc)
271{
272 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
273 fibril_mutex_lock(&cr->guard);
274 // Prevent others from starting CR again.
275 cr_set_state(cr, XHCI_CR_STATE_OPEN);
276 fibril_mutex_unlock(&cr->guard);
277}
278
279/**
280 * Abort currently processed command. Note that it is only aborted when the
281 * command is "blocking" - see section 4.6.1.2 of xHCI spec.
282 */
283static void abort_command_ring(xhci_hc_t *hc)
284{
285 XHCI_REG_SET(hc->op_regs, XHCI_OP_CA, 1);
286}
287
288static const char *trb_codes [] = {
289#define TRBC(t) [XHCI_TRBC_##t] = #t
290 TRBC(INVALID),
291 TRBC(SUCCESS),
292 TRBC(DATA_BUFFER_ERROR),
293 TRBC(BABBLE_DETECTED_ERROR),
294 TRBC(USB_TRANSACTION_ERROR),
295 TRBC(TRB_ERROR),
296 TRBC(STALL_ERROR),
297 TRBC(RESOURCE_ERROR),
298 TRBC(BANDWIDTH_ERROR),
299 TRBC(NO_SLOTS_ERROR),
300 TRBC(INVALID_STREAM_ERROR),
301 TRBC(SLOT_NOT_ENABLED_ERROR),
302 TRBC(EP_NOT_ENABLED_ERROR),
303 TRBC(SHORT_PACKET),
304 TRBC(RING_UNDERRUN),
305 TRBC(RING_OVERRUN),
306 TRBC(VF_EVENT_RING_FULL),
307 TRBC(PARAMETER_ERROR),
308 TRBC(BANDWIDTH_OVERRUN_ERROR),
309 TRBC(CONTEXT_STATE_ERROR),
310 TRBC(NO_PING_RESPONSE_ERROR),
311 TRBC(EVENT_RING_FULL_ERROR),
312 TRBC(INCOMPATIBLE_DEVICE_ERROR),
313 TRBC(MISSED_SERVICE_ERROR),
314 TRBC(COMMAND_RING_STOPPED),
315 TRBC(COMMAND_ABORTED),
316 TRBC(STOPPED),
317 TRBC(STOPPED_LENGTH_INVALID),
318 TRBC(STOPPED_SHORT_PACKET),
319 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
320 [30] = "<reserved>",
321 TRBC(ISOCH_BUFFER_OVERRUN),
322 TRBC(EVENT_LOST_ERROR),
323 TRBC(UNDEFINED_ERROR),
324 TRBC(INVALID_STREAM_ID_ERROR),
325 TRBC(SECONDARY_BANDWIDTH_ERROR),
326 TRBC(SPLIT_TRANSACTION_ERROR),
327 [XHCI_TRBC_MAX] = NULL
328#undef TRBC
329};
330
331/**
332 * Report an error according to command completion code.
333 */
334static void report_error(int code)
335{
336 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
337 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
338 else
339 usb_log_error("Command resulted in reserved or vendor specific error.");
340}
341
342/**
343 * Handle a command completion. Feed the fibril waiting for result.
344 *
345 * @param trb The COMMAND_COMPLETION TRB found in event ring.
346 */
347errno_t xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
348{
349 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
350 assert(trb);
351
352 fibril_mutex_lock(&cr->guard);
353
354 int code = TRB_GET_CODE(*trb);
355
356 if (code == XHCI_TRBC_COMMAND_RING_STOPPED) {
357 /* This can either mean that the ring is being stopped, or
358 * a command was aborted. In either way, wake threads waiting
359 * on stopped_cv.
360 *
361 * Note that we need to hold mutex, because we must be sure the
362 * requesting thread is waiting inside the CV.
363 */
364 usb_log_debug("Command ring stopped.");
365 fibril_condvar_broadcast(&cr->stopped_cv);
366 fibril_mutex_unlock(&cr->guard);
367 return EOK;
368 }
369
370 const uint64_t phys = TRB_GET_PHYS(*trb);
371 xhci_trb_ring_update_dequeue(&cr->trb_ring, phys);
372
373 if (cr->state == XHCI_CR_STATE_FULL)
374 cr_set_state(cr, XHCI_CR_STATE_OPEN);
375
376 xhci_cmd_t *command = find_command(hc, phys);
377 if (command == NULL) {
378 usb_log_error("No command struct for completion event found.");
379
380 if (code != XHCI_TRBC_SUCCESS)
381 report_error(code);
382
383 return EOK;
384 }
385
386 list_remove(&command->_header.link);
387
388 /* Semantics of NO_OP_CMD is that success is marked as a TRB error. */
389 if (command->_header.cmd == XHCI_CMD_NO_OP && code == XHCI_TRBC_TRB_ERROR)
390 code = XHCI_TRBC_SUCCESS;
391
392 command->status = code;
393 command->slot_id = TRB_GET_SLOT(*trb);
394
395 usb_log_debug("Completed command %s",
396 xhci_trb_str_type(TRB_TYPE(command->_header.trb)));
397
398 if (code != XHCI_TRBC_SUCCESS) {
399 report_error(code);
400 xhci_dump_trb(&command->_header.trb);
401 }
402
403 fibril_mutex_unlock(&cr->guard);
404
405 fibril_mutex_lock(&command->_header.completed_mtx);
406 command->_header.completed = true;
407 fibril_condvar_broadcast(&command->_header.completed_cv);
408 fibril_mutex_unlock(&command->_header.completed_mtx);
409
410 if (command->_header.async) {
411 /* Free the command and other DS upon completion. */
412 xhci_cmd_fini(command);
413 }
414
415 return EOK;
416}
417
418/* Command-issuing functions */
419
420static errno_t no_op_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
421{
422 assert(hc);
423
424 xhci_trb_clean(&cmd->_header.trb);
425
426 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_NO_OP_CMD);
427
428 return enqueue_command(hc, cmd);
429}
430
431static errno_t enable_slot_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
432{
433 assert(hc);
434
435 xhci_trb_clean(&cmd->_header.trb);
436
437 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
438 cmd->_header.trb.control |=
439 host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
440
441 return enqueue_command(hc, cmd);
442}
443
444static errno_t disable_slot_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
445{
446 assert(hc);
447 assert(cmd);
448
449 xhci_trb_clean(&cmd->_header.trb);
450
451 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
452 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
453
454 return enqueue_command(hc, cmd);
455}
456
457static errno_t address_device_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
458{
459 assert(hc);
460 assert(cmd);
461 assert(dma_buffer_is_set(&cmd->input_ctx));
462
463 /**
464 * TODO: Requirements for this command:
465 * dcbaa[slot_id] is properly sized and initialized
466 * ictx has valids slot context and endpoint 0, all
467 * other should be ignored at this point (see section 4.6.5).
468 */
469
470 xhci_trb_clean(&cmd->_header.trb);
471
472 const uintptr_t phys = dma_buffer_phys_base(&cmd->input_ctx);
473 TRB_SET_ICTX(cmd->_header.trb, phys);
474
475 /**
476 * Note: According to section 6.4.3.4, we can set the 9th bit
477 * of the control field of the trb (BSR) to 1 and then the xHC
478 * will not issue the SET_ADDRESS request to the USB device.
479 * This can be used to provide compatibility with legacy USB devices
480 * that require their device descriptor to be read before such request.
481 */
482 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
483 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
484
485 return enqueue_command(hc, cmd);
486}
487
488static errno_t configure_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
489{
490 assert(hc);
491 assert(cmd);
492
493 xhci_trb_clean(&cmd->_header.trb);
494
495 if (!cmd->deconfigure) {
496 /* If the DC flag is on, input context is not evaluated. */
497 assert(dma_buffer_is_set(&cmd->input_ctx));
498
499 const uintptr_t phys = dma_buffer_phys_base(&cmd->input_ctx);
500 TRB_SET_ICTX(cmd->_header.trb, phys);
501 }
502
503 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
504 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
505 TRB_SET_DC(cmd->_header.trb, cmd->deconfigure);
506
507 return enqueue_command(hc, cmd);
508}
509
510static errno_t evaluate_context_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
511{
512 assert(hc);
513 assert(cmd);
514 assert(dma_buffer_is_set(&cmd->input_ctx));
515
516 /**
517 * Note: All Drop Context flags of the input context shall be 0,
518 * all Add Context flags shall be initialize to indicate IDs
519 * of the contexts affected by the command.
520 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
521 */
522 xhci_trb_clean(&cmd->_header.trb);
523
524 const uintptr_t phys = dma_buffer_phys_base(&cmd->input_ctx);
525 TRB_SET_ICTX(cmd->_header.trb, phys);
526
527 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
528 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
529
530 return enqueue_command(hc, cmd);
531}
532
533static errno_t reset_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
534{
535 assert(hc);
536 assert(cmd);
537
538 xhci_trb_clean(&cmd->_header.trb);
539
540 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
541 TRB_SET_TSP(cmd->_header.trb, cmd->tsp);
542 TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
543 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
544
545 return enqueue_command(hc, cmd);
546}
547
548static errno_t stop_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
549{
550 assert(hc);
551 assert(cmd);
552
553 xhci_trb_clean(&cmd->_header.trb);
554
555 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
556 TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
557 TRB_SET_SUSP(cmd->_header.trb, cmd->susp);
558 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
559
560 return enqueue_command(hc, cmd);
561}
562
563static errno_t set_tr_dequeue_pointer_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
564{
565 assert(hc);
566 assert(cmd);
567
568 xhci_trb_clean(&cmd->_header.trb);
569
570 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
571 TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
572 TRB_SET_STREAM(cmd->_header.trb, cmd->stream_id);
573 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
574 TRB_SET_DEQUEUE_PTR(cmd->_header.trb, cmd->dequeue_ptr);
575
576 return enqueue_command(hc, cmd);
577}
578
579static errno_t reset_device_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
580{
581 assert(hc);
582 assert(cmd);
583
584 xhci_trb_clean(&cmd->_header.trb);
585
586 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
587 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
588
589 return enqueue_command(hc, cmd);
590}
591
592static errno_t get_port_bandwidth_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
593{
594 assert(hc);
595 assert(cmd);
596
597 xhci_trb_clean(&cmd->_header.trb);
598
599 const uintptr_t phys = dma_buffer_phys_base(&cmd->input_ctx);
600 TRB_SET_ICTX(cmd->_header.trb, phys);
601
602 TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
603 TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
604 TRB_SET_DEV_SPEED(cmd->_header.trb, cmd->device_speed);
605
606 return enqueue_command(hc, cmd);
607}
608
609/* The table of command-issuing functions. */
610
611typedef errno_t (*cmd_handler) (xhci_hc_t *hc, xhci_cmd_t *cmd);
612
613static cmd_handler cmd_handlers [] = {
614 [XHCI_CMD_ENABLE_SLOT] = enable_slot_cmd,
615 [XHCI_CMD_DISABLE_SLOT] = disable_slot_cmd,
616 [XHCI_CMD_ADDRESS_DEVICE] = address_device_cmd,
617 [XHCI_CMD_CONFIGURE_ENDPOINT] = configure_endpoint_cmd,
618 [XHCI_CMD_EVALUATE_CONTEXT] = evaluate_context_cmd,
619 [XHCI_CMD_RESET_ENDPOINT] = reset_endpoint_cmd,
620 [XHCI_CMD_STOP_ENDPOINT] = stop_endpoint_cmd,
621 [XHCI_CMD_SET_TR_DEQUEUE_POINTER] = set_tr_dequeue_pointer_cmd,
622 [XHCI_CMD_RESET_DEVICE] = reset_device_cmd,
623 [XHCI_CMD_FORCE_EVENT] = NULL,
624 [XHCI_CMD_NEGOTIATE_BANDWIDTH] = NULL,
625 [XHCI_CMD_SET_LATENCY_TOLERANCE_VALUE] = NULL,
626 [XHCI_CMD_GET_PORT_BANDWIDTH] = get_port_bandwidth_cmd,
627 [XHCI_CMD_FORCE_HEADER] = NULL,
628 [XHCI_CMD_NO_OP] = no_op_cmd
629};
630
631/**
632 * Try to abort currently processed command. This is tricky, because
633 * calling fibril is not necessarily the one which issued the blocked command.
634 * Also, the trickiness intensifies by the fact that stopping a CR is denoted by
635 * event, which is again handled in different fibril. but, once we go to sleep
636 * on waiting for that event, another fibril may wake up and try to abort the
637 * blocked command.
638 *
639 * So, we mark the command ring as being restarted, wait for it to stop, and
640 * then start it again. If there was a blocked command, it will be satisfied by
641 * COMMAND_ABORTED event.
642 */
643static errno_t try_abort_current_command(xhci_hc_t *hc)
644{
645 xhci_cmd_ring_t *cr = get_cmd_ring(hc);
646
647 fibril_mutex_lock(&cr->guard);
648
649 if (cr->state == XHCI_CR_STATE_CLOSED) {
650 fibril_mutex_unlock(&cr->guard);
651 return ENAK;
652 }
653
654 if (cr->state == XHCI_CR_STATE_CHANGING) {
655 fibril_mutex_unlock(&cr->guard);
656 return EOK;
657 }
658
659 usb_log_error("Timeout while waiting for command: aborting current command.");
660
661 cr_set_state(cr, XHCI_CR_STATE_CHANGING);
662
663 abort_command_ring(hc);
664
665 fibril_condvar_wait_timeout(&cr->stopped_cv, &cr->guard, XHCI_CR_ABORT_TIMEOUT);
666
667 if (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR)) {
668 /* 4.6.1.2, implementation note
669 * Assume there are larger problems with HC and
670 * reset it.
671 */
672 usb_log_error("Command didn't abort.");
673
674 cr_set_state(cr, XHCI_CR_STATE_CLOSED);
675
676 // TODO: Reset HC completely.
677 // Don't forget to somehow complete all commands with error.
678
679 fibril_mutex_unlock(&cr->guard);
680 return ENAK;
681 }
682
683 cr_set_state(cr, XHCI_CR_STATE_OPEN);
684
685 fibril_mutex_unlock(&cr->guard);
686
687 usb_log_error("Command ring stopped. Starting again.");
688 hc_ring_doorbell(hc, 0, 0);
689
690 return EOK;
691}
692
693/**
694 * Wait, until the command is completed. The completion is triggered by
695 * COMMAND_COMPLETION event. As we do not want to rely on HW completing the
696 * command in timely manner, we timeout. Note that we can't just return an
697 * error after the timeout pass - it may be other command blocking the ring,
698 * and ours can be completed afterwards. Therefore, it is not guaranteed that
699 * this function will return in XHCI_COMMAND_TIMEOUT. It will continue waiting
700 * until COMMAND_COMPLETION event arrives.
701 */
702static errno_t wait_for_cmd_completion(xhci_hc_t *hc, xhci_cmd_t *cmd)
703{
704 errno_t rv = EOK;
705
706 if (fibril_get_id() == hc->event_handler) {
707 usb_log_error("Deadlock detected in waiting for command.");
708 abort();
709 }
710
711 fibril_mutex_lock(&cmd->_header.completed_mtx);
712 while (!cmd->_header.completed) {
713
714 rv = fibril_condvar_wait_timeout(&cmd->_header.completed_cv,
715 &cmd->_header.completed_mtx, XHCI_COMMAND_TIMEOUT);
716
717 /* The waiting timed out. Current command (not necessarily
718 * ours) is probably blocked.
719 */
720 if (!cmd->_header.completed && rv == ETIMEOUT) {
721 fibril_mutex_unlock(&cmd->_header.completed_mtx);
722
723 rv = try_abort_current_command(hc);
724 if (rv)
725 return rv;
726
727 fibril_mutex_lock(&cmd->_header.completed_mtx);
728 }
729 }
730 fibril_mutex_unlock(&cmd->_header.completed_mtx);
731
732 return rv;
733}
734
735/**
736 * Issue command and block the current fibril until it is completed or timeout
737 * expires. Nothing is deallocated. Caller should always execute `xhci_cmd_fini`.
738 */
739errno_t xhci_cmd_sync(xhci_hc_t *hc, xhci_cmd_t *cmd)
740{
741 assert(hc);
742 assert(cmd);
743
744 errno_t err;
745
746 if (!cmd_handlers[cmd->_header.cmd]) {
747 /* Handler not implemented. */
748 return ENOTSUP;
749 }
750
751 if ((err = cmd_handlers[cmd->_header.cmd](hc, cmd))) {
752 /* Command could not be issued. */
753 return err;
754 }
755
756 if ((err = wait_for_cmd_completion(hc, cmd))) {
757 /* Command failed. */
758 return err;
759 }
760
761 switch (cmd->status) {
762 case XHCI_TRBC_SUCCESS:
763 return EOK;
764 case XHCI_TRBC_USB_TRANSACTION_ERROR:
765 return ESTALL;
766 case XHCI_TRBC_RESOURCE_ERROR:
767 case XHCI_TRBC_BANDWIDTH_ERROR:
768 case XHCI_TRBC_NO_SLOTS_ERROR:
769 return ELIMIT;
770 case XHCI_TRBC_SLOT_NOT_ENABLED_ERROR:
771 return ENOENT;
772 default:
773 return EINVAL;
774 }
775}
776
777/**
778 * Does the same thing as `xhci_cmd_sync` and executes `xhci_cmd_fini`. This
779 * is a useful shorthand for issuing commands without out parameters.
780 */
781errno_t xhci_cmd_sync_fini(xhci_hc_t *hc, xhci_cmd_t *cmd)
782{
783 const errno_t err = xhci_cmd_sync(hc, cmd);
784 xhci_cmd_fini(cmd);
785
786 return err;
787}
788
789/**
790 * Does the same thing as `xhci_cmd_sync_fini` without blocking the current
791 * fibril. The command is copied to stack memory and `fini` is called upon its completion.
792 */
793errno_t xhci_cmd_async_fini(xhci_hc_t *hc, xhci_cmd_t *stack_cmd)
794{
795 assert(hc);
796 assert(stack_cmd);
797
798 /* Save the command for later. */
799 xhci_cmd_t *heap_cmd = (xhci_cmd_t *) malloc(sizeof(xhci_cmd_t));
800 if (!heap_cmd) {
801 return ENOMEM;
802 }
803
804 /* TODO: Is this good for the mutex and the condvar? */
805 memcpy(heap_cmd, stack_cmd, sizeof(xhci_cmd_t));
806 heap_cmd->_header.async = true;
807
808 /* Issue the command. */
809 errno_t err;
810
811 if (!cmd_handlers[heap_cmd->_header.cmd]) {
812 /* Handler not implemented. */
813 err = ENOTSUP;
814 goto err_heap_cmd;
815 }
816
817 if ((err = cmd_handlers[heap_cmd->_header.cmd](hc, heap_cmd))) {
818 /* Command could not be issued. */
819 goto err_heap_cmd;
820 }
821
822 return EOK;
823
824err_heap_cmd:
825 free(heap_cmd);
826 return err;
827}
828
829/**
830 * @}
831 */
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