source: mainline/uspace/drv/bus/usb/xhci/commands.c@ 370a1c8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 370a1c8 was 4688350b, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

xhci commands: waiting for commands completion uses fibril condvar
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File size: 13.5 KB
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1/*
2 * Copyright (c) 2017 Jaroslav Jindrak
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief Command sending functions.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include <usb/host/utils/malloc32.h>
40#include "commands.h"
41#include "debug.h"
42#include "hc.h"
43#include "hw_struct/context.h"
44#include "hw_struct/trb.h"
45
46#define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
47#define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
48#define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
49#define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
50#define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
51#define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
52
53/**
54 * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
55 */
56#define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
57#define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
58
59#define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
60#define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
61#define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
62
63int xhci_init_commands(xhci_hc_t *hc)
64{
65 assert(hc);
66
67 list_initialize(&hc->commands);
68 return EOK;
69}
70
71void xhci_fini_commands(xhci_hc_t *hc)
72{
73 // Note: Untested.
74 assert(hc);
75
76 // We assume that the hc is dying/stopping, so we ignore
77 // the ownership of the commands.
78 list_foreach(hc->commands, link, xhci_cmd_t, cmd) {
79 xhci_free_command(cmd);
80 }
81}
82
83int xhci_wait_for_command(xhci_cmd_t *cmd, suseconds_t timeout)
84{
85 int rv = EOK;
86
87 fibril_mutex_lock(&cmd->completed_mtx);
88 while (!cmd->completed) {
89 usb_log_debug2("Waiting for event completion: going to sleep.");
90 rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
91
92 usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
93 if (rv == ETIMEOUT)
94 break;
95 }
96 fibril_mutex_lock(&cmd->completed_mtx);
97
98 return rv;
99}
100
101xhci_cmd_t *xhci_alloc_command(void)
102{
103 xhci_cmd_t *cmd = malloc32(sizeof(xhci_cmd_t));
104 xhci_cmd_init(cmd);
105 return cmd;
106}
107
108void xhci_cmd_init(xhci_cmd_t *cmd)
109{
110 memset(cmd, 0, sizeof(*cmd));
111
112 link_initialize(&cmd->link);
113
114 fibril_mutex_initialize(&cmd->completed_mtx);
115 fibril_condvar_initialize(&cmd->completed_cv);
116
117 /**
118 * Internal functions will set this to false, other are implicit
119 * owners unless they overwrite this field.
120 * TODO: Is this wise?
121 */
122 cmd->has_owner = true;
123}
124
125void xhci_free_command(xhci_cmd_t *cmd)
126{
127 list_remove(&cmd->link);
128
129 if (cmd->ictx)
130 free32(cmd->ictx);
131
132 free32(cmd);
133}
134
135static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
136{
137 link_t *cmd_link = list_first(&hc->commands);
138
139
140 usb_log_debug2("Searching TRB %lu...", phys);
141
142 while (cmd_link != NULL) {
143 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
144
145 if (cmd->trb_phys == phys)
146 break;
147
148 cmd_link = list_next(cmd_link, &hc->commands);
149 }
150
151 if (cmd_link != NULL) {
152 list_remove(cmd_link);
153
154 return list_get_instance(cmd_link, xhci_cmd_t, link);
155 }
156
157 return NULL;
158}
159
160static inline int ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
161{
162 assert(hc);
163 uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
164 pio_write_32(&hc->db_arry[doorbell], v);
165 return EOK;
166}
167
168static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
169{
170 assert(hc);
171 assert(cmd);
172
173 list_append(&cmd->link, &hc->commands);
174
175 xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
176 ring_doorbell(hc, doorbell, target);
177
178 usb_log_debug2("HC(%p): Sent command:", hc);
179 xhci_dump_trb(&cmd->trb);
180
181 return EOK;
182}
183
184void xhci_stop_command_ring(xhci_hc_t *hc)
185{
186 assert(hc);
187
188 XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
189
190 /**
191 * Note: There is a bug in qemu that checks CS only when CRCR_HI
192 * is written, this (and the read/write in abort) ensures
193 * the command rings stops.
194 */
195 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
196}
197
198void xhci_abort_command_ring(xhci_hc_t *hc)
199{
200 assert(hc);
201
202 XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
203 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
204}
205
206void xhci_start_command_ring(xhci_hc_t *hc)
207{
208 assert(hc);
209
210 XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
211 ring_doorbell(hc, 0, 0);
212}
213
214static const char *trb_codes [] = {
215#define TRBC(t) [XHCI_TRBC_##t] = #t
216 TRBC(INVALID),
217 TRBC(SUCCESS),
218 TRBC(DATA_BUFFER_ERROR),
219 TRBC(BABBLE_DETECTED_ERROR),
220 TRBC(USB_TRANSACTION_ERROR),
221 TRBC(TRB_ERROR),
222 TRBC(STALL_ERROR),
223 TRBC(RESOURCE_ERROR),
224 TRBC(BANDWIDTH_ERROR),
225 TRBC(NO_SLOTS_ERROR),
226 TRBC(INVALID_STREAM_ERROR),
227 TRBC(SLOT_NOT_ENABLED_ERROR),
228 TRBC(EP_NOT_ENABLED_ERROR),
229 TRBC(SHORT_PACKET),
230 TRBC(RING_UNDERRUN),
231 TRBC(RING_OVERRUN),
232 TRBC(VF_EVENT_RING_FULL),
233 TRBC(PARAMETER_ERROR),
234 TRBC(BANDWIDTH_OVERRUN_ERROR),
235 TRBC(CONTEXT_STATE_ERROR),
236 TRBC(NO_PING_RESPONSE_ERROR),
237 TRBC(EVENT_RING_FULL_ERROR),
238 TRBC(INCOMPATIBLE_DEVICE_ERROR),
239 TRBC(MISSED_SERVICE_ERROR),
240 TRBC(COMMAND_RING_STOPPED),
241 TRBC(COMMAND_ABORTED),
242 TRBC(STOPPED),
243 TRBC(STOPPED_LENGTH_INVALID),
244 TRBC(STOPPED_SHORT_PACKET),
245 TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
246 [30] = "<reserved>",
247 TRBC(ISOCH_BUFFER_OVERRUN),
248 TRBC(EVENT_LOST_ERROR),
249 TRBC(UNDEFINED_ERROR),
250 TRBC(INVALID_STREAM_ID_ERROR),
251 TRBC(SECONDARY_BANDWIDTH_ERROR),
252 TRBC(SPLIT_TRANSACTION_ERROR),
253 [XHCI_TRBC_MAX] = NULL
254#undef TRBC
255};
256
257static void report_error(int code)
258{
259 if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
260 usb_log_error("Command resulted in error: %s.", trb_codes[code]);
261 else
262 usb_log_error("Command resulted in reserved or vendor specific error.");
263}
264
265int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
266{
267 assert(hc);
268
269 xhci_trb_clean(&cmd->trb);
270
271 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
272
273 return enqueue_command(hc, cmd, 0, 0);
274}
275
276int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
277{
278 assert(hc);
279
280 xhci_trb_clean(&cmd->trb);
281
282 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
283 cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
284
285 return enqueue_command(hc, cmd, 0, 0);
286}
287
288int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
289{
290 assert(hc);
291 assert(cmd);
292
293 xhci_trb_clean(&cmd->trb);
294
295 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
296 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
297
298 return enqueue_command(hc, cmd, 0, 0);
299}
300
301int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
302{
303 assert(hc);
304 assert(cmd);
305 assert(cmd->ictx);
306
307 /**
308 * TODO: Requirements for this command:
309 * dcbaa[slot_id] is properly sized and initialized
310 * ictx has valids slot context and endpoint 0, all
311 * other should be ignored at this point (see section 4.6.5).
312 */
313 xhci_trb_clean(&cmd->trb);
314
315 uint64_t phys_addr = (uint64_t) addr_to_phys(cmd->ictx);
316 TRB_SET_ICTX(cmd->trb, phys_addr);
317
318 /**
319 * Note: According to section 6.4.3.4, we can set the 9th bit
320 * of the control field of the trb (BSR) to 1 and then the xHC
321 * will not issue the SET_ADDRESS request to the USB device.
322 * This can be used to provide compatibility with legacy USB devices
323 * that require their device descriptor to be read before such request.
324 */
325 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
326 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
327
328 return enqueue_command(hc, cmd, 0, 0);
329}
330
331int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
332{
333 assert(hc);
334 assert(cmd);
335 assert(cmd->ictx);
336
337 xhci_trb_clean(&cmd->trb);
338
339 uint64_t phys_addr = (uint64_t) addr_to_phys(cmd->ictx);
340 TRB_SET_ICTX(cmd->trb, phys_addr);
341
342 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
343 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
344
345 return enqueue_command(hc, cmd, 0, 0);
346}
347
348int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
349{
350 assert(hc);
351 assert(cmd);
352 assert(cmd->ictx);
353
354 /**
355 * Note: All Drop Context flags of the input context shall be 0,
356 * all Add Context flags shall be initialize to indicate IDs
357 * of the contexts affected by the command.
358 * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
359 */
360 xhci_trb_clean(&cmd->trb);
361
362 uint64_t phys_addr = (uint64_t) addr_to_phys(cmd->ictx);
363 TRB_SET_ICTX(cmd->trb, phys_addr);
364
365 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
366 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
367
368 return enqueue_command(hc, cmd, 0, 0);
369}
370
371int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
372{
373 assert(hc);
374 assert(cmd);
375
376 /**
377 * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
378 * information about this flag.
379 */
380 xhci_trb_clean(&cmd->trb);
381
382 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
383 TRB_SET_TCS(cmd->trb, tcs);
384 TRB_SET_EP(cmd->trb, ep_id);
385 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
386
387 return enqueue_command(hc, cmd, 0, 0);
388}
389
390int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
391{
392 assert(hc);
393 assert(cmd);
394
395 xhci_trb_clean(&cmd->trb);
396
397 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
398 TRB_SET_EP(cmd->trb, ep_id);
399 TRB_SET_SUSP(cmd->trb, susp);
400 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
401
402 return enqueue_command(hc, cmd, 0, 0);
403}
404
405int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
406 uintptr_t dequeue_ptr, uint16_t stream_id,
407 uint32_t ep_id)
408{
409 assert(hc);
410 assert(cmd);
411
412 xhci_trb_clean(&cmd->trb);
413
414 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
415 TRB_SET_EP(cmd->trb, ep_id);
416 TRB_SET_STREAM(cmd->trb, stream_id);
417 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
418 TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
419
420 /**
421 * TODO: Set DCS (see section 4.6.10).
422 */
423
424 return enqueue_command(hc, cmd, 0, 0);
425}
426
427int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
428{
429 assert(hc);
430 assert(cmd);
431
432 xhci_trb_clean(&cmd->trb);
433
434 TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
435 TRB_SET_SLOT(cmd->trb, cmd->slot_id);
436
437 return enqueue_command(hc, cmd, 0, 0);
438}
439
440int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
441{
442 // TODO: Update dequeue ptrs.
443 assert(hc);
444 assert(trb);
445
446 usb_log_debug("HC(%p) Command completed.", hc);
447
448 int code;
449 uint64_t phys;
450 xhci_cmd_t *command;
451
452 code = TRB_GET_CODE(*trb);
453 phys = TRB_GET_PHYS(*trb);;
454 command = get_command(hc, phys);
455 if (command == NULL) {
456 // TODO: STOP & ABORT may not have command structs in the list!
457 usb_log_error("No command struct for this completion event");
458
459 if (code != XHCI_TRBC_SUCCESS)
460 report_error(code);
461
462 return EOK;
463 }
464
465 command->status = code;
466 command->slot_id = TRB_GET_SLOT(*trb);
467
468 usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
469 if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
470 if (code != XHCI_TRBC_SUCCESS) {
471 report_error(code);
472 xhci_dump_trb(&command->trb);
473 }
474 }
475
476 switch (TRB_TYPE(command->trb)) {
477 case XHCI_TRB_TYPE_NO_OP_CMD:
478 assert(code == XHCI_TRBC_TRB_ERROR);
479 break;
480 case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
481 break;
482 case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
483 break;
484 case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
485 break;
486 case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
487 break;
488 case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
489 break;
490 case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
491 break;
492 case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
493 // Note: If the endpoint was in the middle of a transfer, then the xHC
494 // will add a Transfer TRB before the Event TRB, research that and
495 // handle it appropriately!
496 break;
497 case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
498 break;
499 default:
500 usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
501
502 command->completed = true;
503 return ENAK;
504 }
505
506 fibril_mutex_lock(&command->completed_mtx);
507 command->completed = true;
508 fibril_condvar_broadcast(&command->completed_cv);
509 fibril_mutex_unlock(&command->completed_mtx);
510
511
512 if (!command->has_owner) {
513 usb_log_debug2("Command has no owner, deallocating.");
514 xhci_free_command(command);
515 } else {
516 usb_log_debug2("Command has owner, don't forget to deallocate!");
517 }
518
519 return EOK;
520}
521
522
523/**
524 * @}
525 */
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