[c9c0e41] | 1 | /*
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| 2 | * Copyright (c) 2017 Jaroslav Jindrak
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Command sending functions.
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| 34 | */
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| 35 |
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| 36 | #include <errno.h>
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| 37 | #include <str_error.h>
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| 38 | #include <usb/debug.h>
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| 39 | #include <usb/host/utils/malloc32.h>
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| 40 | #include "commands.h"
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| 41 | #include "debug.h"
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| 42 | #include "hc.h"
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[8db42f7] | 43 | #include "hw_struct/context.h"
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[c9c0e41] | 44 | #include "hw_struct/trb.h"
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| 45 |
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[1b78a7c1] | 46 | #define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
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| 47 | #define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
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| 48 | #define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
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[0cabd10] | 49 | #define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
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[1b78a7c1] | 50 | #define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
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| 51 | #define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
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| 52 |
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[0cabd10] | 53 | /**
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| 54 | * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
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| 55 | */
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| 56 | #define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
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[548c123] | 57 | #define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, phys_addr & (~0xF))
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[1b78a7c1] | 58 |
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| 59 | #define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
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| 60 | #define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
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| 61 | #define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
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| 62 |
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[110d795] | 63 | int xhci_init_commands(xhci_hc_t *hc)
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| 64 | {
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| 65 | assert(hc);
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| 66 |
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| 67 | list_initialize(&hc->commands);
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| 68 | return EOK;
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| 69 | }
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| 70 |
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[c46c356] | 71 | void xhci_fini_commands(xhci_hc_t *hc)
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| 72 | {
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| 73 | // Note: Untested.
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| 74 | assert(hc);
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| 75 | }
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| 76 |
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[04df063] | 77 | int xhci_cmd_wait(xhci_cmd_t *cmd, suseconds_t timeout)
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[110d795] | 78 | {
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[4688350b] | 79 | int rv = EOK;
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| 80 |
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| 81 | fibril_mutex_lock(&cmd->completed_mtx);
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[110d795] | 82 | while (!cmd->completed) {
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[4688350b] | 83 | usb_log_debug2("Waiting for event completion: going to sleep.");
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| 84 | rv = fibril_condvar_wait_timeout(&cmd->completed_cv, &cmd->completed_mtx, timeout);
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[110d795] | 85 |
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[4688350b] | 86 | usb_log_debug2("Waiting for event completion: woken: %s", str_error(rv));
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| 87 | if (rv == ETIMEOUT)
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| 88 | break;
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[110d795] | 89 | }
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[1f76b7d] | 90 | fibril_mutex_unlock(&cmd->completed_mtx);
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[110d795] | 91 |
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[4688350b] | 92 | return rv;
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[110d795] | 93 | }
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| 94 |
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[04df063] | 95 | xhci_cmd_t *xhci_cmd_alloc(void)
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[110d795] | 96 | {
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| 97 | xhci_cmd_t *cmd = malloc32(sizeof(xhci_cmd_t));
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[4688350b] | 98 | xhci_cmd_init(cmd);
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[04df063] | 99 |
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| 100 | usb_log_debug2("Allocating cmd on the heap. Don't forget to deallocate it!");
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[4688350b] | 101 | return cmd;
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| 102 | }
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| 103 |
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| 104 | void xhci_cmd_init(xhci_cmd_t *cmd)
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| 105 | {
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| 106 | memset(cmd, 0, sizeof(*cmd));
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[110d795] | 107 |
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| 108 | link_initialize(&cmd->link);
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| 109 |
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[4688350b] | 110 | fibril_mutex_initialize(&cmd->completed_mtx);
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| 111 | fibril_condvar_initialize(&cmd->completed_cv);
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[110d795] | 112 | }
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| 113 |
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[04df063] | 114 | void xhci_cmd_fini(xhci_cmd_t *cmd)
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[110d795] | 115 | {
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[9304b66] | 116 | list_remove(&cmd->link);
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[04df063] | 117 | }
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[9304b66] | 118 |
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[04df063] | 119 | void xhci_cmd_free(xhci_cmd_t *cmd)
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| 120 | {
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| 121 | xhci_cmd_fini(cmd);
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[110d795] | 122 | free32(cmd);
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| 123 | }
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| 124 |
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[2fa43d1] | 125 | static inline xhci_cmd_t *get_command(xhci_hc_t *hc, uint64_t phys)
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[110d795] | 126 | {
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| 127 | link_t *cmd_link = list_first(&hc->commands);
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| 128 |
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[548c123] | 129 |
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| 130 | usb_log_debug2("Searching TRB %lu...", phys);
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| 131 |
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[2fa43d1] | 132 | while (cmd_link != NULL) {
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| 133 | xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, link);
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| 134 |
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[548c123] | 135 | if (cmd->trb_phys == phys)
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[2fa43d1] | 136 | break;
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| 137 |
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| 138 | cmd_link = list_next(cmd_link, &hc->commands);
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| 139 | }
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| 140 |
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[110d795] | 141 | if (cmd_link != NULL) {
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| 142 | list_remove(cmd_link);
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[9f5b613] | 143 |
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[110d795] | 144 | return list_get_instance(cmd_link, xhci_cmd_t, link);
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| 145 | }
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| 146 |
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| 147 | return NULL;
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| 148 | }
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| 149 |
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[481af21e] | 150 | static inline int ring_doorbell(xhci_hc_t *hc, unsigned doorbell, unsigned target)
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[c9c0e41] | 151 | {
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[c058a388] | 152 | assert(hc);
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[c9c0e41] | 153 | uint32_t v = host2xhci(32, target & BIT_RRANGE(uint32_t, 7));
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| 154 | pio_write_32(&hc->db_arry[doorbell], v);
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| 155 | return EOK;
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| 156 | }
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| 157 |
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[548c123] | 158 | static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd, unsigned doorbell, unsigned target)
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[481af21e] | 159 | {
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[c058a388] | 160 | assert(hc);
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[548c123] | 161 | assert(cmd);
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| 162 |
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| 163 | list_append(&cmd->link, &hc->commands);
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[c058a388] | 164 |
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[548c123] | 165 | xhci_trb_ring_enqueue(&hc->command_ring, &cmd->trb, &cmd->trb_phys);
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[481af21e] | 166 | ring_doorbell(hc, doorbell, target);
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| 167 |
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[548c123] | 168 | usb_log_debug2("HC(%p): Sent command:", hc);
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| 169 | xhci_dump_trb(&cmd->trb);
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[481af21e] | 170 |
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| 171 | return EOK;
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| 172 | }
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| 173 |
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[3dc519f] | 174 | void xhci_stop_command_ring(xhci_hc_t *hc)
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| 175 | {
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| 176 | assert(hc);
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| 177 |
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| 178 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
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| 179 |
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| 180 | /**
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| 181 | * Note: There is a bug in qemu that checks CS only when CRCR_HI
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| 182 | * is written, this (and the read/write in abort) ensures
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| 183 | * the command rings stops.
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| 184 | */
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| 185 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
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| 186 | }
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| 187 |
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| 188 | void xhci_abort_command_ring(xhci_hc_t *hc)
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| 189 | {
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| 190 | assert(hc);
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| 191 |
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| 192 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
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| 193 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, XHCI_REG_RD(hc->op_regs, XHCI_OP_CRCR_HI));
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| 194 | }
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| 195 |
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| 196 | void xhci_start_command_ring(xhci_hc_t *hc)
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| 197 | {
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| 198 | assert(hc);
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| 199 |
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| 200 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CRR, 1);
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| 201 | ring_doorbell(hc, 0, 0);
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| 202 | }
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| 203 |
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[4fa5342] | 204 | static const char *trb_codes [] = {
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| 205 | #define TRBC(t) [XHCI_TRBC_##t] = #t
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| 206 | TRBC(INVALID),
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| 207 | TRBC(SUCCESS),
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| 208 | TRBC(DATA_BUFFER_ERROR),
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| 209 | TRBC(BABBLE_DETECTED_ERROR),
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| 210 | TRBC(USB_TRANSACTION_ERROR),
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| 211 | TRBC(TRB_ERROR),
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| 212 | TRBC(STALL_ERROR),
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| 213 | TRBC(RESOURCE_ERROR),
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| 214 | TRBC(BANDWIDTH_ERROR),
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| 215 | TRBC(NO_SLOTS_ERROR),
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| 216 | TRBC(INVALID_STREAM_ERROR),
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| 217 | TRBC(SLOT_NOT_ENABLED_ERROR),
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| 218 | TRBC(EP_NOT_ENABLED_ERROR),
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| 219 | TRBC(SHORT_PACKET),
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| 220 | TRBC(RING_UNDERRUN),
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| 221 | TRBC(RING_OVERRUN),
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| 222 | TRBC(VF_EVENT_RING_FULL),
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| 223 | TRBC(PARAMETER_ERROR),
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| 224 | TRBC(BANDWIDTH_OVERRUN_ERROR),
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| 225 | TRBC(CONTEXT_STATE_ERROR),
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| 226 | TRBC(NO_PING_RESPONSE_ERROR),
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| 227 | TRBC(EVENT_RING_FULL_ERROR),
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| 228 | TRBC(INCOMPATIBLE_DEVICE_ERROR),
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| 229 | TRBC(MISSED_SERVICE_ERROR),
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| 230 | TRBC(COMMAND_RING_STOPPED),
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| 231 | TRBC(COMMAND_ABORTED),
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| 232 | TRBC(STOPPED),
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| 233 | TRBC(STOPPED_LENGTH_INVALID),
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| 234 | TRBC(STOPPED_SHORT_PACKET),
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| 235 | TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
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| 236 | [30] = "<reserved>",
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| 237 | TRBC(ISOCH_BUFFER_OVERRUN),
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| 238 | TRBC(EVENT_LOST_ERROR),
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| 239 | TRBC(UNDEFINED_ERROR),
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| 240 | TRBC(INVALID_STREAM_ID_ERROR),
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| 241 | TRBC(SECONDARY_BANDWIDTH_ERROR),
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| 242 | TRBC(SPLIT_TRANSACTION_ERROR),
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| 243 | [XHCI_TRBC_MAX] = NULL
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| 244 | #undef TRBC
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| 245 | };
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| 246 |
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| 247 | static void report_error(int code)
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| 248 | {
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| 249 | if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
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| 250 | usb_log_error("Command resulted in error: %s.", trb_codes[code]);
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| 251 | else
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| 252 | usb_log_error("Command resulted in reserved or vendor specific error.");
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| 253 | }
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| 254 |
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[110d795] | 255 | int xhci_send_no_op_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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[c9c0e41] | 256 | {
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[c058a388] | 257 | assert(hc);
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| 258 |
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[548c123] | 259 | xhci_trb_clean(&cmd->trb);
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[c9c0e41] | 260 |
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[548c123] | 261 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_NO_OP_CMD);
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[110d795] | 262 |
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[548c123] | 263 | return enqueue_command(hc, cmd, 0, 0);
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[c9c0e41] | 264 | }
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| 265 |
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[110d795] | 266 | int xhci_send_enable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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[c9c0e41] | 267 | {
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[c058a388] | 268 | assert(hc);
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| 269 |
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[548c123] | 270 | xhci_trb_clean(&cmd->trb);
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[c9c0e41] | 271 |
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[548c123] | 272 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
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| 273 | cmd->trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
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[110d795] | 274 |
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[548c123] | 275 | return enqueue_command(hc, cmd, 0, 0);
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[5ac5eb1] | 276 | }
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| 277 |
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[110d795] | 278 | int xhci_send_disable_slot_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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[5ac5eb1] | 279 | {
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[c058a388] | 280 | assert(hc);
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[110d795] | 281 | assert(cmd);
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[c058a388] | 282 |
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[548c123] | 283 | xhci_trb_clean(&cmd->trb);
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[5ac5eb1] | 284 |
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[548c123] | 285 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
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| 286 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
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[110d795] | 287 |
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[548c123] | 288 | return enqueue_command(hc, cmd, 0, 0);
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[c9c0e41] | 289 | }
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| 290 |
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[04df063] | 291 | int xhci_send_address_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
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[8db42f7] | 292 | {
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[c058a388] | 293 | assert(hc);
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[110d795] | 294 | assert(cmd);
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[04df063] | 295 | assert(ictx);
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[c058a388] | 296 |
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[8db42f7] | 297 | /**
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| 298 | * TODO: Requirements for this command:
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| 299 | * dcbaa[slot_id] is properly sized and initialized
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| 300 | * ictx has valids slot context and endpoint 0, all
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| 301 | * other should be ignored at this point (see section 4.6.5).
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| 302 | */
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[04df063] | 303 |
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[548c123] | 304 | xhci_trb_clean(&cmd->trb);
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[8db42f7] | 305 |
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[04df063] | 306 | uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
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[548c123] | 307 | TRB_SET_ICTX(cmd->trb, phys_addr);
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[8db42f7] | 308 |
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| 309 | /**
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| 310 | * Note: According to section 6.4.3.4, we can set the 9th bit
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| 311 | * of the control field of the trb (BSR) to 1 and then the xHC
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| 312 | * will not issue the SET_ADDRESS request to the USB device.
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| 313 | * This can be used to provide compatibility with legacy USB devices
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| 314 | * that require their device descriptor to be read before such request.
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| 315 | */
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[548c123] | 316 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
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| 317 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
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[8db42f7] | 318 |
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[548c123] | 319 | return enqueue_command(hc, cmd, 0, 0);
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[8db42f7] | 320 | }
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| 321 |
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[04df063] | 322 | int xhci_send_configure_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
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[665bf3c] | 323 | {
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[c058a388] | 324 | assert(hc);
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[110d795] | 325 | assert(cmd);
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[04df063] | 326 | assert(ictx);
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[c058a388] | 327 |
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[548c123] | 328 | xhci_trb_clean(&cmd->trb);
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[665bf3c] | 329 |
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[04df063] | 330 | uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
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[548c123] | 331 | TRB_SET_ICTX(cmd->trb, phys_addr);
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[110d795] | 332 |
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[548c123] | 333 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
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| 334 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
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[665bf3c] | 335 |
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[548c123] | 336 | return enqueue_command(hc, cmd, 0, 0);
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[665bf3c] | 337 | }
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| 338 |
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[04df063] | 339 | int xhci_send_evaluate_context_command(xhci_hc_t *hc, xhci_cmd_t *cmd, xhci_input_ctx_t *ictx)
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[c9ce62ae] | 340 | {
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[c058a388] | 341 | assert(hc);
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[110d795] | 342 | assert(cmd);
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[04df063] | 343 | assert(ictx);
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[c058a388] | 344 |
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[c9ce62ae] | 345 | /**
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| 346 | * Note: All Drop Context flags of the input context shall be 0,
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| 347 | * all Add Context flags shall be initialize to indicate IDs
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| 348 | * of the contexts affected by the command.
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| 349 | * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
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| 350 | */
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[548c123] | 351 | xhci_trb_clean(&cmd->trb);
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[c9ce62ae] | 352 |
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[04df063] | 353 | uint64_t phys_addr = (uint64_t) addr_to_phys(ictx);
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[548c123] | 354 | TRB_SET_ICTX(cmd->trb, phys_addr);
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[c9ce62ae] | 355 |
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[548c123] | 356 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
|
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| 357 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
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[110d795] | 358 |
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[548c123] | 359 | return enqueue_command(hc, cmd, 0, 0);
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[c9ce62ae] | 360 | }
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| 361 |
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[110d795] | 362 | int xhci_send_reset_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t tcs)
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[05aeee0e] | 363 | {
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[c058a388] | 364 | assert(hc);
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[110d795] | 365 | assert(cmd);
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[c058a388] | 366 |
|
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[05aeee0e] | 367 | /**
|
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| 368 | * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
|
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| 369 | * information about this flag.
|
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| 370 | */
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[548c123] | 371 | xhci_trb_clean(&cmd->trb);
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[05aeee0e] | 372 |
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[548c123] | 373 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
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| 374 | TRB_SET_TCS(cmd->trb, tcs);
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| 375 | TRB_SET_EP(cmd->trb, ep_id);
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| 376 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
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[c9bec1c] | 377 |
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[548c123] | 378 | return enqueue_command(hc, cmd, 0, 0);
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[05aeee0e] | 379 | }
|
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| 380 |
|
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[110d795] | 381 | int xhci_send_stop_endpoint_command(xhci_hc_t *hc, xhci_cmd_t *cmd, uint32_t ep_id, uint8_t susp)
|
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[05aeee0e] | 382 | {
|
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[c058a388] | 383 | assert(hc);
|
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[110d795] | 384 | assert(cmd);
|
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[c058a388] | 385 |
|
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[548c123] | 386 | xhci_trb_clean(&cmd->trb);
|
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[110d795] | 387 |
|
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[548c123] | 388 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
|
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| 389 | TRB_SET_EP(cmd->trb, ep_id);
|
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| 390 | TRB_SET_SUSP(cmd->trb, susp);
|
---|
| 391 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
---|
[05aeee0e] | 392 |
|
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[548c123] | 393 | return enqueue_command(hc, cmd, 0, 0);
|
---|
[c058a388] | 394 | }
|
---|
[05aeee0e] | 395 |
|
---|
[0cabd10] | 396 | int xhci_send_set_dequeue_ptr_command(xhci_hc_t *hc, xhci_cmd_t *cmd,
|
---|
| 397 | uintptr_t dequeue_ptr, uint16_t stream_id,
|
---|
| 398 | uint32_t ep_id)
|
---|
| 399 | {
|
---|
| 400 | assert(hc);
|
---|
| 401 | assert(cmd);
|
---|
| 402 |
|
---|
[548c123] | 403 | xhci_trb_clean(&cmd->trb);
|
---|
[0cabd10] | 404 |
|
---|
[548c123] | 405 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
|
---|
| 406 | TRB_SET_EP(cmd->trb, ep_id);
|
---|
| 407 | TRB_SET_STREAM(cmd->trb, stream_id);
|
---|
| 408 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
---|
| 409 | TRB_SET_DEQUEUE_PTR(cmd->trb, dequeue_ptr);
|
---|
[0cabd10] | 410 |
|
---|
| 411 | /**
|
---|
| 412 | * TODO: Set DCS (see section 4.6.10).
|
---|
| 413 | */
|
---|
| 414 |
|
---|
[548c123] | 415 | return enqueue_command(hc, cmd, 0, 0);
|
---|
[0cabd10] | 416 | }
|
---|
| 417 |
|
---|
[110d795] | 418 | int xhci_send_reset_device_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c058a388] | 419 | {
|
---|
| 420 | assert(hc);
|
---|
[110d795] | 421 | assert(cmd);
|
---|
[c058a388] | 422 |
|
---|
[548c123] | 423 | xhci_trb_clean(&cmd->trb);
|
---|
[c058a388] | 424 |
|
---|
[548c123] | 425 | TRB_SET_TYPE(cmd->trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
|
---|
| 426 | TRB_SET_SLOT(cmd->trb, cmd->slot_id);
|
---|
[c9bec1c] | 427 |
|
---|
[548c123] | 428 | return enqueue_command(hc, cmd, 0, 0);
|
---|
[05aeee0e] | 429 | }
|
---|
| 430 |
|
---|
[f9e7fe8] | 431 | int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
|
---|
| 432 | {
|
---|
[110d795] | 433 | // TODO: Update dequeue ptrs.
|
---|
[c058a388] | 434 | assert(hc);
|
---|
| 435 | assert(trb);
|
---|
| 436 |
|
---|
[5ac5eb1] | 437 | usb_log_debug("HC(%p) Command completed.", hc);
|
---|
[f9e7fe8] | 438 |
|
---|
[5ac5eb1] | 439 | int code;
|
---|
[2fa43d1] | 440 | uint64_t phys;
|
---|
[110d795] | 441 | xhci_cmd_t *command;
|
---|
[f711f06] | 442 |
|
---|
[1b78a7c1] | 443 | code = TRB_GET_CODE(*trb);
|
---|
| 444 | phys = TRB_GET_PHYS(*trb);;
|
---|
[2fa43d1] | 445 | command = get_command(hc, phys);
|
---|
| 446 | if (command == NULL) {
|
---|
| 447 | // TODO: STOP & ABORT may not have command structs in the list!
|
---|
[04df063] | 448 | usb_log_debug("No command struct for this completion event found.");
|
---|
[2fa43d1] | 449 |
|
---|
| 450 | if (code != XHCI_TRBC_SUCCESS)
|
---|
| 451 | report_error(code);
|
---|
| 452 |
|
---|
| 453 | return EOK;
|
---|
| 454 | }
|
---|
[110d795] | 455 |
|
---|
| 456 | command->status = code;
|
---|
[1b78a7c1] | 457 | command->slot_id = TRB_GET_SLOT(*trb);
|
---|
[110d795] | 458 |
|
---|
[548c123] | 459 | usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
|
---|
| 460 | if (TRB_TYPE(command->trb) != XHCI_TRB_TYPE_NO_OP_CMD) {
|
---|
[665bf3c] | 461 | if (code != XHCI_TRBC_SUCCESS) {
|
---|
[4fa5342] | 462 | report_error(code);
|
---|
[548c123] | 463 | xhci_dump_trb(&command->trb);
|
---|
[665bf3c] | 464 | }
|
---|
| 465 | }
|
---|
[c362127] | 466 |
|
---|
[548c123] | 467 | switch (TRB_TYPE(command->trb)) {
|
---|
[c362127] | 468 | case XHCI_TRB_TYPE_NO_OP_CMD:
|
---|
[9f5b613] | 469 | assert(code == XHCI_TRBC_TRB_ERROR);
|
---|
[110d795] | 470 | break;
|
---|
[c362127] | 471 | case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
|
---|
[110d795] | 472 | break;
|
---|
[5ac5eb1] | 473 | case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
|
---|
[110d795] | 474 | break;
|
---|
[8db42f7] | 475 | case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
|
---|
[110d795] | 476 | break;
|
---|
[665bf3c] | 477 | case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
|
---|
[110d795] | 478 | break;
|
---|
[c9ce62ae] | 479 | case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
|
---|
[110d795] | 480 | break;
|
---|
[05aeee0e] | 481 | case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
|
---|
[110d795] | 482 | break;
|
---|
[05aeee0e] | 483 | case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
|
---|
| 484 | // Note: If the endpoint was in the middle of a transfer, then the xHC
|
---|
| 485 | // will add a Transfer TRB before the Event TRB, research that and
|
---|
| 486 | // handle it appropriately!
|
---|
[110d795] | 487 | break;
|
---|
[c058a388] | 488 | case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
|
---|
[110d795] | 489 | break;
|
---|
[c362127] | 490 | default:
|
---|
[548c123] | 491 | usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->trb)));
|
---|
[110d795] | 492 |
|
---|
| 493 | command->completed = true;
|
---|
[665bf3c] | 494 | return ENAK;
|
---|
[f711f06] | 495 | }
|
---|
[110d795] | 496 |
|
---|
[4688350b] | 497 | fibril_mutex_lock(&command->completed_mtx);
|
---|
[110d795] | 498 | command->completed = true;
|
---|
[4688350b] | 499 | fibril_condvar_broadcast(&command->completed_cv);
|
---|
| 500 | fibril_mutex_unlock(&command->completed_mtx);
|
---|
| 501 |
|
---|
[110d795] | 502 | return EOK;
|
---|
[f9e7fe8] | 503 | }
|
---|
[c9c0e41] | 504 |
|
---|
| 505 |
|
---|
| 506 | /**
|
---|
| 507 | * @}
|
---|
| 508 | */
|
---|