[c9c0e41] | 1 | /*
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| 2 | * Copyright (c) 2017 Jaroslav Jindrak
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Command sending functions.
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| 34 | */
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| 35 |
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| 36 | #include <errno.h>
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| 37 | #include <str_error.h>
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| 38 | #include <usb/debug.h>
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| 39 | #include "commands.h"
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| 40 | #include "debug.h"
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| 41 | #include "hc.h"
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[8db42f7] | 42 | #include "hw_struct/context.h"
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[c9c0e41] | 43 | #include "hw_struct/trb.h"
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| 44 |
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[1b78a7c1] | 45 | #define TRB_SET_TCS(trb, tcs) (trb).control |= host2xhci(32, ((tcs &0x1) << 9))
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| 46 | #define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
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[b724494] | 47 | #define TRB_SET_DC(trb, dc) (trb).control |= host2xhci(32, (dc) << 9)
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[1b78a7c1] | 48 | #define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
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[0cabd10] | 49 | #define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
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[1b78a7c1] | 50 | #define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
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| 51 | #define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
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[60af4cdb] | 52 | #define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
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[1b78a7c1] | 53 |
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[0cabd10] | 54 | /**
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| 55 | * TODO: Not sure about SCT and DCS (see section 6.4.3.9).
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| 56 | */
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| 57 | #define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
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[b80c1ab] | 58 | #define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, (phys) & (~0xF))
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[1b78a7c1] | 59 |
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| 60 | #define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
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| 61 | #define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
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| 62 | #define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
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| 63 |
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[c3d926f3] | 64 | /* Control functions */
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| 65 |
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[889146e] | 66 | static xhci_cmd_ring_t *get_cmd_ring(xhci_hc_t *hc)
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[110d795] | 67 | {
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| 68 | assert(hc);
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[889146e] | 69 | return &hc->cr;
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| 70 | }
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| 71 |
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[eb928c4] | 72 | /**
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| 73 | * Initialize the command subsystem. Allocates the comand ring.
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| 74 | *
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| 75 | * Does not configure the CR pointer to the hardware, because the xHC will be
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| 76 | * reset before starting.
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| 77 | */
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[889146e] | 78 | int xhci_init_commands(xhci_hc_t *hc)
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| 79 | {
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| 80 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 81 | int err;
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| 82 |
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| 83 | if ((err = xhci_trb_ring_init(&cr->trb_ring)))
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| 84 | return err;
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[110d795] | 85 |
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[889146e] | 86 | fibril_mutex_initialize(&cr->guard);
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| 87 | fibril_condvar_initialize(&cr->state_cv);
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| 88 | fibril_condvar_initialize(&cr->stopped_cv);
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[74b852b] | 89 |
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[889146e] | 90 | list_initialize(&cr->cmd_list);
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| 91 |
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| 92 | cr->state = XHCI_CR_STATE_OPEN;
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[74b852b] | 93 |
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[110d795] | 94 | return EOK;
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| 95 | }
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| 96 |
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[eb928c4] | 97 | /**
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| 98 | * Finish the command subsystem. Stops the hardware from running commands, then
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| 99 | * deallocates the ring.
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| 100 | */
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[c46c356] | 101 | void xhci_fini_commands(xhci_hc_t *hc)
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| 102 | {
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| 103 | assert(hc);
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[eb928c4] | 104 | xhci_stop_command_ring(hc);
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| 105 |
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| 106 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 107 |
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| 108 | fibril_mutex_lock(&cr->guard);
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| 109 | xhci_trb_ring_fini(&cr->trb_ring);
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| 110 | fibril_mutex_unlock(&cr->guard);
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[c46c356] | 111 | }
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| 112 |
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[eb928c4] | 113 | /**
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| 114 | * Initialize a command structure for the given command.
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| 115 | */
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[c3d926f3] | 116 | void xhci_cmd_init(xhci_cmd_t *cmd, xhci_cmd_type_t type)
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[110d795] | 117 | {
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[c3d926f3] | 118 | memset(cmd, 0, sizeof(*cmd));
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[110d795] | 119 |
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[c3d926f3] | 120 | link_initialize(&cmd->_header.link);
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[110d795] | 121 |
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[c3d926f3] | 122 | fibril_mutex_initialize(&cmd->_header.completed_mtx);
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| 123 | fibril_condvar_initialize(&cmd->_header.completed_cv);
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[04df063] | 124 |
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[c3d926f3] | 125 | cmd->_header.cmd = type;
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[4688350b] | 126 | }
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| 127 |
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[eb928c4] | 128 | /**
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| 129 | * Finish the command structure. Some command invocation includes allocating
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| 130 | * a context structure. To have the convenience in calling commands, this
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| 131 | * method deallocates all resources.
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| 132 | */
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[c3d926f3] | 133 | void xhci_cmd_fini(xhci_cmd_t *cmd)
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[4688350b] | 134 | {
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[c3d926f3] | 135 | list_remove(&cmd->_header.link);
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[110d795] | 136 |
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[b80c1ab] | 137 | dma_buffer_free(&cmd->input_ctx);
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| 138 | dma_buffer_free(&cmd->bandwidth_ctx);
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[9304b66] | 139 |
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[c3d926f3] | 140 | if (cmd->_header.async) {
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| 141 | free(cmd);
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| 142 | }
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[110d795] | 143 | }
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| 144 |
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[eb928c4] | 145 | /**
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| 146 | * Find a command issued by TRB at @c phys inside the command list.
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| 147 | *
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| 148 | * Call with guard locked only.
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| 149 | */
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[889146e] | 150 | static inline xhci_cmd_t *find_command(xhci_hc_t *hc, uint64_t phys)
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[110d795] | 151 | {
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[889146e] | 152 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 153 | assert(fibril_mutex_is_locked(&cr->guard));
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[74b852b] | 154 |
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[889146e] | 155 | link_t *cmd_link = list_first(&cr->cmd_list);
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[110d795] | 156 |
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[2fa43d1] | 157 | while (cmd_link != NULL) {
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[c3d926f3] | 158 | xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, _header.link);
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[2fa43d1] | 159 |
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[c3d926f3] | 160 | if (cmd->_header.trb_phys == phys)
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[2fa43d1] | 161 | break;
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| 162 |
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[889146e] | 163 | cmd_link = list_next(cmd_link, &cr->cmd_list);
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[2fa43d1] | 164 | }
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| 165 |
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[889146e] | 166 | return cmd_link ? list_get_instance(cmd_link, xhci_cmd_t, _header.link)
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| 167 | : NULL;
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[110d795] | 168 | }
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| 169 |
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[eb928c4] | 170 | /**
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| 171 | * Enqueue a command on the TRB ring. Ring the doorbell to initiate processing.
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| 172 | * Register the command as waiting for completion inside the command list.
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| 173 | */
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| 174 | static inline int enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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[481af21e] | 175 | {
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[889146e] | 176 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[548c123] | 177 | assert(cmd);
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| 178 |
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[889146e] | 179 | fibril_mutex_lock(&cr->guard);
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[c058a388] | 180 |
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[889146e] | 181 | while (cr->state == XHCI_CR_STATE_CHANGING)
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| 182 | fibril_condvar_wait(&cr->state_cv, &cr->guard);
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[481af21e] | 183 |
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[889146e] | 184 | if (cr->state != XHCI_CR_STATE_OPEN) {
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| 185 | fibril_mutex_unlock(&cr->guard);
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| 186 | return ENAK;
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| 187 | }
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| 188 |
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| 189 | usb_log_debug2("HC(%p): Sending command:", hc);
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[c3d926f3] | 190 | xhci_dump_trb(&cmd->_header.trb);
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[481af21e] | 191 |
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[889146e] | 192 | list_append(&cmd->_header.link, &cr->cmd_list);
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| 193 |
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| 194 | xhci_trb_ring_enqueue(&cr->trb_ring, &cmd->_header.trb, &cmd->_header.trb_phys);
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| 195 | hc_ring_doorbell(hc, 0, 0);
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| 196 |
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| 197 | fibril_mutex_unlock(&cr->guard);
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| 198 |
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[481af21e] | 199 | return EOK;
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| 200 | }
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| 201 |
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[eb928c4] | 202 | /**
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| 203 | * Stop the command ring. Stop processing commands, block issuing new ones.
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| 204 | * Wait until hardware acknowledges it is stopped.
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| 205 | */
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[3dc519f] | 206 | void xhci_stop_command_ring(xhci_hc_t *hc)
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| 207 | {
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[889146e] | 208 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[3dc519f] | 209 |
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[889146e] | 210 | fibril_mutex_lock(&cr->guard);
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[3dc519f] | 211 |
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[889146e] | 212 | // Prevent others from starting CR again.
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| 213 | cr->state = XHCI_CR_STATE_CLOSED;
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| 214 | fibril_condvar_broadcast(&cr->state_cv);
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[3dc519f] | 215 |
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[889146e] | 216 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
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| 217 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CRCR_HI, 0); // Some systems (incl. QEMU) require 64-bit write
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[3dc519f] | 218 |
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[889146e] | 219 | while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR))
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| 220 | fibril_condvar_wait(&cr->stopped_cv, &cr->guard);
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| 221 |
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| 222 | fibril_mutex_unlock(&cr->guard);
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[3dc519f] | 223 | }
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| 224 |
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[eb928c4] | 225 | /**
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| 226 | * Abort currently processed command. Note that it is only aborted when the
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| 227 | * command is "blocking" - see section 4.6.1.2 of xHCI spec.
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| 228 | */
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[889146e] | 229 | static void abort_command_ring(xhci_hc_t *hc)
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[3dc519f] | 230 | {
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[889146e] | 231 | XHCI_REG_WR(hc->op_regs, XHCI_OP_CA, 1);
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| 232 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CRCR_HI, 0); // Some systems (incl. QEMU) require 64-bit write
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[3dc519f] | 233 | }
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| 234 |
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[4fa5342] | 235 | static const char *trb_codes [] = {
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| 236 | #define TRBC(t) [XHCI_TRBC_##t] = #t
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| 237 | TRBC(INVALID),
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| 238 | TRBC(SUCCESS),
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| 239 | TRBC(DATA_BUFFER_ERROR),
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| 240 | TRBC(BABBLE_DETECTED_ERROR),
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| 241 | TRBC(USB_TRANSACTION_ERROR),
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| 242 | TRBC(TRB_ERROR),
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| 243 | TRBC(STALL_ERROR),
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| 244 | TRBC(RESOURCE_ERROR),
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| 245 | TRBC(BANDWIDTH_ERROR),
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| 246 | TRBC(NO_SLOTS_ERROR),
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| 247 | TRBC(INVALID_STREAM_ERROR),
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| 248 | TRBC(SLOT_NOT_ENABLED_ERROR),
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| 249 | TRBC(EP_NOT_ENABLED_ERROR),
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| 250 | TRBC(SHORT_PACKET),
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| 251 | TRBC(RING_UNDERRUN),
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| 252 | TRBC(RING_OVERRUN),
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| 253 | TRBC(VF_EVENT_RING_FULL),
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| 254 | TRBC(PARAMETER_ERROR),
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| 255 | TRBC(BANDWIDTH_OVERRUN_ERROR),
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| 256 | TRBC(CONTEXT_STATE_ERROR),
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| 257 | TRBC(NO_PING_RESPONSE_ERROR),
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| 258 | TRBC(EVENT_RING_FULL_ERROR),
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| 259 | TRBC(INCOMPATIBLE_DEVICE_ERROR),
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| 260 | TRBC(MISSED_SERVICE_ERROR),
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| 261 | TRBC(COMMAND_RING_STOPPED),
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| 262 | TRBC(COMMAND_ABORTED),
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| 263 | TRBC(STOPPED),
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| 264 | TRBC(STOPPED_LENGTH_INVALID),
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| 265 | TRBC(STOPPED_SHORT_PACKET),
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| 266 | TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
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| 267 | [30] = "<reserved>",
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| 268 | TRBC(ISOCH_BUFFER_OVERRUN),
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| 269 | TRBC(EVENT_LOST_ERROR),
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| 270 | TRBC(UNDEFINED_ERROR),
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| 271 | TRBC(INVALID_STREAM_ID_ERROR),
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| 272 | TRBC(SECONDARY_BANDWIDTH_ERROR),
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| 273 | TRBC(SPLIT_TRANSACTION_ERROR),
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| 274 | [XHCI_TRBC_MAX] = NULL
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| 275 | #undef TRBC
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| 276 | };
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| 277 |
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[eb928c4] | 278 | /**
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| 279 | * Report an error according to command completion code.
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| 280 | */
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[4fa5342] | 281 | static void report_error(int code)
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| 282 | {
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| 283 | if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
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| 284 | usb_log_error("Command resulted in error: %s.", trb_codes[code]);
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| 285 | else
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| 286 | usb_log_error("Command resulted in reserved or vendor specific error.");
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| 287 | }
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| 288 |
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[eb928c4] | 289 | /**
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| 290 | * Handle a command completion. Feed the fibril waiting for result.
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| 291 | *
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| 292 | * @param trb The COMMAND_COMPLETION TRB found in event ring.
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| 293 | */
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[c3d926f3] | 294 | int xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
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[c9c0e41] | 295 | {
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[889146e] | 296 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[c3d926f3] | 297 | assert(trb);
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| 298 |
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| 299 | usb_log_debug2("HC(%p) Command completed.", hc);
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| 300 |
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[889146e] | 301 | fibril_mutex_lock(&cr->guard);
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| 302 |
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| 303 | int code = TRB_GET_CODE(*trb);
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| 304 | const uint64_t phys = TRB_GET_PHYS(*trb);
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[c3d926f3] | 305 |
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[889146e] | 306 | xhci_trb_ring_update_dequeue(&cr->trb_ring, phys);
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| 307 |
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| 308 | if (code == XHCI_TRBC_COMMAND_RING_STOPPED) {
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| 309 | /* This can either mean that the ring is being stopped, or
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| 310 | * a command was aborted. In either way, wake threads waiting
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| 311 | * on stopped_cv.
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| 312 | *
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| 313 | * Note that we need to hold mutex, because we must be sure the
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| 314 | * requesting thread is waiting inside the CV.
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| 315 | */
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| 316 | fibril_condvar_broadcast(&cr->stopped_cv);
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| 317 | fibril_mutex_unlock(&cr->guard);
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| 318 | return EOK;
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| 319 | }
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| 320 |
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| 321 | xhci_cmd_t *command = find_command(hc, phys);
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[c3d926f3] | 322 | if (command == NULL) {
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[889146e] | 323 | usb_log_error("No command struct for this completion event found.");
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[c3d926f3] | 324 |
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| 325 | if (code != XHCI_TRBC_SUCCESS)
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| 326 | report_error(code);
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| 327 |
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| 328 | return EOK;
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| 329 | }
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[c058a388] | 330 |
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[889146e] | 331 | list_remove(&command->_header.link);
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| 332 |
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[3cbc138] | 333 | /* Semantics of NO_OP_CMD is that success is marked as a TRB error. */
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| 334 | if (command->_header.cmd == XHCI_CMD_NO_OP && code == XHCI_TRBC_TRB_ERROR)
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| 335 | code = XHCI_TRBC_SUCCESS;
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| 336 |
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[c3d926f3] | 337 | command->status = code;
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| 338 | command->slot_id = TRB_GET_SLOT(*trb);
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[c9c0e41] | 339 |
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[c3d926f3] | 340 | usb_log_debug2("Completed command trb: %s", xhci_trb_str_type(TRB_TYPE(command->_header.trb)));
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[3cbc138] | 341 |
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| 342 | if (code != XHCI_TRBC_SUCCESS) {
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| 343 | report_error(code);
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| 344 | xhci_dump_trb(&command->_header.trb);
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[c3d926f3] | 345 | }
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| 346 |
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| 347 | switch (TRB_TYPE(command->_header.trb)) {
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| 348 | case XHCI_TRB_TYPE_NO_OP_CMD:
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| 349 | case XHCI_TRB_TYPE_ENABLE_SLOT_CMD:
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| 350 | case XHCI_TRB_TYPE_DISABLE_SLOT_CMD:
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| 351 | case XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD:
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| 352 | case XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD:
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| 353 | case XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD:
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| 354 | case XHCI_TRB_TYPE_RESET_ENDPOINT_CMD:
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| 355 | break;
|
---|
| 356 | case XHCI_TRB_TYPE_STOP_ENDPOINT_CMD:
|
---|
| 357 | // Note: If the endpoint was in the middle of a transfer, then the xHC
|
---|
| 358 | // will add a Transfer TRB before the Event TRB, research that and
|
---|
| 359 | // handle it appropriately!
|
---|
| 360 | break;
|
---|
| 361 | case XHCI_TRB_TYPE_RESET_DEVICE_CMD:
|
---|
| 362 | break;
|
---|
| 363 | default:
|
---|
| 364 | usb_log_debug2("Unsupported command trb: %s", xhci_trb_str_type(TRB_TYPE(command->_header.trb)));
|
---|
| 365 | return ENAK;
|
---|
| 366 | }
|
---|
| 367 |
|
---|
[889146e] | 368 | fibril_mutex_unlock(&cr->guard);
|
---|
| 369 |
|
---|
[c3d926f3] | 370 | fibril_mutex_lock(&command->_header.completed_mtx);
|
---|
| 371 | command->_header.completed = true;
|
---|
| 372 | fibril_condvar_broadcast(&command->_header.completed_cv);
|
---|
| 373 | fibril_mutex_unlock(&command->_header.completed_mtx);
|
---|
| 374 |
|
---|
| 375 | if (command->_header.async) {
|
---|
| 376 | /* Free the command and other DS upon completion. */
|
---|
| 377 | xhci_cmd_fini(command);
|
---|
| 378 | }
|
---|
| 379 |
|
---|
| 380 | return EOK;
|
---|
| 381 | }
|
---|
| 382 |
|
---|
| 383 | /* Command-issuing functions */
|
---|
| 384 |
|
---|
| 385 | static int no_op_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
| 386 | {
|
---|
| 387 | assert(hc);
|
---|
| 388 |
|
---|
| 389 | xhci_trb_clean(&cmd->_header.trb);
|
---|
| 390 |
|
---|
| 391 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_NO_OP_CMD);
|
---|
[110d795] | 392 |
|
---|
[eb928c4] | 393 | return enqueue_command(hc, cmd);
|
---|
[c9c0e41] | 394 | }
|
---|
| 395 |
|
---|
[c3d926f3] | 396 | static int enable_slot_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c9c0e41] | 397 | {
|
---|
[c058a388] | 398 | assert(hc);
|
---|
| 399 |
|
---|
[c3d926f3] | 400 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c9c0e41] | 401 |
|
---|
[c3d926f3] | 402 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
|
---|
| 403 | cmd->_header.trb.control |= host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
|
---|
[110d795] | 404 |
|
---|
[eb928c4] | 405 | return enqueue_command(hc, cmd);
|
---|
[5ac5eb1] | 406 | }
|
---|
| 407 |
|
---|
[c3d926f3] | 408 | static int disable_slot_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[5ac5eb1] | 409 | {
|
---|
[c058a388] | 410 | assert(hc);
|
---|
[110d795] | 411 | assert(cmd);
|
---|
[c058a388] | 412 |
|
---|
[c3d926f3] | 413 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[5ac5eb1] | 414 |
|
---|
[c3d926f3] | 415 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
|
---|
| 416 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[110d795] | 417 |
|
---|
[eb928c4] | 418 | return enqueue_command(hc, cmd);
|
---|
[c9c0e41] | 419 | }
|
---|
| 420 |
|
---|
[c3d926f3] | 421 | static int address_device_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[8db42f7] | 422 | {
|
---|
[c058a388] | 423 | assert(hc);
|
---|
[110d795] | 424 | assert(cmd);
|
---|
[b80c1ab] | 425 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[c058a388] | 426 |
|
---|
[8db42f7] | 427 | /**
|
---|
| 428 | * TODO: Requirements for this command:
|
---|
| 429 | * dcbaa[slot_id] is properly sized and initialized
|
---|
| 430 | * ictx has valids slot context and endpoint 0, all
|
---|
| 431 | * other should be ignored at this point (see section 4.6.5).
|
---|
| 432 | */
|
---|
[04df063] | 433 |
|
---|
[c3d926f3] | 434 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[8db42f7] | 435 |
|
---|
[b80c1ab] | 436 | TRB_SET_ICTX(cmd->_header.trb, cmd->input_ctx.phys);
|
---|
[8db42f7] | 437 |
|
---|
| 438 | /**
|
---|
| 439 | * Note: According to section 6.4.3.4, we can set the 9th bit
|
---|
| 440 | * of the control field of the trb (BSR) to 1 and then the xHC
|
---|
| 441 | * will not issue the SET_ADDRESS request to the USB device.
|
---|
| 442 | * This can be used to provide compatibility with legacy USB devices
|
---|
| 443 | * that require their device descriptor to be read before such request.
|
---|
| 444 | */
|
---|
[c3d926f3] | 445 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
|
---|
| 446 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[8db42f7] | 447 |
|
---|
[eb928c4] | 448 | return enqueue_command(hc, cmd);
|
---|
[8db42f7] | 449 | }
|
---|
| 450 |
|
---|
[c3d926f3] | 451 | static int configure_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[665bf3c] | 452 | {
|
---|
[c058a388] | 453 | assert(hc);
|
---|
[110d795] | 454 | assert(cmd);
|
---|
[c058a388] | 455 |
|
---|
[c3d926f3] | 456 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[665bf3c] | 457 |
|
---|
[b724494] | 458 | if (!cmd->deconfigure) {
|
---|
| 459 | /* If the DC flag is on, input context is not evaluated. */
|
---|
[b80c1ab] | 460 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[b724494] | 461 |
|
---|
[b80c1ab] | 462 | TRB_SET_ICTX(cmd->_header.trb, cmd->input_ctx.phys);
|
---|
[b724494] | 463 | }
|
---|
[110d795] | 464 |
|
---|
[c3d926f3] | 465 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
|
---|
| 466 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 467 | TRB_SET_DC(cmd->_header.trb, cmd->deconfigure);
|
---|
[665bf3c] | 468 |
|
---|
[eb928c4] | 469 | return enqueue_command(hc, cmd);
|
---|
[665bf3c] | 470 | }
|
---|
| 471 |
|
---|
[c3d926f3] | 472 | static int evaluate_context_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c9ce62ae] | 473 | {
|
---|
[c058a388] | 474 | assert(hc);
|
---|
[110d795] | 475 | assert(cmd);
|
---|
[b80c1ab] | 476 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[c058a388] | 477 |
|
---|
[c9ce62ae] | 478 | /**
|
---|
| 479 | * Note: All Drop Context flags of the input context shall be 0,
|
---|
| 480 | * all Add Context flags shall be initialize to indicate IDs
|
---|
| 481 | * of the contexts affected by the command.
|
---|
| 482 | * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
|
---|
| 483 | */
|
---|
[c3d926f3] | 484 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c9ce62ae] | 485 |
|
---|
[b80c1ab] | 486 | TRB_SET_ICTX(cmd->_header.trb, cmd->input_ctx.phys);
|
---|
[c9ce62ae] | 487 |
|
---|
[c3d926f3] | 488 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
|
---|
| 489 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[110d795] | 490 |
|
---|
[eb928c4] | 491 | return enqueue_command(hc, cmd);
|
---|
[c9ce62ae] | 492 | }
|
---|
| 493 |
|
---|
[c3d926f3] | 494 | static int reset_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[05aeee0e] | 495 | {
|
---|
[c058a388] | 496 | assert(hc);
|
---|
[110d795] | 497 | assert(cmd);
|
---|
[c058a388] | 498 |
|
---|
[05aeee0e] | 499 | /**
|
---|
| 500 | * Note: TCS can have values 0 or 1. If it is set to 0, see sectuon 4.5.8 for
|
---|
| 501 | * information about this flag.
|
---|
| 502 | */
|
---|
[c3d926f3] | 503 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[05aeee0e] | 504 |
|
---|
[c3d926f3] | 505 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
|
---|
| 506 | TRB_SET_TCS(cmd->_header.trb, cmd->tcs);
|
---|
| 507 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 508 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[c9bec1c] | 509 |
|
---|
[eb928c4] | 510 | return enqueue_command(hc, cmd);
|
---|
[05aeee0e] | 511 | }
|
---|
| 512 |
|
---|
[c3d926f3] | 513 | static int stop_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[05aeee0e] | 514 | {
|
---|
[c058a388] | 515 | assert(hc);
|
---|
[110d795] | 516 | assert(cmd);
|
---|
[c058a388] | 517 |
|
---|
[c3d926f3] | 518 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[110d795] | 519 |
|
---|
[c3d926f3] | 520 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
|
---|
| 521 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 522 | TRB_SET_SUSP(cmd->_header.trb, cmd->susp);
|
---|
| 523 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[05aeee0e] | 524 |
|
---|
[eb928c4] | 525 | return enqueue_command(hc, cmd);
|
---|
[c058a388] | 526 | }
|
---|
[05aeee0e] | 527 |
|
---|
[c3d926f3] | 528 | static int set_tr_dequeue_pointer_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[0cabd10] | 529 | {
|
---|
| 530 | assert(hc);
|
---|
| 531 | assert(cmd);
|
---|
| 532 |
|
---|
[c3d926f3] | 533 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[0cabd10] | 534 |
|
---|
[c3d926f3] | 535 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
|
---|
| 536 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 537 | TRB_SET_STREAM(cmd->_header.trb, cmd->stream_id);
|
---|
| 538 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 539 | TRB_SET_DEQUEUE_PTR(cmd->_header.trb, cmd->dequeue_ptr);
|
---|
[0cabd10] | 540 |
|
---|
| 541 | /**
|
---|
| 542 | * TODO: Set DCS (see section 4.6.10).
|
---|
| 543 | */
|
---|
| 544 |
|
---|
[eb928c4] | 545 | return enqueue_command(hc, cmd);
|
---|
[0cabd10] | 546 | }
|
---|
| 547 |
|
---|
[c3d926f3] | 548 | static int reset_device_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c058a388] | 549 | {
|
---|
| 550 | assert(hc);
|
---|
[110d795] | 551 | assert(cmd);
|
---|
[c058a388] | 552 |
|
---|
[c3d926f3] | 553 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c058a388] | 554 |
|
---|
[c3d926f3] | 555 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
|
---|
| 556 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[c9bec1c] | 557 |
|
---|
[eb928c4] | 558 | return enqueue_command(hc, cmd);
|
---|
[05aeee0e] | 559 | }
|
---|
| 560 |
|
---|
[c3d926f3] | 561 | static int get_port_bandwidth_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[60af4cdb] | 562 | {
|
---|
| 563 | assert(hc);
|
---|
| 564 | assert(cmd);
|
---|
| 565 |
|
---|
[c3d926f3] | 566 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[60af4cdb] | 567 |
|
---|
[b80c1ab] | 568 | TRB_SET_ICTX(cmd->_header.trb, cmd->bandwidth_ctx.phys);
|
---|
[60af4cdb] | 569 |
|
---|
[c3d926f3] | 570 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
|
---|
| 571 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 572 | TRB_SET_DEV_SPEED(cmd->_header.trb, cmd->device_speed);
|
---|
[60af4cdb] | 573 |
|
---|
[eb928c4] | 574 | return enqueue_command(hc, cmd);
|
---|
[60af4cdb] | 575 | }
|
---|
| 576 |
|
---|
[c3d926f3] | 577 | /* The table of command-issuing functions. */
|
---|
| 578 |
|
---|
| 579 | typedef int (*cmd_handler) (xhci_hc_t *hc, xhci_cmd_t *cmd);
|
---|
| 580 |
|
---|
| 581 | static cmd_handler cmd_handlers [] = {
|
---|
| 582 | [XHCI_CMD_ENABLE_SLOT] = enable_slot_cmd,
|
---|
| 583 | [XHCI_CMD_DISABLE_SLOT] = disable_slot_cmd,
|
---|
| 584 | [XHCI_CMD_ADDRESS_DEVICE] = address_device_cmd,
|
---|
| 585 | [XHCI_CMD_CONFIGURE_ENDPOINT] = configure_endpoint_cmd,
|
---|
| 586 | [XHCI_CMD_EVALUATE_CONTEXT] = evaluate_context_cmd,
|
---|
| 587 | [XHCI_CMD_RESET_ENDPOINT] = reset_endpoint_cmd,
|
---|
| 588 | [XHCI_CMD_STOP_ENDPOINT] = stop_endpoint_cmd,
|
---|
| 589 | [XHCI_CMD_SET_TR_DEQUEUE_POINTER] = set_tr_dequeue_pointer_cmd,
|
---|
| 590 | [XHCI_CMD_RESET_DEVICE] = reset_device_cmd,
|
---|
| 591 | [XHCI_CMD_FORCE_EVENT] = NULL,
|
---|
| 592 | [XHCI_CMD_NEGOTIATE_BANDWIDTH] = NULL,
|
---|
| 593 | [XHCI_CMD_SET_LATENCY_TOLERANCE_VALUE] = NULL,
|
---|
| 594 | [XHCI_CMD_GET_PORT_BANDWIDTH] = get_port_bandwidth_cmd,
|
---|
| 595 | [XHCI_CMD_FORCE_HEADER] = NULL,
|
---|
| 596 | [XHCI_CMD_NO_OP] = no_op_cmd
|
---|
| 597 | };
|
---|
| 598 |
|
---|
[eb928c4] | 599 | /**
|
---|
| 600 | * Try to abort currently processed command. This is tricky, because
|
---|
| 601 | * calling fibril is not necessarily the one which issued the blocked command.
|
---|
| 602 | * Also, the trickiness intensifies by the fact that stopping a CR is denoted by
|
---|
| 603 | * event, which is again handled in different fibril. but, once we go to sleep
|
---|
| 604 | * on waiting for that event, another fibril may wake up and try to abort the
|
---|
| 605 | * blocked command.
|
---|
| 606 | *
|
---|
| 607 | * So, we mark the command ring as being restarted, wait for it to stop, and
|
---|
| 608 | * then start it again. If there was a blocked command, it will be satisfied by
|
---|
| 609 | * COMMAND_ABORTED event.
|
---|
| 610 | */
|
---|
[889146e] | 611 | static int try_abort_current_command(xhci_hc_t *hc)
|
---|
| 612 | {
|
---|
| 613 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
|
---|
| 614 |
|
---|
| 615 | fibril_mutex_lock(&cr->guard);
|
---|
| 616 |
|
---|
| 617 | if (cr->state != XHCI_CR_STATE_OPEN) {
|
---|
| 618 | // The CR is either stopped, or different fibril is already
|
---|
| 619 | // restarting it.
|
---|
| 620 | fibril_mutex_unlock(&cr->guard);
|
---|
| 621 | return EOK;
|
---|
| 622 | }
|
---|
| 623 |
|
---|
| 624 | usb_log_error("HC(%p): Timeout while waiting for command: aborting current command.", hc);
|
---|
| 625 |
|
---|
| 626 | cr->state = XHCI_CR_STATE_CHANGING;
|
---|
| 627 | fibril_condvar_broadcast(&cr->state_cv);
|
---|
| 628 |
|
---|
| 629 | abort_command_ring(hc);
|
---|
| 630 |
|
---|
| 631 | fibril_condvar_wait_timeout(&cr->stopped_cv, &cr->guard, XHCI_CR_ABORT_TIMEOUT);
|
---|
| 632 |
|
---|
| 633 | if (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR)) {
|
---|
| 634 | /* 4.6.1.2, implementation note
|
---|
| 635 | * Assume there are larger problems with HC and
|
---|
| 636 | * reset it.
|
---|
| 637 | */
|
---|
| 638 | usb_log_error("HC(%p): Command didn't abort.", hc);
|
---|
| 639 |
|
---|
| 640 | cr->state = XHCI_CR_STATE_CLOSED;
|
---|
| 641 | fibril_condvar_broadcast(&cr->state_cv);
|
---|
| 642 |
|
---|
| 643 | // TODO: Reset HC completely.
|
---|
| 644 | // Don't forget to somehow complete all commands with error.
|
---|
| 645 |
|
---|
| 646 | fibril_mutex_unlock(&cr->guard);
|
---|
| 647 | return ENAK;
|
---|
| 648 | }
|
---|
| 649 |
|
---|
| 650 | usb_log_error("HC(%p): Command ring stopped. Starting again.", hc);
|
---|
| 651 | hc_ring_doorbell(hc, 0, 0);
|
---|
| 652 |
|
---|
| 653 | cr->state = XHCI_CR_STATE_OPEN;
|
---|
| 654 | fibril_condvar_broadcast(&cr->state_cv);
|
---|
| 655 |
|
---|
| 656 | fibril_mutex_unlock(&cr->guard);
|
---|
| 657 | return EOK;
|
---|
| 658 | }
|
---|
| 659 |
|
---|
[eb928c4] | 660 | /**
|
---|
| 661 | * Wait, until the command is completed. The completion is triggered by
|
---|
| 662 | * COMMAND_COMPLETION event. As we do not want to rely on HW completing the
|
---|
| 663 | * command in timely manner, we timeout. Note that we can't just return an
|
---|
| 664 | * error after the timeout pass - it may be other command blocking the ring,
|
---|
| 665 | * and ours can be completed afterwards. Therefore, it is not guaranteed that
|
---|
| 666 | * this function will return in XHCI_COMMAND_TIMEOUT. It will continue waiting
|
---|
| 667 | * until COMMAND_COMPLETION event arrives.
|
---|
| 668 | */
|
---|
[889146e] | 669 | static int wait_for_cmd_completion(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[f9e7fe8] | 670 | {
|
---|
[c3d926f3] | 671 | int rv = EOK;
|
---|
[c058a388] | 672 |
|
---|
[c3d926f3] | 673 | fibril_mutex_lock(&cmd->_header.completed_mtx);
|
---|
| 674 | while (!cmd->_header.completed) {
|
---|
[f9e7fe8] | 675 |
|
---|
[889146e] | 676 | rv = fibril_condvar_wait_timeout(&cmd->_header.completed_cv, &cmd->_header.completed_mtx, XHCI_COMMAND_TIMEOUT);
|
---|
| 677 |
|
---|
| 678 | /* The waiting timed out. Current command (not necessarily
|
---|
| 679 | * ours) is probably blocked.
|
---|
| 680 | */
|
---|
| 681 | if (!cmd->_header.completed && rv == ETIMEOUT) {
|
---|
| 682 | fibril_mutex_unlock(&cmd->_header.completed_mtx);
|
---|
| 683 |
|
---|
| 684 | rv = try_abort_current_command(hc);
|
---|
| 685 | if (rv)
|
---|
| 686 | return rv;
|
---|
| 687 |
|
---|
| 688 | fibril_mutex_lock(&cmd->_header.completed_mtx);
|
---|
[c3d926f3] | 689 | }
|
---|
| 690 | }
|
---|
| 691 | fibril_mutex_unlock(&cmd->_header.completed_mtx);
|
---|
[f711f06] | 692 |
|
---|
[c3d926f3] | 693 | return rv;
|
---|
| 694 | }
|
---|
[2fa43d1] | 695 |
|
---|
[eb928c4] | 696 | /**
|
---|
| 697 | * Issue command and block the current fibril until it is completed or timeout
|
---|
| 698 | * expires. Nothing is deallocated. Caller should always execute `xhci_cmd_fini`.
|
---|
[c3d926f3] | 699 | */
|
---|
| 700 | int xhci_cmd_sync(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
| 701 | {
|
---|
| 702 | assert(hc);
|
---|
| 703 | assert(cmd);
|
---|
[2fa43d1] | 704 |
|
---|
[c3d926f3] | 705 | int err;
|
---|
| 706 |
|
---|
| 707 | if (!cmd_handlers[cmd->_header.cmd]) {
|
---|
| 708 | /* Handler not implemented. */
|
---|
| 709 | return ENOTSUP;
|
---|
[2fa43d1] | 710 | }
|
---|
[110d795] | 711 |
|
---|
[c3d926f3] | 712 | if ((err = cmd_handlers[cmd->_header.cmd](hc, cmd))) {
|
---|
| 713 | /* Command could not be issued. */
|
---|
| 714 | return err;
|
---|
| 715 | }
|
---|
[110d795] | 716 |
|
---|
[889146e] | 717 | if ((err = wait_for_cmd_completion(hc, cmd))) {
|
---|
| 718 | /* Command failed. */
|
---|
[c3d926f3] | 719 | return err;
|
---|
[665bf3c] | 720 | }
|
---|
[c362127] | 721 |
|
---|
[3cbc138] | 722 | return cmd->status == XHCI_TRBC_SUCCESS ? EOK : EINVAL;
|
---|
[c3d926f3] | 723 | }
|
---|
[110d795] | 724 |
|
---|
[eb928c4] | 725 | /**
|
---|
| 726 | * Does the same thing as `xhci_cmd_sync` and executes `xhci_cmd_fini`. This
|
---|
| 727 | * is a useful shorthand for issuing commands without out parameters.
|
---|
[c3d926f3] | 728 | */
|
---|
| 729 | int xhci_cmd_sync_fini(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
| 730 | {
|
---|
| 731 | const int err = xhci_cmd_sync(hc, cmd);
|
---|
| 732 | xhci_cmd_fini(cmd);
|
---|
| 733 |
|
---|
| 734 | return err;
|
---|
| 735 | }
|
---|
| 736 |
|
---|
[eb928c4] | 737 | /**
|
---|
| 738 | * Does the same thing as `xhci_cmd_sync_fini` without blocking the current
|
---|
| 739 | * fibril. The command is copied to stack memory and `fini` is called upon its completion.
|
---|
[c3d926f3] | 740 | */
|
---|
| 741 | int xhci_cmd_async_fini(xhci_hc_t *hc, xhci_cmd_t *stack_cmd)
|
---|
| 742 | {
|
---|
| 743 | assert(hc);
|
---|
| 744 | assert(stack_cmd);
|
---|
| 745 |
|
---|
| 746 | /* Save the command for later. */
|
---|
| 747 | xhci_cmd_t *heap_cmd = (xhci_cmd_t *) malloc(sizeof(xhci_cmd_t));
|
---|
| 748 | if (!heap_cmd) {
|
---|
| 749 | return ENOMEM;
|
---|
| 750 | }
|
---|
| 751 |
|
---|
| 752 | /* TODO: Is this good for the mutex and the condvar? */
|
---|
| 753 | memcpy(heap_cmd, stack_cmd, sizeof(xhci_cmd_t));
|
---|
| 754 | heap_cmd->_header.async = true;
|
---|
| 755 |
|
---|
| 756 | /* Issue the command. */
|
---|
| 757 | int err;
|
---|
| 758 |
|
---|
| 759 | if (!cmd_handlers[heap_cmd->_header.cmd]) {
|
---|
| 760 | /* Handler not implemented. */
|
---|
| 761 | err = ENOTSUP;
|
---|
| 762 | goto err_heap_cmd;
|
---|
[f711f06] | 763 | }
|
---|
[110d795] | 764 |
|
---|
[c3d926f3] | 765 | if ((err = cmd_handlers[heap_cmd->_header.cmd](hc, heap_cmd))) {
|
---|
| 766 | /* Command could not be issued. */
|
---|
| 767 | goto err_heap_cmd;
|
---|
| 768 | }
|
---|
[4688350b] | 769 |
|
---|
[110d795] | 770 | return EOK;
|
---|
[c9c0e41] | 771 |
|
---|
[c3d926f3] | 772 | err_heap_cmd:
|
---|
| 773 | free(heap_cmd);
|
---|
| 774 | return err;
|
---|
| 775 | }
|
---|
[c9c0e41] | 776 |
|
---|
| 777 | /**
|
---|
| 778 | * @}
|
---|
| 779 | */
|
---|