[c9c0e41] | 1 | /*
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[e0a5d4c] | 2 | * Copyright (c) 2018 Jaroslav Jindrak, Ondrej Hlavaty, Petr Manek, Michal Staruch, Jan Hrach
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[c9c0e41] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Command sending functions.
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| 34 | */
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| 35 |
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| 36 | #include <errno.h>
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| 37 | #include <str_error.h>
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| 38 | #include <usb/debug.h>
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| 39 | #include "commands.h"
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| 40 | #include "debug.h"
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| 41 | #include "hc.h"
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[8db42f7] | 42 | #include "hw_struct/context.h"
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[c9c0e41] | 43 | #include "hw_struct/trb.h"
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| 44 |
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[e7f21884] | 45 | #define TRB_SET_TSP(trb, tsp) (trb).control |= host2xhci(32, (((tsp) & 0x1) << 9))
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[1b78a7c1] | 46 | #define TRB_SET_TYPE(trb, type) (trb).control |= host2xhci(32, (type) << 10)
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[b724494] | 47 | #define TRB_SET_DC(trb, dc) (trb).control |= host2xhci(32, (dc) << 9)
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[1b78a7c1] | 48 | #define TRB_SET_EP(trb, ep) (trb).control |= host2xhci(32, ((ep) & 0x5) << 16)
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[0cabd10] | 49 | #define TRB_SET_STREAM(trb, st) (trb).control |= host2xhci(32, ((st) & 0xFFFF) << 16)
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[1b78a7c1] | 50 | #define TRB_SET_SUSP(trb, susp) (trb).control |= host2xhci(32, ((susp) & 0x1) << 23)
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| 51 | #define TRB_SET_SLOT(trb, slot) (trb).control |= host2xhci(32, (slot) << 24)
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[60af4cdb] | 52 | #define TRB_SET_DEV_SPEED(trb, speed) (trb).control |= host2xhci(32, (speed & 0xF) << 16)
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[0cabd10] | 53 | #define TRB_SET_DEQUEUE_PTR(trb, dptr) (trb).parameter |= host2xhci(64, (dptr))
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[b80c1ab] | 54 | #define TRB_SET_ICTX(trb, phys) (trb).parameter |= host2xhci(64, (phys) & (~0xF))
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[1b78a7c1] | 55 |
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| 56 | #define TRB_GET_CODE(trb) XHCI_DWORD_EXTRACT((trb).status, 31, 24)
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| 57 | #define TRB_GET_SLOT(trb) XHCI_DWORD_EXTRACT((trb).control, 31, 24)
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| 58 | #define TRB_GET_PHYS(trb) (XHCI_QWORD_EXTRACT((trb).parameter, 63, 4) << 4)
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| 59 |
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[c3d926f3] | 60 | /* Control functions */
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| 61 |
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[889146e] | 62 | static xhci_cmd_ring_t *get_cmd_ring(xhci_hc_t *hc)
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[110d795] | 63 | {
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| 64 | assert(hc);
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[889146e] | 65 | return &hc->cr;
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| 66 | }
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| 67 |
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[eb928c4] | 68 | /**
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| 69 | * Initialize the command subsystem. Allocates the comand ring.
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| 70 | *
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| 71 | * Does not configure the CR pointer to the hardware, because the xHC will be
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| 72 | * reset before starting.
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| 73 | */
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[45457265] | 74 | errno_t xhci_init_commands(xhci_hc_t *hc)
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[889146e] | 75 | {
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| 76 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[45457265] | 77 | errno_t err;
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[889146e] | 78 |
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[998773d] | 79 | if ((err = xhci_trb_ring_init(&cr->trb_ring, 0)))
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[889146e] | 80 | return err;
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[110d795] | 81 |
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[889146e] | 82 | fibril_mutex_initialize(&cr->guard);
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| 83 | fibril_condvar_initialize(&cr->state_cv);
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| 84 | fibril_condvar_initialize(&cr->stopped_cv);
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[74b852b] | 85 |
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[889146e] | 86 | list_initialize(&cr->cmd_list);
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| 87 |
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[110d795] | 88 | return EOK;
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| 89 | }
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| 90 |
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[eb928c4] | 91 | /**
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| 92 | * Finish the command subsystem. Stops the hardware from running commands, then
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| 93 | * deallocates the ring.
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| 94 | */
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[c46c356] | 95 | void xhci_fini_commands(xhci_hc_t *hc)
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| 96 | {
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| 97 | assert(hc);
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[eb928c4] | 98 | xhci_stop_command_ring(hc);
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| 99 |
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| 100 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 101 |
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| 102 | fibril_mutex_lock(&cr->guard);
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| 103 | xhci_trb_ring_fini(&cr->trb_ring);
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| 104 | fibril_mutex_unlock(&cr->guard);
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[c46c356] | 105 | }
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| 106 |
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[eb928c4] | 107 | /**
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| 108 | * Initialize a command structure for the given command.
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| 109 | */
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[c3d926f3] | 110 | void xhci_cmd_init(xhci_cmd_t *cmd, xhci_cmd_type_t type)
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[110d795] | 111 | {
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[c3d926f3] | 112 | memset(cmd, 0, sizeof(*cmd));
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[110d795] | 113 |
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[c3d926f3] | 114 | link_initialize(&cmd->_header.link);
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[110d795] | 115 |
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[c3d926f3] | 116 | fibril_mutex_initialize(&cmd->_header.completed_mtx);
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| 117 | fibril_condvar_initialize(&cmd->_header.completed_cv);
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[04df063] | 118 |
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[c3d926f3] | 119 | cmd->_header.cmd = type;
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[4688350b] | 120 | }
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| 121 |
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[eb928c4] | 122 | /**
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| 123 | * Finish the command structure. Some command invocation includes allocating
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| 124 | * a context structure. To have the convenience in calling commands, this
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| 125 | * method deallocates all resources.
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| 126 | */
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[c3d926f3] | 127 | void xhci_cmd_fini(xhci_cmd_t *cmd)
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[4688350b] | 128 | {
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[c3d926f3] | 129 | list_remove(&cmd->_header.link);
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[110d795] | 130 |
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[b80c1ab] | 131 | dma_buffer_free(&cmd->input_ctx);
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| 132 | dma_buffer_free(&cmd->bandwidth_ctx);
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[9304b66] | 133 |
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[c3d926f3] | 134 | if (cmd->_header.async) {
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| 135 | free(cmd);
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| 136 | }
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[110d795] | 137 | }
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| 138 |
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[eb928c4] | 139 | /**
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| 140 | * Find a command issued by TRB at @c phys inside the command list.
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| 141 | *
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| 142 | * Call with guard locked only.
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| 143 | */
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[889146e] | 144 | static inline xhci_cmd_t *find_command(xhci_hc_t *hc, uint64_t phys)
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[110d795] | 145 | {
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[889146e] | 146 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 147 | assert(fibril_mutex_is_locked(&cr->guard));
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[74b852b] | 148 |
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[889146e] | 149 | link_t *cmd_link = list_first(&cr->cmd_list);
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[110d795] | 150 |
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[2fa43d1] | 151 | while (cmd_link != NULL) {
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[ae3a941] | 152 | xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t,
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| 153 | _header.link);
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[2fa43d1] | 154 |
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[c3d926f3] | 155 | if (cmd->_header.trb_phys == phys)
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[2fa43d1] | 156 | break;
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| 157 |
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[889146e] | 158 | cmd_link = list_next(cmd_link, &cr->cmd_list);
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[2fa43d1] | 159 | }
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| 160 |
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[3bacee1] | 161 | return cmd_link ?
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| 162 | list_get_instance(cmd_link, xhci_cmd_t, _header.link) :
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| 163 | NULL;
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[110d795] | 164 | }
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| 165 |
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[d2c3dcd] | 166 | static void cr_set_state(xhci_cmd_ring_t *cr, xhci_cr_state_t state)
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| 167 | {
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| 168 | assert(fibril_mutex_is_locked(&cr->guard));
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| 169 |
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| 170 | cr->state = state;
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[ae3a941] | 171 | if (state == XHCI_CR_STATE_OPEN || state == XHCI_CR_STATE_CLOSED)
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[d2c3dcd] | 172 | fibril_condvar_broadcast(&cr->state_cv);
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| 173 | }
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| 174 |
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[45457265] | 175 | static errno_t wait_for_ring_open(xhci_cmd_ring_t *cr)
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[d2c3dcd] | 176 | {
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| 177 | assert(fibril_mutex_is_locked(&cr->guard));
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| 178 |
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| 179 | while (true) {
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| 180 | switch (cr->state) {
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| 181 | case XHCI_CR_STATE_CHANGING:
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| 182 | case XHCI_CR_STATE_FULL:
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| 183 | fibril_condvar_wait(&cr->state_cv, &cr->guard);
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| 184 | break;
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| 185 | case XHCI_CR_STATE_OPEN:
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| 186 | return EOK;
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| 187 | case XHCI_CR_STATE_CLOSED:
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| 188 | return ENAK;
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| 189 | }
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| 190 | }
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| 191 | }
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| 192 |
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[eb928c4] | 193 | /**
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| 194 | * Enqueue a command on the TRB ring. Ring the doorbell to initiate processing.
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| 195 | * Register the command as waiting for completion inside the command list.
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| 196 | */
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[45457265] | 197 | static inline errno_t enqueue_command(xhci_hc_t *hc, xhci_cmd_t *cmd)
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[481af21e] | 198 | {
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[889146e] | 199 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[548c123] | 200 | assert(cmd);
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| 201 |
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[889146e] | 202 | fibril_mutex_lock(&cr->guard);
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[c058a388] | 203 |
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[d2c3dcd] | 204 | if (wait_for_ring_open(cr)) {
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[889146e] | 205 | fibril_mutex_unlock(&cr->guard);
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| 206 | return ENAK;
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| 207 | }
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| 208 |
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[ae3a941] | 209 | usb_log_debug("Sending command %s",
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| 210 | xhci_trb_str_type(TRB_TYPE(cmd->_header.trb)));
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[481af21e] | 211 |
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[889146e] | 212 | list_append(&cmd->_header.link, &cr->cmd_list);
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| 213 |
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[45457265] | 214 | errno_t err = EOK;
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[d2c3dcd] | 215 | while (err == EOK) {
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| 216 | err = xhci_trb_ring_enqueue(&cr->trb_ring,
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| 217 | &cmd->_header.trb, &cmd->_header.trb_phys);
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| 218 | if (err != EAGAIN)
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| 219 | break;
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| 220 |
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| 221 | cr_set_state(cr, XHCI_CR_STATE_FULL);
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| 222 | err = wait_for_ring_open(cr);
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| 223 | }
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| 224 |
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| 225 | if (err == EOK)
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| 226 | hc_ring_doorbell(hc, 0, 0);
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[889146e] | 227 |
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| 228 | fibril_mutex_unlock(&cr->guard);
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| 229 |
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[d2c3dcd] | 230 | return err;
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[481af21e] | 231 | }
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| 232 |
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[eb928c4] | 233 | /**
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| 234 | * Stop the command ring. Stop processing commands, block issuing new ones.
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| 235 | * Wait until hardware acknowledges it is stopped.
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| 236 | */
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[3dc519f] | 237 | void xhci_stop_command_ring(xhci_hc_t *hc)
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| 238 | {
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[889146e] | 239 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[3dc519f] | 240 |
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[889146e] | 241 | fibril_mutex_lock(&cr->guard);
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[3dc519f] | 242 |
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[889146e] | 243 | // Prevent others from starting CR again.
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[d2c3dcd] | 244 | cr_set_state(cr, XHCI_CR_STATE_CLOSED);
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[3dc519f] | 245 |
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[889146e] | 246 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
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[3dc519f] | 247 |
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[889146e] | 248 | while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR))
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| 249 | fibril_condvar_wait(&cr->stopped_cv, &cr->guard);
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| 250 |
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| 251 | fibril_mutex_unlock(&cr->guard);
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[3dc519f] | 252 | }
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| 253 |
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[19f0048] | 254 | /**
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| 255 | * Mark the command ring as stopped. NAK new commands, abort running, do not
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| 256 | * touch the HC as it's probably broken.
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| 257 | */
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| 258 | void xhci_nuke_command_ring(xhci_hc_t *hc)
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| 259 | {
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| 260 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 261 | fibril_mutex_lock(&cr->guard);
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| 262 | // Prevent others from starting CR again.
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| 263 | cr_set_state(cr, XHCI_CR_STATE_CLOSED);
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[c21e6a5] | 264 |
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| 265 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
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[19f0048] | 266 | fibril_mutex_unlock(&cr->guard);
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| 267 | }
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| 268 |
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| 269 | /**
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| 270 | * Mark the command ring as working again.
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| 271 | */
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| 272 | void xhci_start_command_ring(xhci_hc_t *hc)
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| 273 | {
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| 274 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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| 275 | fibril_mutex_lock(&cr->guard);
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| 276 | // Prevent others from starting CR again.
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| 277 | cr_set_state(cr, XHCI_CR_STATE_OPEN);
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| 278 | fibril_mutex_unlock(&cr->guard);
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| 279 | }
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| 280 |
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[eb928c4] | 281 | /**
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| 282 | * Abort currently processed command. Note that it is only aborted when the
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| 283 | * command is "blocking" - see section 4.6.1.2 of xHCI spec.
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| 284 | */
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[889146e] | 285 | static void abort_command_ring(xhci_hc_t *hc)
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[3dc519f] | 286 | {
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[8033f89] | 287 | XHCI_REG_SET(hc->op_regs, XHCI_OP_CA, 1);
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[3dc519f] | 288 | }
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| 289 |
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[4fa5342] | 290 | static const char *trb_codes [] = {
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| 291 | #define TRBC(t) [XHCI_TRBC_##t] = #t
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| 292 | TRBC(INVALID),
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| 293 | TRBC(SUCCESS),
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| 294 | TRBC(DATA_BUFFER_ERROR),
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| 295 | TRBC(BABBLE_DETECTED_ERROR),
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| 296 | TRBC(USB_TRANSACTION_ERROR),
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| 297 | TRBC(TRB_ERROR),
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| 298 | TRBC(STALL_ERROR),
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| 299 | TRBC(RESOURCE_ERROR),
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| 300 | TRBC(BANDWIDTH_ERROR),
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| 301 | TRBC(NO_SLOTS_ERROR),
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| 302 | TRBC(INVALID_STREAM_ERROR),
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| 303 | TRBC(SLOT_NOT_ENABLED_ERROR),
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| 304 | TRBC(EP_NOT_ENABLED_ERROR),
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| 305 | TRBC(SHORT_PACKET),
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| 306 | TRBC(RING_UNDERRUN),
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| 307 | TRBC(RING_OVERRUN),
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| 308 | TRBC(VF_EVENT_RING_FULL),
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| 309 | TRBC(PARAMETER_ERROR),
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| 310 | TRBC(BANDWIDTH_OVERRUN_ERROR),
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| 311 | TRBC(CONTEXT_STATE_ERROR),
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| 312 | TRBC(NO_PING_RESPONSE_ERROR),
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| 313 | TRBC(EVENT_RING_FULL_ERROR),
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| 314 | TRBC(INCOMPATIBLE_DEVICE_ERROR),
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| 315 | TRBC(MISSED_SERVICE_ERROR),
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| 316 | TRBC(COMMAND_RING_STOPPED),
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| 317 | TRBC(COMMAND_ABORTED),
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| 318 | TRBC(STOPPED),
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| 319 | TRBC(STOPPED_LENGTH_INVALID),
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| 320 | TRBC(STOPPED_SHORT_PACKET),
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| 321 | TRBC(MAX_EXIT_LATENCY_TOO_LARGE_ERROR),
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| 322 | [30] = "<reserved>",
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| 323 | TRBC(ISOCH_BUFFER_OVERRUN),
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| 324 | TRBC(EVENT_LOST_ERROR),
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| 325 | TRBC(UNDEFINED_ERROR),
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| 326 | TRBC(INVALID_STREAM_ID_ERROR),
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| 327 | TRBC(SECONDARY_BANDWIDTH_ERROR),
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| 328 | TRBC(SPLIT_TRANSACTION_ERROR),
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| 329 | [XHCI_TRBC_MAX] = NULL
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| 330 | #undef TRBC
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| 331 | };
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| 332 |
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[eb928c4] | 333 | /**
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| 334 | * Report an error according to command completion code.
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| 335 | */
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[4fa5342] | 336 | static void report_error(int code)
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| 337 | {
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| 338 | if (code < XHCI_TRBC_MAX && trb_codes[code] != NULL)
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| 339 | usb_log_error("Command resulted in error: %s.", trb_codes[code]);
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| 340 | else
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[ae3a941] | 341 | usb_log_error("Command resulted in reserved or "
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| 342 | "vendor specific error.");
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[4fa5342] | 343 | }
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| 344 |
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[eb928c4] | 345 | /**
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| 346 | * Handle a command completion. Feed the fibril waiting for result.
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| 347 | *
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| 348 | * @param trb The COMMAND_COMPLETION TRB found in event ring.
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| 349 | */
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[45457265] | 350 | errno_t xhci_handle_command_completion(xhci_hc_t *hc, xhci_trb_t *trb)
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[c9c0e41] | 351 | {
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[889146e] | 352 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
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[c3d926f3] | 353 | assert(trb);
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| 354 |
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[889146e] | 355 | fibril_mutex_lock(&cr->guard);
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| 356 |
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| 357 | int code = TRB_GET_CODE(*trb);
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| 358 |
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| 359 | if (code == XHCI_TRBC_COMMAND_RING_STOPPED) {
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[7c3fb9b] | 360 | /*
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| 361 | * This can either mean that the ring is being stopped, or
|
---|
[889146e] | 362 | * a command was aborted. In either way, wake threads waiting
|
---|
| 363 | * on stopped_cv.
|
---|
| 364 | *
|
---|
| 365 | * Note that we need to hold mutex, because we must be sure the
|
---|
| 366 | * requesting thread is waiting inside the CV.
|
---|
| 367 | */
|
---|
[defaab2] | 368 | usb_log_debug("Command ring stopped.");
|
---|
[889146e] | 369 | fibril_condvar_broadcast(&cr->stopped_cv);
|
---|
| 370 | fibril_mutex_unlock(&cr->guard);
|
---|
| 371 | return EOK;
|
---|
| 372 | }
|
---|
| 373 |
|
---|
[d2c3dcd] | 374 | const uint64_t phys = TRB_GET_PHYS(*trb);
|
---|
| 375 | xhci_trb_ring_update_dequeue(&cr->trb_ring, phys);
|
---|
| 376 |
|
---|
| 377 | if (cr->state == XHCI_CR_STATE_FULL)
|
---|
| 378 | cr_set_state(cr, XHCI_CR_STATE_OPEN);
|
---|
| 379 |
|
---|
[889146e] | 380 | xhci_cmd_t *command = find_command(hc, phys);
|
---|
[c3d926f3] | 381 | if (command == NULL) {
|
---|
[837581fd] | 382 | usb_log_error("No command struct for completion event found.");
|
---|
[c3d926f3] | 383 |
|
---|
| 384 | if (code != XHCI_TRBC_SUCCESS)
|
---|
| 385 | report_error(code);
|
---|
| 386 |
|
---|
| 387 | return EOK;
|
---|
| 388 | }
|
---|
[c058a388] | 389 |
|
---|
[889146e] | 390 | list_remove(&command->_header.link);
|
---|
| 391 |
|
---|
[3cbc138] | 392 | /* Semantics of NO_OP_CMD is that success is marked as a TRB error. */
|
---|
| 393 | if (command->_header.cmd == XHCI_CMD_NO_OP && code == XHCI_TRBC_TRB_ERROR)
|
---|
| 394 | code = XHCI_TRBC_SUCCESS;
|
---|
| 395 |
|
---|
[c3d926f3] | 396 | command->status = code;
|
---|
| 397 | command->slot_id = TRB_GET_SLOT(*trb);
|
---|
[c9c0e41] | 398 |
|
---|
[8033f89] | 399 | usb_log_debug("Completed command %s",
|
---|
| 400 | xhci_trb_str_type(TRB_TYPE(command->_header.trb)));
|
---|
[3cbc138] | 401 |
|
---|
| 402 | if (code != XHCI_TRBC_SUCCESS) {
|
---|
| 403 | report_error(code);
|
---|
| 404 | xhci_dump_trb(&command->_header.trb);
|
---|
[c3d926f3] | 405 | }
|
---|
| 406 |
|
---|
[889146e] | 407 | fibril_mutex_unlock(&cr->guard);
|
---|
| 408 |
|
---|
[c3d926f3] | 409 | fibril_mutex_lock(&command->_header.completed_mtx);
|
---|
| 410 | command->_header.completed = true;
|
---|
| 411 | fibril_condvar_broadcast(&command->_header.completed_cv);
|
---|
| 412 | fibril_mutex_unlock(&command->_header.completed_mtx);
|
---|
| 413 |
|
---|
| 414 | if (command->_header.async) {
|
---|
| 415 | /* Free the command and other DS upon completion. */
|
---|
| 416 | xhci_cmd_fini(command);
|
---|
| 417 | }
|
---|
| 418 |
|
---|
| 419 | return EOK;
|
---|
| 420 | }
|
---|
| 421 |
|
---|
| 422 | /* Command-issuing functions */
|
---|
| 423 |
|
---|
[45457265] | 424 | static errno_t no_op_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c3d926f3] | 425 | {
|
---|
| 426 | assert(hc);
|
---|
| 427 |
|
---|
| 428 | xhci_trb_clean(&cmd->_header.trb);
|
---|
| 429 |
|
---|
| 430 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_NO_OP_CMD);
|
---|
[110d795] | 431 |
|
---|
[eb928c4] | 432 | return enqueue_command(hc, cmd);
|
---|
[c9c0e41] | 433 | }
|
---|
| 434 |
|
---|
[45457265] | 435 | static errno_t enable_slot_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c9c0e41] | 436 | {
|
---|
[c058a388] | 437 | assert(hc);
|
---|
| 438 |
|
---|
[c3d926f3] | 439 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c9c0e41] | 440 |
|
---|
[c3d926f3] | 441 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_ENABLE_SLOT_CMD);
|
---|
[8033f89] | 442 | cmd->_header.trb.control |=
|
---|
| 443 | host2xhci(32, XHCI_REG_RD(hc->xecp, XHCI_EC_SP_SLOT_TYPE) << 16);
|
---|
[110d795] | 444 |
|
---|
[eb928c4] | 445 | return enqueue_command(hc, cmd);
|
---|
[5ac5eb1] | 446 | }
|
---|
| 447 |
|
---|
[45457265] | 448 | static errno_t disable_slot_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[5ac5eb1] | 449 | {
|
---|
[c058a388] | 450 | assert(hc);
|
---|
[110d795] | 451 | assert(cmd);
|
---|
[c058a388] | 452 |
|
---|
[c3d926f3] | 453 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[5ac5eb1] | 454 |
|
---|
[c3d926f3] | 455 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_DISABLE_SLOT_CMD);
|
---|
| 456 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[110d795] | 457 |
|
---|
[eb928c4] | 458 | return enqueue_command(hc, cmd);
|
---|
[c9c0e41] | 459 | }
|
---|
| 460 |
|
---|
[45457265] | 461 | static errno_t address_device_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[8db42f7] | 462 | {
|
---|
[c058a388] | 463 | assert(hc);
|
---|
[110d795] | 464 | assert(cmd);
|
---|
[b80c1ab] | 465 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[c058a388] | 466 |
|
---|
[8db42f7] | 467 | /**
|
---|
| 468 | * TODO: Requirements for this command:
|
---|
| 469 | * dcbaa[slot_id] is properly sized and initialized
|
---|
| 470 | * ictx has valids slot context and endpoint 0, all
|
---|
| 471 | * other should be ignored at this point (see section 4.6.5).
|
---|
| 472 | */
|
---|
[04df063] | 473 |
|
---|
[c3d926f3] | 474 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[8db42f7] | 475 |
|
---|
[1d758fc] | 476 | const uintptr_t phys = dma_buffer_phys_base(&cmd->input_ctx);
|
---|
| 477 | TRB_SET_ICTX(cmd->_header.trb, phys);
|
---|
[8db42f7] | 478 |
|
---|
| 479 | /**
|
---|
| 480 | * Note: According to section 6.4.3.4, we can set the 9th bit
|
---|
| 481 | * of the control field of the trb (BSR) to 1 and then the xHC
|
---|
| 482 | * will not issue the SET_ADDRESS request to the USB device.
|
---|
| 483 | * This can be used to provide compatibility with legacy USB devices
|
---|
| 484 | * that require their device descriptor to be read before such request.
|
---|
| 485 | */
|
---|
[c3d926f3] | 486 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD);
|
---|
| 487 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[8db42f7] | 488 |
|
---|
[eb928c4] | 489 | return enqueue_command(hc, cmd);
|
---|
[8db42f7] | 490 | }
|
---|
| 491 |
|
---|
[45457265] | 492 | static errno_t configure_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[665bf3c] | 493 | {
|
---|
[c058a388] | 494 | assert(hc);
|
---|
[110d795] | 495 | assert(cmd);
|
---|
[c058a388] | 496 |
|
---|
[c3d926f3] | 497 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[665bf3c] | 498 |
|
---|
[b724494] | 499 | if (!cmd->deconfigure) {
|
---|
| 500 | /* If the DC flag is on, input context is not evaluated. */
|
---|
[b80c1ab] | 501 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[b724494] | 502 |
|
---|
[1d758fc] | 503 | const uintptr_t phys = dma_buffer_phys_base(&cmd->input_ctx);
|
---|
| 504 | TRB_SET_ICTX(cmd->_header.trb, phys);
|
---|
[b724494] | 505 | }
|
---|
[110d795] | 506 |
|
---|
[c3d926f3] | 507 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_CONFIGURE_ENDPOINT_CMD);
|
---|
| 508 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 509 | TRB_SET_DC(cmd->_header.trb, cmd->deconfigure);
|
---|
[665bf3c] | 510 |
|
---|
[eb928c4] | 511 | return enqueue_command(hc, cmd);
|
---|
[665bf3c] | 512 | }
|
---|
| 513 |
|
---|
[45457265] | 514 | static errno_t evaluate_context_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c9ce62ae] | 515 | {
|
---|
[c058a388] | 516 | assert(hc);
|
---|
[110d795] | 517 | assert(cmd);
|
---|
[b80c1ab] | 518 | assert(dma_buffer_is_set(&cmd->input_ctx));
|
---|
[c058a388] | 519 |
|
---|
[c9ce62ae] | 520 | /**
|
---|
| 521 | * Note: All Drop Context flags of the input context shall be 0,
|
---|
| 522 | * all Add Context flags shall be initialize to indicate IDs
|
---|
| 523 | * of the contexts affected by the command.
|
---|
| 524 | * Refer to sections 6.2.2.3 and 6.3.3.3 for further info.
|
---|
| 525 | */
|
---|
[c3d926f3] | 526 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c9ce62ae] | 527 |
|
---|
[1d758fc] | 528 | const uintptr_t phys = dma_buffer_phys_base(&cmd->input_ctx);
|
---|
| 529 | TRB_SET_ICTX(cmd->_header.trb, phys);
|
---|
[c9ce62ae] | 530 |
|
---|
[c3d926f3] | 531 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_EVALUATE_CONTEXT_CMD);
|
---|
| 532 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[110d795] | 533 |
|
---|
[eb928c4] | 534 | return enqueue_command(hc, cmd);
|
---|
[c9ce62ae] | 535 | }
|
---|
| 536 |
|
---|
[45457265] | 537 | static errno_t reset_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[05aeee0e] | 538 | {
|
---|
[c058a388] | 539 | assert(hc);
|
---|
[110d795] | 540 | assert(cmd);
|
---|
[c058a388] | 541 |
|
---|
[c3d926f3] | 542 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[05aeee0e] | 543 |
|
---|
[c3d926f3] | 544 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_RESET_ENDPOINT_CMD);
|
---|
[e7f21884] | 545 | TRB_SET_TSP(cmd->_header.trb, cmd->tsp);
|
---|
[c3d926f3] | 546 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 547 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[c9bec1c] | 548 |
|
---|
[eb928c4] | 549 | return enqueue_command(hc, cmd);
|
---|
[05aeee0e] | 550 | }
|
---|
| 551 |
|
---|
[45457265] | 552 | static errno_t stop_endpoint_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[05aeee0e] | 553 | {
|
---|
[c058a388] | 554 | assert(hc);
|
---|
[110d795] | 555 | assert(cmd);
|
---|
[c058a388] | 556 |
|
---|
[c3d926f3] | 557 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[110d795] | 558 |
|
---|
[c3d926f3] | 559 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_STOP_ENDPOINT_CMD);
|
---|
| 560 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 561 | TRB_SET_SUSP(cmd->_header.trb, cmd->susp);
|
---|
| 562 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[05aeee0e] | 563 |
|
---|
[eb928c4] | 564 | return enqueue_command(hc, cmd);
|
---|
[c058a388] | 565 | }
|
---|
[05aeee0e] | 566 |
|
---|
[45457265] | 567 | static errno_t set_tr_dequeue_pointer_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[0cabd10] | 568 | {
|
---|
| 569 | assert(hc);
|
---|
| 570 | assert(cmd);
|
---|
| 571 |
|
---|
[c3d926f3] | 572 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[0cabd10] | 573 |
|
---|
[c3d926f3] | 574 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_SET_TR_DEQUEUE_POINTER_CMD);
|
---|
| 575 | TRB_SET_EP(cmd->_header.trb, cmd->endpoint_id);
|
---|
| 576 | TRB_SET_STREAM(cmd->_header.trb, cmd->stream_id);
|
---|
| 577 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 578 | TRB_SET_DEQUEUE_PTR(cmd->_header.trb, cmd->dequeue_ptr);
|
---|
[0cabd10] | 579 |
|
---|
[eb928c4] | 580 | return enqueue_command(hc, cmd);
|
---|
[0cabd10] | 581 | }
|
---|
| 582 |
|
---|
[45457265] | 583 | static errno_t reset_device_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c058a388] | 584 | {
|
---|
| 585 | assert(hc);
|
---|
[110d795] | 586 | assert(cmd);
|
---|
[c058a388] | 587 |
|
---|
[c3d926f3] | 588 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[c058a388] | 589 |
|
---|
[c3d926f3] | 590 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_RESET_DEVICE_CMD);
|
---|
| 591 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
[c9bec1c] | 592 |
|
---|
[eb928c4] | 593 | return enqueue_command(hc, cmd);
|
---|
[05aeee0e] | 594 | }
|
---|
| 595 |
|
---|
[45457265] | 596 | static errno_t get_port_bandwidth_cmd(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[60af4cdb] | 597 | {
|
---|
| 598 | assert(hc);
|
---|
| 599 | assert(cmd);
|
---|
| 600 |
|
---|
[c3d926f3] | 601 | xhci_trb_clean(&cmd->_header.trb);
|
---|
[60af4cdb] | 602 |
|
---|
[1d758fc] | 603 | const uintptr_t phys = dma_buffer_phys_base(&cmd->input_ctx);
|
---|
| 604 | TRB_SET_ICTX(cmd->_header.trb, phys);
|
---|
[60af4cdb] | 605 |
|
---|
[c3d926f3] | 606 | TRB_SET_TYPE(cmd->_header.trb, XHCI_TRB_TYPE_GET_PORT_BANDWIDTH_CMD);
|
---|
| 607 | TRB_SET_SLOT(cmd->_header.trb, cmd->slot_id);
|
---|
| 608 | TRB_SET_DEV_SPEED(cmd->_header.trb, cmd->device_speed);
|
---|
[60af4cdb] | 609 |
|
---|
[eb928c4] | 610 | return enqueue_command(hc, cmd);
|
---|
[60af4cdb] | 611 | }
|
---|
| 612 |
|
---|
[c3d926f3] | 613 | /* The table of command-issuing functions. */
|
---|
| 614 |
|
---|
[45457265] | 615 | typedef errno_t (*cmd_handler) (xhci_hc_t *hc, xhci_cmd_t *cmd);
|
---|
[c3d926f3] | 616 |
|
---|
| 617 | static cmd_handler cmd_handlers [] = {
|
---|
| 618 | [XHCI_CMD_ENABLE_SLOT] = enable_slot_cmd,
|
---|
| 619 | [XHCI_CMD_DISABLE_SLOT] = disable_slot_cmd,
|
---|
| 620 | [XHCI_CMD_ADDRESS_DEVICE] = address_device_cmd,
|
---|
| 621 | [XHCI_CMD_CONFIGURE_ENDPOINT] = configure_endpoint_cmd,
|
---|
| 622 | [XHCI_CMD_EVALUATE_CONTEXT] = evaluate_context_cmd,
|
---|
| 623 | [XHCI_CMD_RESET_ENDPOINT] = reset_endpoint_cmd,
|
---|
| 624 | [XHCI_CMD_STOP_ENDPOINT] = stop_endpoint_cmd,
|
---|
| 625 | [XHCI_CMD_SET_TR_DEQUEUE_POINTER] = set_tr_dequeue_pointer_cmd,
|
---|
| 626 | [XHCI_CMD_RESET_DEVICE] = reset_device_cmd,
|
---|
| 627 | [XHCI_CMD_FORCE_EVENT] = NULL,
|
---|
| 628 | [XHCI_CMD_NEGOTIATE_BANDWIDTH] = NULL,
|
---|
| 629 | [XHCI_CMD_SET_LATENCY_TOLERANCE_VALUE] = NULL,
|
---|
| 630 | [XHCI_CMD_GET_PORT_BANDWIDTH] = get_port_bandwidth_cmd,
|
---|
| 631 | [XHCI_CMD_FORCE_HEADER] = NULL,
|
---|
| 632 | [XHCI_CMD_NO_OP] = no_op_cmd
|
---|
| 633 | };
|
---|
| 634 |
|
---|
[eb928c4] | 635 | /**
|
---|
| 636 | * Try to abort currently processed command. This is tricky, because
|
---|
| 637 | * calling fibril is not necessarily the one which issued the blocked command.
|
---|
| 638 | * Also, the trickiness intensifies by the fact that stopping a CR is denoted by
|
---|
| 639 | * event, which is again handled in different fibril. but, once we go to sleep
|
---|
| 640 | * on waiting for that event, another fibril may wake up and try to abort the
|
---|
| 641 | * blocked command.
|
---|
| 642 | *
|
---|
| 643 | * So, we mark the command ring as being restarted, wait for it to stop, and
|
---|
| 644 | * then start it again. If there was a blocked command, it will be satisfied by
|
---|
| 645 | * COMMAND_ABORTED event.
|
---|
| 646 | */
|
---|
[45457265] | 647 | static errno_t try_abort_current_command(xhci_hc_t *hc)
|
---|
[889146e] | 648 | {
|
---|
| 649 | xhci_cmd_ring_t *cr = get_cmd_ring(hc);
|
---|
| 650 |
|
---|
| 651 | fibril_mutex_lock(&cr->guard);
|
---|
| 652 |
|
---|
[d2c3dcd] | 653 | if (cr->state == XHCI_CR_STATE_CLOSED) {
|
---|
| 654 | fibril_mutex_unlock(&cr->guard);
|
---|
| 655 | return ENAK;
|
---|
| 656 | }
|
---|
| 657 |
|
---|
| 658 | if (cr->state == XHCI_CR_STATE_CHANGING) {
|
---|
[889146e] | 659 | fibril_mutex_unlock(&cr->guard);
|
---|
| 660 | return EOK;
|
---|
| 661 | }
|
---|
| 662 |
|
---|
[ae3a941] | 663 | usb_log_error("Timeout while waiting for command: "
|
---|
| 664 | "aborting current command.");
|
---|
[889146e] | 665 |
|
---|
[d2c3dcd] | 666 | cr_set_state(cr, XHCI_CR_STATE_CHANGING);
|
---|
[889146e] | 667 |
|
---|
| 668 | abort_command_ring(hc);
|
---|
| 669 |
|
---|
[ae3a941] | 670 | fibril_condvar_wait_timeout(&cr->stopped_cv, &cr->guard,
|
---|
| 671 | XHCI_CR_ABORT_TIMEOUT);
|
---|
[889146e] | 672 |
|
---|
| 673 | if (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR)) {
|
---|
[7c3fb9b] | 674 | /*
|
---|
| 675 | * 4.6.1.2, implementation note
|
---|
[889146e] | 676 | * Assume there are larger problems with HC and
|
---|
| 677 | * reset it.
|
---|
| 678 | */
|
---|
[837581fd] | 679 | usb_log_error("Command didn't abort.");
|
---|
[889146e] | 680 |
|
---|
[d2c3dcd] | 681 | cr_set_state(cr, XHCI_CR_STATE_CLOSED);
|
---|
[889146e] | 682 |
|
---|
| 683 | // TODO: Reset HC completely.
|
---|
| 684 | // Don't forget to somehow complete all commands with error.
|
---|
| 685 |
|
---|
| 686 | fibril_mutex_unlock(&cr->guard);
|
---|
| 687 | return ENAK;
|
---|
| 688 | }
|
---|
| 689 |
|
---|
[d2c3dcd] | 690 | cr_set_state(cr, XHCI_CR_STATE_OPEN);
|
---|
| 691 |
|
---|
| 692 | fibril_mutex_unlock(&cr->guard);
|
---|
| 693 |
|
---|
[837581fd] | 694 | usb_log_error("Command ring stopped. Starting again.");
|
---|
[889146e] | 695 | hc_ring_doorbell(hc, 0, 0);
|
---|
| 696 |
|
---|
| 697 | return EOK;
|
---|
| 698 | }
|
---|
| 699 |
|
---|
[eb928c4] | 700 | /**
|
---|
| 701 | * Wait, until the command is completed. The completion is triggered by
|
---|
| 702 | * COMMAND_COMPLETION event. As we do not want to rely on HW completing the
|
---|
| 703 | * command in timely manner, we timeout. Note that we can't just return an
|
---|
| 704 | * error after the timeout pass - it may be other command blocking the ring,
|
---|
| 705 | * and ours can be completed afterwards. Therefore, it is not guaranteed that
|
---|
| 706 | * this function will return in XHCI_COMMAND_TIMEOUT. It will continue waiting
|
---|
| 707 | * until COMMAND_COMPLETION event arrives.
|
---|
| 708 | */
|
---|
[45457265] | 709 | static errno_t wait_for_cmd_completion(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[f9e7fe8] | 710 | {
|
---|
[45457265] | 711 | errno_t rv = EOK;
|
---|
[c058a388] | 712 |
|
---|
[f3baab1] | 713 | if (fibril_get_id() == hc->event_handler) {
|
---|
| 714 | usb_log_error("Deadlock detected in waiting for command.");
|
---|
| 715 | abort();
|
---|
| 716 | }
|
---|
| 717 |
|
---|
[c3d926f3] | 718 | fibril_mutex_lock(&cmd->_header.completed_mtx);
|
---|
| 719 | while (!cmd->_header.completed) {
|
---|
[f9e7fe8] | 720 |
|
---|
[8033f89] | 721 | rv = fibril_condvar_wait_timeout(&cmd->_header.completed_cv,
|
---|
| 722 | &cmd->_header.completed_mtx, XHCI_COMMAND_TIMEOUT);
|
---|
[889146e] | 723 |
|
---|
[7c3fb9b] | 724 | /*
|
---|
| 725 | * The waiting timed out. Current command (not necessarily
|
---|
[889146e] | 726 | * ours) is probably blocked.
|
---|
| 727 | */
|
---|
| 728 | if (!cmd->_header.completed && rv == ETIMEOUT) {
|
---|
| 729 | fibril_mutex_unlock(&cmd->_header.completed_mtx);
|
---|
| 730 |
|
---|
| 731 | rv = try_abort_current_command(hc);
|
---|
| 732 | if (rv)
|
---|
| 733 | return rv;
|
---|
| 734 |
|
---|
| 735 | fibril_mutex_lock(&cmd->_header.completed_mtx);
|
---|
[c3d926f3] | 736 | }
|
---|
| 737 | }
|
---|
| 738 | fibril_mutex_unlock(&cmd->_header.completed_mtx);
|
---|
[f711f06] | 739 |
|
---|
[c3d926f3] | 740 | return rv;
|
---|
| 741 | }
|
---|
[2fa43d1] | 742 |
|
---|
[eb928c4] | 743 | /**
|
---|
| 744 | * Issue command and block the current fibril until it is completed or timeout
|
---|
| 745 | * expires. Nothing is deallocated. Caller should always execute `xhci_cmd_fini`.
|
---|
[c3d926f3] | 746 | */
|
---|
[45457265] | 747 | errno_t xhci_cmd_sync(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c3d926f3] | 748 | {
|
---|
| 749 | assert(hc);
|
---|
| 750 | assert(cmd);
|
---|
[2fa43d1] | 751 |
|
---|
[45457265] | 752 | errno_t err;
|
---|
[c3d926f3] | 753 |
|
---|
| 754 | if (!cmd_handlers[cmd->_header.cmd]) {
|
---|
| 755 | /* Handler not implemented. */
|
---|
| 756 | return ENOTSUP;
|
---|
[2fa43d1] | 757 | }
|
---|
[110d795] | 758 |
|
---|
[c3d926f3] | 759 | if ((err = cmd_handlers[cmd->_header.cmd](hc, cmd))) {
|
---|
| 760 | /* Command could not be issued. */
|
---|
| 761 | return err;
|
---|
| 762 | }
|
---|
[110d795] | 763 |
|
---|
[889146e] | 764 | if ((err = wait_for_cmd_completion(hc, cmd))) {
|
---|
| 765 | /* Command failed. */
|
---|
[c3d926f3] | 766 | return err;
|
---|
[665bf3c] | 767 | }
|
---|
[c362127] | 768 |
|
---|
[e7e99bf] | 769 | switch (cmd->status) {
|
---|
| 770 | case XHCI_TRBC_SUCCESS:
|
---|
| 771 | return EOK;
|
---|
| 772 | case XHCI_TRBC_USB_TRANSACTION_ERROR:
|
---|
| 773 | return ESTALL;
|
---|
[feabe163] | 774 | case XHCI_TRBC_RESOURCE_ERROR:
|
---|
| 775 | case XHCI_TRBC_BANDWIDTH_ERROR:
|
---|
| 776 | case XHCI_TRBC_NO_SLOTS_ERROR:
|
---|
| 777 | return ELIMIT;
|
---|
| 778 | case XHCI_TRBC_SLOT_NOT_ENABLED_ERROR:
|
---|
| 779 | return ENOENT;
|
---|
[e7e99bf] | 780 | default:
|
---|
| 781 | return EINVAL;
|
---|
| 782 | }
|
---|
[c3d926f3] | 783 | }
|
---|
[110d795] | 784 |
|
---|
[eb928c4] | 785 | /**
|
---|
| 786 | * Does the same thing as `xhci_cmd_sync` and executes `xhci_cmd_fini`. This
|
---|
| 787 | * is a useful shorthand for issuing commands without out parameters.
|
---|
[c3d926f3] | 788 | */
|
---|
[45457265] | 789 | errno_t xhci_cmd_sync_fini(xhci_hc_t *hc, xhci_cmd_t *cmd)
|
---|
[c3d926f3] | 790 | {
|
---|
[45457265] | 791 | const errno_t err = xhci_cmd_sync(hc, cmd);
|
---|
[c3d926f3] | 792 | xhci_cmd_fini(cmd);
|
---|
| 793 |
|
---|
| 794 | return err;
|
---|
| 795 | }
|
---|
| 796 |
|
---|
[eb928c4] | 797 | /**
|
---|
| 798 | * Does the same thing as `xhci_cmd_sync_fini` without blocking the current
|
---|
| 799 | * fibril. The command is copied to stack memory and `fini` is called upon its completion.
|
---|
[c3d926f3] | 800 | */
|
---|
[45457265] | 801 | errno_t xhci_cmd_async_fini(xhci_hc_t *hc, xhci_cmd_t *stack_cmd)
|
---|
[c3d926f3] | 802 | {
|
---|
| 803 | assert(hc);
|
---|
| 804 | assert(stack_cmd);
|
---|
| 805 |
|
---|
| 806 | /* Save the command for later. */
|
---|
| 807 | xhci_cmd_t *heap_cmd = (xhci_cmd_t *) malloc(sizeof(xhci_cmd_t));
|
---|
| 808 | if (!heap_cmd) {
|
---|
| 809 | return ENOMEM;
|
---|
| 810 | }
|
---|
| 811 |
|
---|
| 812 | /* TODO: Is this good for the mutex and the condvar? */
|
---|
| 813 | memcpy(heap_cmd, stack_cmd, sizeof(xhci_cmd_t));
|
---|
| 814 | heap_cmd->_header.async = true;
|
---|
| 815 |
|
---|
| 816 | /* Issue the command. */
|
---|
[45457265] | 817 | errno_t err;
|
---|
[c3d926f3] | 818 |
|
---|
| 819 | if (!cmd_handlers[heap_cmd->_header.cmd]) {
|
---|
| 820 | /* Handler not implemented. */
|
---|
| 821 | err = ENOTSUP;
|
---|
| 822 | goto err_heap_cmd;
|
---|
[f711f06] | 823 | }
|
---|
[110d795] | 824 |
|
---|
[c3d926f3] | 825 | if ((err = cmd_handlers[heap_cmd->_header.cmd](hc, heap_cmd))) {
|
---|
| 826 | /* Command could not be issued. */
|
---|
| 827 | goto err_heap_cmd;
|
---|
| 828 | }
|
---|
[4688350b] | 829 |
|
---|
[110d795] | 830 | return EOK;
|
---|
[c9c0e41] | 831 |
|
---|
[c3d926f3] | 832 | err_heap_cmd:
|
---|
| 833 | free(heap_cmd);
|
---|
| 834 | return err;
|
---|
| 835 | }
|
---|
[c9c0e41] | 836 |
|
---|
| 837 | /**
|
---|
| 838 | * @}
|
---|
| 839 | */
|
---|