source: mainline/uspace/drv/bus/usb/uhci/hc.c@ eb3683a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since eb3683a was 8486c07, checked in by Martin Decky <martin@…>, 13 years ago

IRQ pseudocode improvements

  • rename CMD_BTEST to CMD_AND (less cryptic)
  • implement CMD_LOAD to load a constant value into a scratch register
  • implement simple pseudocode static checker
  • slightly alter the semantics of several pseudocode commands (scratch[0] is a usable field, although not propagated to the IPC notification)
  • Property mode set to 100644
File size: 15.4 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "uhci_batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
52 .base = 0,
53 .size = sizeof(uhci_regs_t)
54 }
55};
56
57static const irq_cmd_t uhci_irq_commands[] = {
58 {
59 .cmd = CMD_PIO_READ_16,
60 .dstarg = 1,
61 .addr = NULL
62 },
63 {
64 .cmd = CMD_AND,
65 .srcarg = 1,
66 .dstarg = 2,
67 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
68 },
69 {
70 .cmd = CMD_PREDICATE,
71 .srcarg = 2,
72 .value = 2
73 },
74 {
75 .cmd = CMD_PIO_WRITE_A_16,
76 .srcarg = 1,
77 .addr = NULL
78 },
79 {
80 .cmd = CMD_ACCEPT
81 }
82};
83
84static void hc_init_hw(const hc_t *instance);
85static int hc_init_mem_structures(hc_t *instance);
86static int hc_init_transfer_lists(hc_t *instance);
87static int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
88
89static int hc_interrupt_emulator(void *arg);
90static int hc_debug_checker(void *arg);
91
92
93/** Get number of PIO ranges used in IRQ code.
94 * @return Number of ranges.
95 */
96size_t hc_irq_pio_range_count(void)
97{
98 return sizeof(uhci_irq_pio_ranges) / sizeof(irq_pio_range_t);
99}
100
101/** Get number of commands used in IRQ code.
102 * @return Number of commands.
103 */
104size_t hc_irq_cmd_count(void)
105{
106 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
107}
108
109/** Generate IRQ code.
110 * @param[out] ranges PIO ranges buffer.
111 * @param[in] ranges_size Size of the ranges buffer (bytes).
112 * @param[out] cmds Commands buffer.
113 * @param[in] cmds_size Size of the commands buffer (bytes).
114 * @param[in] regs Physical address of device's registers.
115 * @param[in] reg_size Size of the register area (bytes).
116 *
117 * @return Error code.
118 */
119int
120hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
121 size_t cmds_size, uintptr_t regs, size_t reg_size)
122{
123 if ((ranges_size < sizeof(uhci_irq_pio_ranges)) ||
124 (cmds_size < sizeof(uhci_irq_commands)) ||
125 (reg_size < sizeof(uhci_regs_t)))
126 return EOVERFLOW;
127
128 memcpy(ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
129 ranges[0].base = regs;
130
131 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
132 uhci_regs_t *registers = (uhci_regs_t *) regs;
133 cmds[0].addr = &registers->usbsts;
134 cmds[3].addr = &registers->usbsts;
135
136 return EOK;
137}
138
139/** Take action based on the interrupt cause.
140 *
141 * @param[in] instance UHCI structure to use.
142 * @param[in] status Value of the status register at the time of interrupt.
143 *
144 * Interrupt might indicate:
145 * - transaction completed, either by triggering IOC, SPD, or an error
146 * - some kind of device error
147 * - resume from suspend state (not implemented)
148 */
149void hc_interrupt(hc_t *instance, uint16_t status)
150{
151 assert(instance);
152 /* Lower 2 bits are transaction error and transaction complete */
153 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
154 LIST_INITIALIZE(done);
155 transfer_list_remove_finished(
156 &instance->transfers_interrupt, &done);
157 transfer_list_remove_finished(
158 &instance->transfers_control_slow, &done);
159 transfer_list_remove_finished(
160 &instance->transfers_control_full, &done);
161 transfer_list_remove_finished(
162 &instance->transfers_bulk_full, &done);
163
164 while (!list_empty(&done)) {
165 link_t *item = list_first(&done);
166 list_remove(item);
167 uhci_transfer_batch_t *batch =
168 uhci_transfer_batch_from_link(item);
169 uhci_transfer_batch_finish_dispose(batch);
170 }
171 }
172 /* Resume interrupts are not supported */
173 if (status & UHCI_STATUS_RESUME) {
174 usb_log_error("Resume interrupt!\n");
175 }
176
177 /* Bits 4 and 5 indicate hc error */
178 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
179 usb_log_error("UHCI hardware failure!.\n");
180 ++instance->hw_failures;
181 transfer_list_abort_all(&instance->transfers_interrupt);
182 transfer_list_abort_all(&instance->transfers_control_slow);
183 transfer_list_abort_all(&instance->transfers_control_full);
184 transfer_list_abort_all(&instance->transfers_bulk_full);
185
186 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
187 /* reinitialize hw, this triggers virtual disconnect*/
188 hc_init_hw(instance);
189 } else {
190 usb_log_fatal("Too many UHCI hardware failures!.\n");
191 hc_fini(instance);
192 }
193 }
194}
195
196/** Initialize UHCI hc driver structure
197 *
198 * @param[in] instance Memory place to initialize.
199 * @param[in] regs Address of I/O control registers.
200 * @param[in] reg_size Size of I/O control registers.
201 * @param[in] interrupts True if hw interrupts should be used.
202 * @return Error code.
203 * @note Should be called only once on any structure.
204 *
205 * Initializes memory structures, starts up hw, and launches debugger and
206 * interrupt fibrils.
207 */
208int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
209{
210 assert(reg_size >= sizeof(uhci_regs_t));
211 int ret;
212
213#define CHECK_RET_RETURN(ret, message...) \
214 if (ret != EOK) { \
215 usb_log_error(message); \
216 return ret; \
217 } else (void) 0
218
219 instance->hw_interrupts = interrupts;
220 instance->hw_failures = 0;
221
222 /* allow access to hc control registers */
223 uhci_regs_t *io;
224 ret = pio_enable(regs, reg_size, (void **)&io);
225 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
226 io, str_error(ret));
227 instance->registers = io;
228 usb_log_debug(
229 "Device registers at %p (%zuB) accessible.\n", io, reg_size);
230
231 ret = hc_init_mem_structures(instance);
232 CHECK_RET_RETURN(ret,
233 "Failed to initialize UHCI memory structures: %s.\n",
234 str_error(ret));
235
236#undef CHECK_RET_RETURN
237
238 hcd_init(&instance->generic, USB_SPEED_FULL,
239 BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11);
240
241 instance->generic.private_data = instance;
242 instance->generic.schedule = hc_schedule;
243 instance->generic.ep_add_hook = NULL;
244
245 hc_init_hw(instance);
246 if (!interrupts) {
247 instance->interrupt_emulator =
248 fibril_create(hc_interrupt_emulator, instance);
249 fibril_add_ready(instance->interrupt_emulator);
250 }
251 (void)hc_debug_checker;
252
253 return EOK;
254}
255
256/** Initialize UHCI hc hw resources.
257 *
258 * @param[in] instance UHCI structure to use.
259 * For magic values see UHCI Design Guide
260 */
261void hc_init_hw(const hc_t *instance)
262{
263 assert(instance);
264 uhci_regs_t *registers = instance->registers;
265
266 /* Reset everything, who knows what touched it before us */
267 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
268 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
269 pio_write_16(&registers->usbcmd, 0);
270
271 /* Reset hc, all states and counters. Hope that hw is not broken */
272 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
273 do { async_usleep(10); }
274 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
275
276 /* Set frame to exactly 1ms */
277 pio_write_8(&registers->sofmod, 64);
278
279 /* Set frame list pointer */
280 const uint32_t pa = addr_to_phys(instance->frame_list);
281 pio_write_32(&registers->flbaseadd, pa);
282
283 if (instance->hw_interrupts) {
284 /* Enable all interrupts, but resume interrupt */
285 pio_write_16(&instance->registers->usbintr,
286 UHCI_INTR_ALLOW_INTERRUPTS);
287 }
288
289 const uint16_t cmd = pio_read_16(&registers->usbcmd);
290 if (cmd != 0)
291 usb_log_warning("Previous command value: %x.\n", cmd);
292
293 /* Start the hc with large(64B) packet FSBR */
294 pio_write_16(&registers->usbcmd,
295 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
296}
297
298/** Initialize UHCI hc memory structures.
299 *
300 * @param[in] instance UHCI structure to use.
301 * @return Error code
302 * @note Should be called only once on any structure.
303 *
304 * Structures:
305 * - transfer lists (queue heads need to be accessible by the hw)
306 * - frame list page (needs to be one UHCI hw accessible 4K page)
307 */
308int hc_init_mem_structures(hc_t *instance)
309{
310 assert(instance);
311
312 /* Init USB frame list page */
313 instance->frame_list = get_page();
314 if (!instance->frame_list) {
315 return ENOMEM;
316 }
317 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
318
319 /* Init transfer lists */
320 int ret = hc_init_transfer_lists(instance);
321 if (ret != EOK) {
322 usb_log_error("Failed to initialize transfer lists.\n");
323 return_page(instance->frame_list);
324 return ENOMEM;
325 }
326 usb_log_debug("Initialized transfer lists.\n");
327
328
329 /* Set all frames to point to the first queue head */
330 const uint32_t queue = LINK_POINTER_QH(
331 addr_to_phys(instance->transfers_interrupt.queue_head));
332
333 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
334 instance->frame_list[i] = queue;
335 }
336
337 return EOK;
338}
339
340/** Initialize UHCI hc transfer lists.
341 *
342 * @param[in] instance UHCI structure to use.
343 * @return Error code
344 * @note Should be called only once on any structure.
345 *
346 * Initializes transfer lists and sets them in one chain to support proper
347 * USB scheduling. Sets pointer table for quick access.
348 */
349int hc_init_transfer_lists(hc_t *instance)
350{
351 assert(instance);
352#define SETUP_TRANSFER_LIST(type, name) \
353do { \
354 int ret = transfer_list_init(&instance->transfers_##type, name); \
355 if (ret != EOK) { \
356 usb_log_error("Failed to setup %s transfer list: %s.\n", \
357 name, str_error(ret)); \
358 transfer_list_fini(&instance->transfers_bulk_full); \
359 transfer_list_fini(&instance->transfers_control_full); \
360 transfer_list_fini(&instance->transfers_control_slow); \
361 transfer_list_fini(&instance->transfers_interrupt); \
362 return ret; \
363 } \
364} while (0)
365
366 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
367 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
368 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
369 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
370#undef SETUP_TRANSFER_LIST
371 /* Connect lists into one schedule */
372 transfer_list_set_next(&instance->transfers_control_full,
373 &instance->transfers_bulk_full);
374 transfer_list_set_next(&instance->transfers_control_slow,
375 &instance->transfers_control_full);
376 transfer_list_set_next(&instance->transfers_interrupt,
377 &instance->transfers_control_slow);
378
379 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
380 * buggy on certain hw, enable at your own risk. */
381#ifdef FSBR
382 transfer_list_set_next(&instance->transfers_bulk_full,
383 &instance->transfers_control_full);
384#endif
385
386 /* Assign pointers to be used during scheduling */
387 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
388 &instance->transfers_interrupt;
389 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
390 &instance->transfers_interrupt;
391 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
392 &instance->transfers_control_full;
393 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
394 &instance->transfers_control_slow;
395 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
396 &instance->transfers_bulk_full;
397
398 return EOK;
399#undef CHECK_RET_CLEAR_RETURN
400}
401
402/** Schedule batch for execution.
403 *
404 * @param[in] instance UHCI structure to use.
405 * @param[in] batch Transfer batch to schedule.
406 * @return Error code
407 *
408 * Checks for bandwidth availability and appends the batch to the proper queue.
409 */
410int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
411{
412 assert(hcd);
413 hc_t *instance = hcd->private_data;
414 assert(instance);
415 assert(batch);
416 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
417 if (!uhci_batch) {
418 usb_log_error("Failed to create UHCI transfer structures.\n");
419 return ENOMEM;
420 }
421
422 transfer_list_t *list =
423 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
424 assert(list);
425 transfer_list_add_batch(list, uhci_batch);
426
427 return EOK;
428}
429
430/** Polling function, emulates interrupts.
431 *
432 * @param[in] arg UHCI hc structure to use.
433 * @return EOK (should never return)
434 */
435int hc_interrupt_emulator(void* arg)
436{
437 usb_log_debug("Started interrupt emulator.\n");
438 hc_t *instance = arg;
439 assert(instance);
440
441 while (1) {
442 /* Read and clear status register */
443 uint16_t status = pio_read_16(&instance->registers->usbsts);
444 pio_write_16(&instance->registers->usbsts, status);
445 if (status != 0)
446 usb_log_debug2("UHCI status: %x.\n", status);
447 hc_interrupt(instance, status);
448 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
449 }
450 return EOK;
451}
452
453/** Debug function, checks consistency of memory structures.
454 *
455 * @param[in] arg UHCI structure to use.
456 * @return EOK (should never return)
457 */
458int hc_debug_checker(void *arg)
459{
460 hc_t *instance = arg;
461 assert(instance);
462
463#define QH(queue) \
464 instance->transfers_##queue.queue_head
465
466 while (1) {
467 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
468 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
469 const uint16_t intr =
470 pio_read_16(&instance->registers->usbintr);
471
472 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
473 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
474 cmd, sts, intr);
475 }
476
477 const uintptr_t frame_list =
478 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
479 if (frame_list != addr_to_phys(instance->frame_list)) {
480 usb_log_debug("Framelist address: %p vs. %p.\n",
481 (void *) frame_list,
482 (void *) addr_to_phys(instance->frame_list));
483 }
484
485 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
486
487 uintptr_t expected_pa = instance->frame_list[frnum]
488 & LINK_POINTER_ADDRESS_MASK;
489 uintptr_t real_pa = addr_to_phys(QH(interrupt));
490 if (expected_pa != real_pa) {
491 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
492 (void *) expected_pa, frnum, (void *) real_pa);
493 }
494
495 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
496 real_pa = addr_to_phys(QH(control_slow));
497 if (expected_pa != real_pa) {
498 usb_log_debug("Control Slow QH: %p vs. %p.\n",
499 (void *) expected_pa, (void *) real_pa);
500 }
501
502 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
503 real_pa = addr_to_phys(QH(control_full));
504 if (expected_pa != real_pa) {
505 usb_log_debug("Control Full QH: %p vs. %p.\n",
506 (void *) expected_pa, (void *) real_pa);
507 }
508
509 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
510 real_pa = addr_to_phys(QH(bulk_full));
511 if (expected_pa != real_pa ) {
512 usb_log_debug("Bulk QH: %p vs. %p.\n",
513 (void *) expected_pa, (void *) real_pa);
514 }
515 async_usleep(UHCI_DEBUGER_TIMEOUT);
516 }
517 return EOK;
518#undef QH
519}
520/**
521 * @}
522 */
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