source: mainline/uspace/drv/bus/usb/ohci/ohci_regs.h@ c8ea6eca

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c8ea6eca was 904b1bc, checked in by Jiri Svoboda <jiri@…>, 8 years ago

Fix remaining ccheck issues.
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbohci
30 * @{
31 */
32/** @file
33 * @brief OHCI host controller register structure
34 */
35
36#ifndef DRV_OHCI_OHCI_REGS_H
37#define DRV_OHCI_OHCI_REGS_H
38
39#include <ddi.h>
40#include <byteorder.h>
41
42#define OHCI_WR(reg, val) pio_write_32(&(reg), host2uint32_t_le(val))
43#define OHCI_RD(reg) uint32_t_le2host(pio_read_32(&(reg)))
44#define OHCI_SET(reg, val) pio_set_32(&(reg), host2uint32_t_le(val), 1)
45#define OHCI_CLR(reg, val) pio_clear_32(&(reg), host2uint32_t_le(val), 1)
46
47#define LEGACY_REGS_OFFSET 0x100
48
49/** OHCI memory mapped registers structure */
50typedef struct ohci_regs {
51 const ioport32_t revision;
52
53 ioport32_t control;
54
55 ioport32_t command_status;
56
57 /** Interupt enable/disable/status,
58 * reads give the same value,
59 * writing causes enable/disable,
60 * status is write-clean (writing 1 clears the bit
61 */
62 ioport32_t interrupt_status;
63 ioport32_t interrupt_enable;
64 ioport32_t interrupt_disable;
65
66 /** HCCA pointer (see hw_struct hcca.h) */
67 ioport32_t hcca;
68
69 /** Currently executed periodic endpoint */
70 const ioport32_t periodic_current;
71
72 /** The first control endpoint */
73 ioport32_t control_head;
74
75 /** Currently executed control endpoint */
76 ioport32_t control_current;
77
78 /** The first bulk endpoint */
79 ioport32_t bulk_head;
80
81 /** Currently executed bulk endpoint */
82 ioport32_t bulk_current;
83
84 /** Done TD list, this value is periodically written to HCCA */
85 const ioport32_t done_head;
86
87 /** Frame time and max packet size for all transfers */
88 ioport32_t fm_interval;
89
90 /** Bit times remaining in current frame */
91 const ioport32_t fm_remaining;
92
93 /** Frame number */
94 const ioport32_t fm_number;
95
96 /** Remaining bit time in frame to start periodic transfers */
97 ioport32_t periodic_start;
98
99 /** Threshold for starting LS transaction */
100 ioport32_t ls_threshold;
101
102 /** The first root hub control register */
103 ioport32_t rh_desc_a;
104
105 /** The other root hub control register */
106 ioport32_t rh_desc_b;
107
108 /** Root hub status register */
109 ioport32_t rh_status;
110
111 /** Root hub per port status */
112 ioport32_t rh_port_status[];
113#define RHPS_CCS_FLAG (1 << 0) /* r: current connect status,
114 * w: 1-clear port enable, 0-N/S*/
115#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
116#define RHPS_PES_FLAG (1 << 1) /* r: port enable status
117 * w: 1-set port enable, 0-N/S */
118#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
119#define RHPS_PSS_FLAG (1 << 2) /* r: port suspend status
120 * w: 1-set port suspend, 0-N/S */
121#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
122#define RHPS_POCI_FLAG (1 << 3) /* r: port over-current
123 * (if reports are per-port
124 * w: 1-clear port suspend
125 * (start resume if suspened)
126 * 0-nothing */
127#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
128#define RHPS_PRS_FLAG (1 << 4) /* r: port reset status
129 * w: 1-set port reset, 0-N/S */
130#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
131#define RHPS_PPS_FLAG (1 << 8) /* r: port power status
132 * w: 1-set port power, 0-N/S */
133#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
134#define RHPS_LSDA_FLAG (1 << 9) /* r: low speed device attached
135 * w: 1-clear port power, 0-N/S*/
136#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
137#define RHPS_CSC_FLAG (1 << 16) /* connect status change WC */
138#define RHPS_PESC_FLAG (1 << 17) /* port enable status change WC */
139#define RHPS_PSSC_FLAG (1 << 18) /* port suspend status change WC */
140#define RHPS_OCIC_FLAG (1 << 19) /* port over-current change WC */
141#define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
142#define RHPS_CHANGE_WC_MASK (0x1f0000)
143} ohci_regs_t;
144
145/*
146 * ohci_regs_t.revision
147 */
148
149#define R_REVISION_MASK (0x3f)
150#define R_LEGACY_FLAG (0x80)
151
152/*
153 * ohci_regs_t.control
154 */
155
156/* Control-bulk service ratio */
157#define C_CBSR_1_1 (0x0)
158#define C_CBSR_1_2 (0x1)
159#define C_CBSR_1_3 (0x2)
160#define C_CBSR_1_4 (0x3)
161#define C_CBSR_MASK (0x3)
162#define C_CBSR_SHIFT 0
163
164#define C_PLE (1 << 2) /* Periodic list enable */
165#define C_IE (1 << 3) /* Isochronous enable */
166#define C_CLE (1 << 4) /* Control list enable */
167#define C_BLE (1 << 5) /* Bulk list enable */
168
169/* Host controller functional state */
170#define C_HCFS_RESET (0x0)
171#define C_HCFS_RESUME (0x1)
172#define C_HCFS_OPERATIONAL (0x2)
173#define C_HCFS_SUSPEND (0x3)
174#define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
175#define C_HCFS_SET(reg, value) \
176do { \
177 uint32_t r = OHCI_RD(reg); \
178 r &= ~(0x3 << 6); \
179 r |= (value & 0x3) << 6; \
180 OHCI_WR(reg, r); \
181} while (0)
182
183#define C_IR (1 << 8) /* Interrupt routing, make sure it's 0 */
184#define C_RWC (1 << 9) /* Remote wakeup connected, host specific */
185#define C_RWE (1 << 10) /* Remote wakeup enable */
186
187/*
188 * ohci_regs_t.command_status
189 */
190
191#define CS_HCR (1 << 0) /* Host controller reset */
192#define CS_CLF (1 << 1) /* Control list filled */
193#define CS_BLF (1 << 2) /* Bulk list filled */
194#define CS_OCR (1 << 3) /* Ownership change request */
195#if 0
196#define CS_SOC_MASK (0x3) /* Scheduling overrun count */
197#define CS_SOC_SHIFT (16)
198#endif
199
200/*
201 * ohci_regs_t.interrupt_xxx
202 */
203
204#define I_SO (1 << 0) /* Scheduling overrun */
205#define I_WDH (1 << 1) /* Done head write-back */
206#define I_SF (1 << 2) /* Start of frame */
207#define I_RD (1 << 3) /* Resume detect */
208#define I_UE (1 << 4) /* Unrecoverable error */
209#define I_FNO (1 << 5) /* Frame number overflow */
210#define I_RHSC (1 << 6) /* Root hub status change */
211#define I_OC (1 << 30) /* Ownership change */
212#define I_MI (1 << 31) /* Master interrupt (any/all) */
213
214
215/*
216 * ohci_regs_t.hcca
217 */
218
219#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
220
221/*
222 * ohci_regs_t.fm_interval
223 */
224
225#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
226#define FMI_FI_SHIFT (0)
227#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
228#define FMI_FSMPS_SHIFT (16)
229#define FMI_TOGGLE_FLAG (1 << 31)
230
231/*
232 * ohci_regs_t.fm_remaining
233 */
234
235#define FMR_FR_MASK FMI_FI_MASK
236#define FMR_FR_SHIFT FMI_FI_SHIFT
237#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
238
239/*
240 * ohci_regs_t.fm_number
241 */
242
243#define FMN_NUMBER_MASK (0xffff)
244
245/*
246 * ohci_regs_t.periodic_start
247 */
248
249#define PS_MASK 0x3fff
250#define PS_SHIFT 0
251
252/*
253 * ohci_regs_t.ls_threshold
254 */
255
256#define LST_LST_MASK (0x7fff)
257
258/*
259 * ohci_regs_t.rh_desc_a
260 */
261
262/** Number of downstream ports, max 15 */
263#define RHDA_NDS_MASK (0xff)
264/** Power switching mode: 0-global, 1-per port*/
265#define RHDA_PSM_FLAG (1 << 8)
266/** No power switch: 1-power on, 0-use PSM*/
267#define RHDA_NPS_FLAG (1 << 9)
268/** 1-Compound device, must be 0 */
269#define RHDA_DT_FLAG (1 << 10)
270/** Over-current mode: 0-global, 1-per port */
271#define RHDA_OCPM_FLAG (1 << 11)
272/** OC control: 0-use OCPM, 1-OC off */
273#define RHDA_NOCP_FLAG (1 << 12)
274/** Power on to power good time */
275#define RHDA_POTPGT_SHIFT 24
276
277/*
278 * ohci_regs_t.rh_desc_b
279 */
280
281/** Device removable mask */
282#define RHDB_DR_SHIFT 0
283#define RHDB_DR_MASK 0xffffU
284
285/** Power control mask */
286#define RHDB_PCC_MASK 0xffffU
287#define RHDB_PCC_SHIFT 16
288
289/*
290 * ohci_regs_t.rh_status
291 */
292
293/*
294 * read: 0,
295 * write: 0-no effect,
296 * 1-turn off port power for ports
297 * specified in PPCM(RHDB), or all ports,
298 * if power is set globally
299 */
300#define RHS_LPS_FLAG (1 << 0)
301#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
302/** Over-current indicator, if per-port: 0 */
303#define RHS_OCI_FLAG (1 << 1)
304/*
305 * read: 0-connect status change does not wake HC
306 * 1-connect status change wakes HC
307 * write: 1-set DRWE, 0-no effect
308 */
309#define RHS_DRWE_FLAG (1 << 15)
310#define RHS_SET_DRWE RHS_DRWE_FLAG
311/*
312 * read: 0,
313 * write: 0-no effect
314 * 1-turn on port power for ports
315 * specified in PPCM(RHDB), or all ports,
316 * if power is set globally
317 */
318#define RHS_LPSC_FLAG (1 << 16)
319#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
320/** Over-current change indicator*/
321#define RHS_OCIC_FLAG (1 << 17)
322#define RHS_CLEAR_DRWE (1 << 31)
323
324#endif
325
326/*
327 * ohci_regs_t.rh_port_status[x]
328 */
329
330/** r: current connect status, w: 1-clear port enable, 0-N/S*/
331#define RHPS_CCS_FLAG (1 << 0)
332#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
333/** r: port enable status, w: 1-set port enable, 0-N/S */
334#define RHPS_PES_FLAG (1 << 1)
335#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
336/** r: port suspend status, w: 1-set port suspend, 0-N/S */
337#define RHPS_PSS_FLAG (1 << 2)
338#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
339/** r: port over-current (if reports are per-port
340 * w: 1-clear port suspend (start resume if suspened), 0-nothing
341 */
342#define RHPS_POCI_FLAG (1 << 3)
343#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
344/** r: port reset status, w: 1-set port reset, 0-N/S */
345#define RHPS_PRS_FLAG (1 << 4)
346#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
347/** r: port power status, w: 1-set port power, 0-N/S */
348#define RHPS_PPS_FLAG (1 << 8)
349#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
350/** r: low speed device attached, w: 1-clear port power, 0-N/S */
351#define RHPS_LSDA_FLAG (1 << 9)
352#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
353/** connect status change WC */
354#define RHPS_CSC_FLAG (1 << 16)
355/** port enable status change WC */
356#define RHPS_PESC_FLAG (1 << 17)
357/** port suspend status change WC */
358#define RHPS_PSSC_FLAG (1 << 18)
359/** port over-current change WC */
360#define RHPS_OCIC_FLAG (1 << 19)
361/** port reset status change WC */
362#define RHPS_PRSC_FLAG (1 << 20)
363#define RHPS_CHANGE_WC_MASK (0x1f0000)
364
365/**
366 * @}
367 */
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