| 1 | /*
|
|---|
| 2 | * Copyright (c) 2011 Jan Vesely
|
|---|
| 3 | * All rights reserved.
|
|---|
| 4 | *
|
|---|
| 5 | * Redistribution and use in source and binary forms, with or without
|
|---|
| 6 | * modification, are permitted provided that the following conditions
|
|---|
| 7 | * are met:
|
|---|
| 8 | *
|
|---|
| 9 | * - Redistributions of source code must retain the above copyright
|
|---|
| 10 | * notice, this list of conditions and the following disclaimer.
|
|---|
| 11 | * - Redistributions in binary form must reproduce the above copyright
|
|---|
| 12 | * notice, this list of conditions and the following disclaimer in the
|
|---|
| 13 | * documentation and/or other materials provided with the distribution.
|
|---|
| 14 | * - The name of the author may not be used to endorse or promote products
|
|---|
| 15 | * derived from this software without specific prior written permission.
|
|---|
| 16 | *
|
|---|
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|---|
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|---|
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|---|
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|---|
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|---|
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|---|
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|---|
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|---|
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|---|
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|---|
| 27 | */
|
|---|
| 28 | /** @addtogroup drvusbohci
|
|---|
| 29 | * @{
|
|---|
| 30 | */
|
|---|
| 31 | /** @file
|
|---|
| 32 | * @brief OHCI host controller register structure
|
|---|
| 33 | */
|
|---|
| 34 | #ifndef DRV_OHCI_OHCI_REGS_H
|
|---|
| 35 | #define DRV_OHCI_OHCI_REGS_H
|
|---|
| 36 | #include <sys/types.h>
|
|---|
| 37 | #include <byteorder.h>
|
|---|
| 38 |
|
|---|
| 39 |
|
|---|
| 40 | /* assume OHCI regs are le */
|
|---|
| 41 | #define host2ohci_reg(value) host2uint32_t_le(value)
|
|---|
| 42 | #define ohci_reg2host(value) uint32_t_le2host(value)
|
|---|
| 43 |
|
|---|
| 44 | #define OHCI_WR(reg, val) reg = host2uint32_t_le(val)
|
|---|
| 45 | #define OHCI_RD(reg) uint32_t_le2host(reg)
|
|---|
| 46 | #define OHCI_SET(reg, val) reg |= host2uint32_t_le(val)
|
|---|
| 47 | #define OHCI_CLR(reg, val) reg &= host2uint32_t_le(val)
|
|---|
| 48 |
|
|---|
| 49 |
|
|---|
| 50 | #define LEGACY_REGS_OFFSET 0x100
|
|---|
| 51 |
|
|---|
| 52 | /** OHCI memory mapped registers structure */
|
|---|
| 53 | typedef struct ohci_regs {
|
|---|
| 54 | const ioport32_t revision;
|
|---|
| 55 | #define R_REVISION_MASK (0x3f)
|
|---|
| 56 | #define R_LEGACY_FLAG (0x80)
|
|---|
| 57 |
|
|---|
| 58 | ioport32_t control;
|
|---|
| 59 | /* Control-bulk service ratio */
|
|---|
| 60 | #define C_CBSR_1_1 (0x0)
|
|---|
| 61 | #define C_CBSR_1_2 (0x1)
|
|---|
| 62 | #define C_CBSR_1_3 (0x2)
|
|---|
| 63 | #define C_CBSR_1_4 (0x3)
|
|---|
| 64 | #define C_CBSR_MASK (0x3)
|
|---|
| 65 | #define C_CBSR_SHIFT 0
|
|---|
| 66 |
|
|---|
| 67 | #define C_PLE (1 << 2) /* Periodic list enable */
|
|---|
| 68 | #define C_IE (1 << 3) /* Isochronous enable */
|
|---|
| 69 | #define C_CLE (1 << 4) /* Control list enable */
|
|---|
| 70 | #define C_BLE (1 << 5) /* Bulk list enable */
|
|---|
| 71 |
|
|---|
| 72 | /* Host controller functional state */
|
|---|
| 73 | #define C_HCFS_RESET (0x0)
|
|---|
| 74 | #define C_HCFS_RESUME (0x1)
|
|---|
| 75 | #define C_HCFS_OPERATIONAL (0x2)
|
|---|
| 76 | #define C_HCFS_SUSPEND (0x3)
|
|---|
| 77 | #define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
|
|---|
| 78 | #define C_HCFS_SET(reg, value) \
|
|---|
| 79 | do { \
|
|---|
| 80 | uint32_t r = OHCI_RD(reg); \
|
|---|
| 81 | r &= ~(0x3 << 6); \
|
|---|
| 82 | r |= (value & 0x3) << 6; \
|
|---|
| 83 | OHCI_WR(reg, r); \
|
|---|
| 84 | } while (0)
|
|---|
| 85 |
|
|---|
| 86 | #define C_IR (1 << 8) /* Interrupt routing, make sure it's 0 */
|
|---|
| 87 | #define C_RWC (1 << 9) /* Remote wakeup connected, host specific */
|
|---|
| 88 | #define C_RWE (1 << 10) /* Remote wakeup enable */
|
|---|
| 89 |
|
|---|
| 90 | ioport32_t command_status;
|
|---|
| 91 | #define CS_HCR (1 << 0) /* Host controller reset */
|
|---|
| 92 | #define CS_CLF (1 << 1) /* Control list filled */
|
|---|
| 93 | #define CS_BLF (1 << 2) /* Bulk list filled */
|
|---|
| 94 | #define CS_OCR (1 << 3) /* Ownership change request */
|
|---|
| 95 | #if 0
|
|---|
| 96 | #define CS_SOC_MASK (0x3) /* Scheduling overrun count */
|
|---|
| 97 | #define CS_SOC_SHIFT (16)
|
|---|
| 98 | #endif
|
|---|
| 99 |
|
|---|
| 100 | /** Interupt enable/disable/status,
|
|---|
| 101 | * reads give the same value,
|
|---|
| 102 | * writing causes enable/disable,
|
|---|
| 103 | * status is write-clean (writing 1 clears the bit*/
|
|---|
| 104 | ioport32_t interrupt_status;
|
|---|
| 105 | ioport32_t interrupt_enable;
|
|---|
| 106 | ioport32_t interrupt_disable;
|
|---|
| 107 | #define I_SO (1 << 0) /* Scheduling overrun */
|
|---|
| 108 | #define I_WDH (1 << 1) /* Done head write-back */
|
|---|
| 109 | #define I_SF (1 << 2) /* Start of frame */
|
|---|
| 110 | #define I_RD (1 << 3) /* Resume detect */
|
|---|
| 111 | #define I_UE (1 << 4) /* Unrecoverable error */
|
|---|
| 112 | #define I_FNO (1 << 5) /* Frame number overflow */
|
|---|
| 113 | #define I_RHSC (1 << 6) /* Root hub status change */
|
|---|
| 114 | #define I_OC (1 << 30) /* Ownership change */
|
|---|
| 115 | #define I_MI (1 << 31) /* Master interrupt (any/all) */
|
|---|
| 116 |
|
|---|
| 117 | /** HCCA pointer (see hw_struct hcca.h) */
|
|---|
| 118 | ioport32_t hcca;
|
|---|
| 119 | #define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
|
|---|
| 120 |
|
|---|
| 121 | /** Currently executed periodic endpoint */
|
|---|
| 122 | const ioport32_t periodic_current;
|
|---|
| 123 |
|
|---|
| 124 | /** The first control endpoint */
|
|---|
| 125 | ioport32_t control_head;
|
|---|
| 126 |
|
|---|
| 127 | /** Currently executed control endpoint */
|
|---|
| 128 | ioport32_t control_current;
|
|---|
| 129 |
|
|---|
| 130 | /** The first bulk endpoint */
|
|---|
| 131 | ioport32_t bulk_head;
|
|---|
| 132 |
|
|---|
| 133 | /** Currently executed bulk endpoint */
|
|---|
| 134 | ioport32_t bulk_current;
|
|---|
| 135 |
|
|---|
| 136 | /** Done TD list, this value is periodically written to HCCA */
|
|---|
| 137 | const ioport32_t done_head;
|
|---|
| 138 |
|
|---|
| 139 | /** Frame time and max packet size for all transfers */
|
|---|
| 140 | ioport32_t fm_interval;
|
|---|
| 141 | #define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
|
|---|
| 142 | #define FMI_FI_SHIFT (0)
|
|---|
| 143 | #define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
|
|---|
| 144 | #define FMI_FSMPS_SHIFT (16)
|
|---|
| 145 | #define FMI_TOGGLE_FLAG (1 << 31)
|
|---|
| 146 |
|
|---|
| 147 | /** Bit times remaining in current frame */
|
|---|
| 148 | const ioport32_t fm_remaining;
|
|---|
| 149 | #define FMR_FR_MASK FMI_FI_MASK
|
|---|
| 150 | #define FMR_FR_SHIFT FMI_FI_SHIFT
|
|---|
| 151 | #define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
|
|---|
| 152 |
|
|---|
| 153 | /** Frame number */
|
|---|
| 154 | const ioport32_t fm_number;
|
|---|
| 155 | #define FMN_NUMBER_MASK (0xffff)
|
|---|
| 156 |
|
|---|
| 157 | /** Remaining bit time in frame to start periodic transfers */
|
|---|
| 158 | ioport32_t periodic_start;
|
|---|
| 159 | #define PS_MASK 0x3fff
|
|---|
| 160 | #define PS_SHIFT 0
|
|---|
| 161 |
|
|---|
| 162 | /** Threshold for starting LS transaction */
|
|---|
| 163 | ioport32_t ls_threshold;
|
|---|
| 164 | #define LST_LST_MASK (0x7fff)
|
|---|
| 165 |
|
|---|
| 166 | /** The first root hub control register */
|
|---|
| 167 | ioport32_t rh_desc_a;
|
|---|
| 168 | /** Number of downstream ports, max 15 */
|
|---|
| 169 | #define RHDA_NDS_MASK (0xff)
|
|---|
| 170 | /** Power switching mode: 0-global, 1-per port*/
|
|---|
| 171 | #define RHDA_PSM_FLAG (1 << 8)
|
|---|
| 172 | /** No power switch: 1-power on, 0-use PSM*/
|
|---|
| 173 | #define RHDA_NPS_FLAG (1 << 9)
|
|---|
| 174 | /** 1-Compound device, must be 0 */
|
|---|
| 175 | #define RHDA_DT_FLAG (1 << 10)
|
|---|
| 176 | /** Over-current mode: 0-global, 1-per port */
|
|---|
| 177 | #define RHDA_OCPM_FLAG (1 << 11)
|
|---|
| 178 | /** OC control: 0-use OCPM, 1-OC off */
|
|---|
| 179 | #define RHDA_NOCP_FLAG (1 << 12)
|
|---|
| 180 | /** Power on to power good time */
|
|---|
| 181 | #define RHDA_POTPGT_SHIFT 24
|
|---|
| 182 |
|
|---|
| 183 | /** The other root hub control register */
|
|---|
| 184 | ioport32_t rh_desc_b;
|
|---|
| 185 | /** Device removable mask */
|
|---|
| 186 | #define RHDB_DR_SHIFT 0
|
|---|
| 187 | #define RHDB_DR_MASK 0xffff
|
|---|
| 188 | /** Power control mask */
|
|---|
| 189 | #define RHDB_PCC_MASK (0xffff)
|
|---|
| 190 | #define RHDB_PCC_SHIFT 16
|
|---|
| 191 |
|
|---|
| 192 | /** Root hub status register */
|
|---|
| 193 | ioport32_t rh_status;
|
|---|
| 194 | /* read: 0,
|
|---|
| 195 | * write: 0-no effect,
|
|---|
| 196 | * 1-turn off port power for ports
|
|---|
| 197 | * specified in PPCM(RHDB), or all ports,
|
|---|
| 198 | * if power is set globally */
|
|---|
| 199 | #define RHS_LPS_FLAG (1 << 0)
|
|---|
| 200 | #define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
|
|---|
| 201 | /** Over-current indicator, if per-port: 0 */
|
|---|
| 202 | #define RHS_OCI_FLAG (1 << 1)
|
|---|
| 203 |
|
|---|
| 204 | /* read: 0-connect status change does not wake HC
|
|---|
| 205 | * 1-connect status change wakes HC
|
|---|
| 206 | * write: 1-set DRWE, 0-no effect */
|
|---|
| 207 | #define RHS_DRWE_FLAG (1 << 15)
|
|---|
| 208 | #define RHS_SET_DRWE RHS_DRWE_FLAG
|
|---|
| 209 | /* read: 0,
|
|---|
| 210 | * write: 0-no effect
|
|---|
| 211 | * 1-turn on port power for ports
|
|---|
| 212 | * specified in PPCM(RHDB), or all ports,
|
|---|
| 213 | * if power is set globally */
|
|---|
| 214 | #define RHS_LPSC_FLAG (1 << 16)
|
|---|
| 215 | #define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
|
|---|
| 216 | /** Over-current change indicator*/
|
|---|
| 217 | #define RHS_OCIC_FLAG (1 << 17)
|
|---|
| 218 | #define RHS_CLEAR_DRWE (1 << 31)
|
|---|
| 219 |
|
|---|
| 220 | /** Root hub per port status */
|
|---|
| 221 | ioport32_t rh_port_status[];
|
|---|
| 222 | #define RHPS_CCS_FLAG (1 << 0) /* r: current connect status,
|
|---|
| 223 | * w: 1-clear port enable, 0-N/S*/
|
|---|
| 224 | #define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
|
|---|
| 225 | #define RHPS_PES_FLAG (1 << 1) /* r: port enable status
|
|---|
| 226 | * w: 1-set port enable, 0-N/S */
|
|---|
| 227 | #define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
|
|---|
| 228 | #define RHPS_PSS_FLAG (1 << 2) /* r: port suspend status
|
|---|
| 229 | * w: 1-set port suspend, 0-N/S */
|
|---|
| 230 | #define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
|
|---|
| 231 | #define RHPS_POCI_FLAG (1 << 3) /* r: port over-current
|
|---|
| 232 | * (if reports are per-port
|
|---|
| 233 | * w: 1-clear port suspend
|
|---|
| 234 | * (start resume if suspened)
|
|---|
| 235 | * 0-nothing */
|
|---|
| 236 | #define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
|
|---|
| 237 | #define RHPS_PRS_FLAG (1 << 4) /* r: port reset status
|
|---|
| 238 | * w: 1-set port reset, 0-N/S */
|
|---|
| 239 | #define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
|
|---|
| 240 | #define RHPS_PPS_FLAG (1 << 8) /* r: port power status
|
|---|
| 241 | * w: 1-set port power, 0-N/S */
|
|---|
| 242 | #define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
|
|---|
| 243 | #define RHPS_LSDA_FLAG (1 << 9) /* r: low speed device attached
|
|---|
| 244 | * w: 1-clear port power, 0-N/S*/
|
|---|
| 245 | #define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
|
|---|
| 246 | #define RHPS_CSC_FLAG (1 << 16) /* connect status change WC */
|
|---|
| 247 | #define RHPS_PESC_FLAG (1 << 17) /* port enable status change WC */
|
|---|
| 248 | #define RHPS_PSSC_FLAG (1 << 18) /* port suspend status change WC */
|
|---|
| 249 | #define RHPS_OCIC_FLAG (1 << 19) /* port over-current change WC */
|
|---|
| 250 | #define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
|
|---|
| 251 | #define RHPS_CHANGE_WC_MASK (0x1f0000)
|
|---|
| 252 | } __attribute__((packed)) ohci_regs_t;
|
|---|
| 253 | #endif
|
|---|
| 254 | /**
|
|---|
| 255 | * @}
|
|---|
| 256 | */
|
|---|
