source: mainline/uspace/drv/bus/usb/ohci/ohci_regs.h@ ffcc5776

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ffcc5776 was ffcc5776, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

ohci: Consider endian difference when accessing OHCI registers.

HC initialization works.
Root hub works.

Turn off work queues until memory structure endian is fixed.
  • Property mode set to 100644
File size: 10.5 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbohci
29 * @{
30 */
31/** @file
32 * @brief OHCI host controller register structure
33 */
34#ifndef DRV_OHCI_OHCI_REGS_H
35#define DRV_OHCI_OHCI_REGS_H
36#include <sys/types.h>
37#include <byteorder.h>
38
39
40/* assume OHCI regs are le */
41#define host2ohci_reg(value) host2uint32_t_le(value)
42#define ohci_reg2host(value) uint32_t_le2host(value)
43
44#define LEGACY_REGS_OFFSET 0x100
45
46/** OHCI memory mapped registers structure */
47typedef struct ohci_regs {
48 const ioport32_t revision;
49#define R_REVISION_(reg) (ohci_reg2host(reg) & 0x3f)
50#define R_LEGACY_FLAG host2ohci_reg(0x80)
51
52 ioport32_t control;
53/* Control-bulk service ratio */
54#define C_CBSR_1_1 (0x0)
55#define C_CBSR_1_2 (0x1)
56#define C_CBSR_1_3 (0x2)
57#define C_CBSR_1_4 (0x3)
58#define C_CBSR_GET(reg) (ohci_reg2host(reg) & 0x3)
59#define C_CBSR_SET(reg, value) \
60do { \
61 reg = (reg & host2ohci_reg(~0x3) | host2ohci_reg(value & 0x3)) \
62} while (0)
63
64#define C_PLE host2ohci_reg(1 << 2) /* Periodic list enable */
65#define C_IE host2ohci_reg(1 << 3) /* Isochronous enable */
66#define C_CLE host2ohci_reg(1 << 4) /* Control list enable */
67#define C_BLE host2ohci_reg(1 << 5) /* Bulk list enable */
68
69/* Host controller functional state */
70#define C_HCFS_RESET (0x0)
71#define C_HCFS_RESUME (0x1)
72#define C_HCFS_OPERATIONAL (0x2)
73#define C_HCFS_SUSPEND (0x3)
74#define C_HCFS_GET(reg) ((ohci_reg2host(reg) >> 6) & 0x3)
75#define C_HCFS_SET(reg, value) \
76do { \
77 reg = (reg & host2ohci_reg(~(0x3 << 6))) \
78 | host2ohci_reg((value & 0x3) << 6); \
79} while (0)
80
81#define C_IR host2ohci_reg(1 << 8) /* Interrupt routing, make sure it's 0 */
82#define C_RWC host2ohci_reg(1 << 9) /* Remote wakeup connected, host specific */
83#define C_RWE host2ohci_reg(1 << 10) /* Remote wakeup enable */
84
85 ioport32_t command_status;
86#define CS_HCR host2ohci_reg(1 << 0) /* Host controller reset */
87#define CS_CLF host2ohci_reg(1 << 1) /* Control list filled */
88#define CS_BLF host2ohci_reg(1 << 2) /* Bulk list filled */
89#define CS_OCR host2ohci_reg(1 << 3) /* Ownership change request */
90#if 0
91#define CS_SOC_MASK (0x3) /* Scheduling overrun count */
92#define CS_SOC_SHIFT (16)
93#endif
94
95 /** Interupt enable/disable/status,
96 * reads give the same value,
97 * writing causes enable/disable,
98 * status is write-clean (writing 1 clears the bit*/
99 ioport32_t interrupt_status;
100 ioport32_t interrupt_enable;
101 ioport32_t interrupt_disable;
102#define I_SO host2ohci_reg(1 << 0) /* Scheduling overrun */
103#define I_WDH host2ohci_reg(1 << 1) /* Done head write-back */
104#define I_SF host2ohci_reg(1 << 2) /* Start of frame */
105#define I_RD host2ohci_reg(1 << 3) /* Resume detect */
106#define I_UE host2ohci_reg(1 << 4) /* Unrecoverable error */
107#define I_FNO host2ohci_reg(1 << 5) /* Frame number overflow */
108#define I_RHSC host2ohci_reg(1 << 6) /* Root hub status change */
109#define I_OC host2ohci_reg(1 << 30) /* Ownership change */
110#define I_MI host2ohci_reg(1 << 31) /* Master interrupt (any/all) */
111
112 /** HCCA pointer (see hw_struct hcca.h) */
113 ioport32_t hcca;
114#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
115
116 /** Currently executed periodic endpoint */
117 const ioport32_t periodic_current;
118
119 /** The first control endpoint */
120 ioport32_t control_head;
121
122 /** Currently executed control endpoint */
123 ioport32_t control_current;
124
125 /** The first bulk endpoint */
126 ioport32_t bulk_head;
127
128 /** Currently executed bulk endpoint */
129 ioport32_t bulk_current;
130
131 /** Done TD list, this value is periodically written to HCCA */
132 const ioport32_t done_head;
133
134 /** Frame time and max packet size for all transfers */
135 ioport32_t fm_interval;
136#define FMI_FL_GET(reg) (ohci_reg2host(reg) & 0x3fff)
137#if 0
138#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
139#define FMI_FI_SHIFT (0)
140#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
141#define FMI_FSMPS_SHIFT (16)
142#define FMI_TOGGLE_FLAG (1 << 31)
143#endif
144
145 /** Bit times remaining in current frame */
146 const ioport32_t fm_remaining;
147#define FMR_R_GET(reg) (ohci_reg2host(reg) & 0x3fff)
148#if 0
149#define FMR_FR_MASK FMI_FI_MASK
150#define FMR_FR_SHIFT FMI_FI_SHIFT
151#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
152#endif
153 /** Frame number */
154 const ioport32_t fm_number;
155#if 0
156#define FMN_NUMBER_MASK (0xffff)
157#endif
158 /** Remaining bit time in frame to start periodic transfers */
159 ioport32_t periodic_start;
160#define PS_GET(reg) (ohci_reg2host(reg) & 0x3fff)
161#define PS_SET(reg, value) \
162do { \
163 reg = (reg & host2ohci_reg(~0x3fff)) | host2ohci_reg(value & 0x3fff); \
164} while (0)
165
166 /** Threshold for starting LS transaction */
167 ioport32_t ls_threshold;
168//#define LST_LST_MASK (0x7fff)
169
170 /** The first root hub control register */
171 ioport32_t rh_desc_a;
172/** Number of downstream ports, max 15 */
173#define RHDA_NDS(reg) (ohci_reg2host(reg) & 0xff)
174/** Power switching mode: 0-global, 1-per port*/
175#define RHDA_PSM_FLAG host2ohci_reg(1 << 8)
176/** No power switch: 1-power on, 0-use PSM*/
177#define RHDA_NPS_FLAG host2ohci_reg(1 << 9)
178/** 1-Compound device, must be 0 */
179#define RHDA_DT_FLAG host2ohci_reg(1 << 10)
180/** Over-current mode: 0-global, 1-per port */
181#define RHDA_OCPM_FLAG host2ohci_reg(1 << 11)
182/** OC control: 0-use OCPM, 1-OC off */
183#define RHDA_NOCP_FLAG host2ohci_reg(1 << 12)
184/** Power on to power good time */
185#define RHDA_POTPGT(reg) (ohci_reg2host(reg) >> 24)
186
187 /** The other root hub control register */
188 ioport32_t rh_desc_b;
189/** Device removable mask */
190#define RHDB_DR_READ(reg) (ohci_reg2host(reg) & 0xffff)
191#define RHDB_DR_WRITE(val) host2ohci_reg(val & 0xffff)
192/** Power control mask */
193#define RHDB_PCC_READ(reg) (ohci_reg2host(reg) >> 16)
194#define RHDB_PCC_WRITE(val) host2ohci_reg(val << 16)
195/* Port device removable status */
196#define RHDB_DR_FLAG(port) \
197 host2ohci_reg(((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
198/* Port power control status: 1-per port power control, 0-global power switch */
199#define RHDB_PPC_FLAG(port) \
200 host2ohci_reg(((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
201
202 /** Root hub status register */
203 ioport32_t rh_status;
204/* read: 0,
205 * write: 0-no effect,
206 * 1-turn off port power for ports
207 * specified in PPCM(RHDB), or all ports,
208 * if power is set globally */
209#define RHS_LPS_FLAG host2ohci_reg(1 << 0)
210#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
211/** Over-current indicator, if per-port: 0 */
212#define RHS_OCI_FLAG host2ohci_reg(1 << 1)
213
214/* read: 0-connect status change does not wake HC
215 * 1-connect status change wakes HC
216 * write: 1-set DRWE, 0-no effect */
217#define RHS_DRWE_FLAG host2ohci_reg(1 << 15)
218#define RHS_SET_DRWE RHS_DRWE_FLAG
219/* read: 0,
220 * write: 0-no effect
221 * 1-turn on port power for ports
222 * specified in PPCM(RHDB), or all ports,
223 * if power is set globally */
224#define RHS_LPSC_FLAG host2ohci_reg(1 << 16)
225#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
226/** Over-current change indicator*/
227#define RHS_OCIC_FLAG host2ohci_reg(1 << 17)
228#define RHS_CLEAR_DRWE host2ohci_reg(1 << 31)
229
230 /** Root hub per port status */
231 ioport32_t rh_port_status[];
232#define RHPS_CCS_FLAG host2ohci_reg(1 << 0) /* r: current connect status,
233 * w: 1-clear port enable, 0-N/S*/
234#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
235#define RHPS_PES_FLAG host2ohci_reg(1 << 1) /* r: port enable status
236 * w: 1-set port enable, 0-N/S */
237#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
238#define RHPS_PSS_FLAG host2ohci_reg(1 << 2) /* r: port suspend status
239 * w: 1-set port suspend, 0-N/S */
240#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
241#define RHPS_POCI_FLAG host2ohci_reg(1 << 3) /* r: port over-current
242 * (if reports are per-port
243 * w: 1-clear port suspend
244 * (start resume if suspened)
245 * 0-nothing */
246#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
247#define RHPS_PRS_FLAG host2ohci_reg(1 << 4) /* r: port reset status
248 * w: 1-set port reset, 0-N/S */
249#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
250#define RHPS_PPS_FLAG host2ohci_reg(1 << 8) /* r: port power status
251 * w: 1-set port power, 0-N/S */
252#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
253#define RHPS_LSDA_FLAG host2ohci_reg(1 << 9) /* r: low speed device attached
254 * w: 1-clear port power, 0-N/S*/
255#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
256#define RHPS_CSC_FLAG host2ohci_reg(1 << 16) /* connect status change WC */
257#define RHPS_PESC_FLAG host2ohci_reg(1 << 17) /* port enable status change WC */
258#define RHPS_PSSC_FLAG host2ohci_reg(1 << 18) /* port suspend status change WC */
259#define RHPS_OCIC_FLAG host2ohci_reg(1 << 19) /* port over-current change WC */
260#define RHPS_PRSC_FLAG host2ohci_reg(1 << 20) /* port reset status change WC */
261#define RHPS_CHANGE_WC_MASK host2ohci_reg(0x1f0000)
262/** OHCI designers were kind enough to make bits correspond to feature # */
263#define RHPS_FEATURE_BIT(feature) host2ohci_reg(1 << feature)
264} __attribute__((packed)) ohci_regs_t;
265#endif
266/**
267 * @}
268 */
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