source: mainline/uspace/drv/bus/usb/ehci/hc.c@ 4c25c2fb

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4c25c2fb was 35c37fc, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

ehci: refactor to dma_buffers

One big hidden thing was refactored - now TDs are allocated in one
buffer together with setup and data buffers themselves. This reduces the
number of allocated pages per transfer to minimum.
  • Property mode set to 100644
File size: 14.6 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbehcihc
30 * @{
31 */
32/** @file
33 * @brief EHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <stdint.h>
43#include <str_error.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47
48#include "ehci_batch.h"
49
50#include "hc.h"
51
52#define EHCI_USED_INTERRUPTS \
53 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
54 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
55
56static const irq_pio_range_t ehci_pio_ranges[] = {
57 {
58 .base = 0,
59 .size = sizeof(ehci_regs_t)
60 }
61};
62
63static const irq_cmd_t ehci_irq_commands[] = {
64 {
65 .cmd = CMD_PIO_READ_32,
66 .dstarg = 1,
67 .addr = NULL
68 },
69 {
70 .cmd = CMD_AND,
71 .srcarg = 1,
72 .dstarg = 2,
73 .value = 0
74 },
75 {
76 .cmd = CMD_PREDICATE,
77 .srcarg = 2,
78 .value = 2
79 },
80 {
81 .cmd = CMD_PIO_WRITE_A_32,
82 .srcarg = 1,
83 .addr = NULL
84 },
85 {
86 .cmd = CMD_ACCEPT
87 }
88};
89
90static int hc_init_memory(hc_t *instance);
91
92/** Generate IRQ code.
93 * @param[out] ranges PIO ranges buffer.
94 * @param[in] hw_res Device's resources.
95 *
96 * @return Error code.
97 */
98int hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
99{
100 assert(code);
101 assert(hw_res);
102 hc_t *instance = hcd_to_hc(hcd);
103
104 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
105 return EINVAL;
106
107 addr_range_t regs = hw_res->mem_ranges.ranges[0];
108
109 if (RNGSZ(regs) < sizeof(ehci_regs_t))
110 return EOVERFLOW;
111
112 code->ranges = malloc(sizeof(ehci_pio_ranges));
113 if (code->ranges == NULL)
114 return ENOMEM;
115
116 code->cmds = malloc(sizeof(ehci_irq_commands));
117 if (code->cmds == NULL) {
118 free(code->ranges);
119 return ENOMEM;
120 }
121
122 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
123 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
124
125 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
126 code->ranges[0].base = RNGABS(regs);
127
128 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
129
130 ehci_regs_t *registers =
131 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength));
132 code->cmds[0].addr = (void *) &registers->usbsts;
133 code->cmds[3].addr = (void *) &registers->usbsts;
134 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
135
136 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
137 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
138
139 return hw_res->irqs.irqs[0];
140}
141
142/** Initialize EHCI hc driver structure
143 *
144 * @param[in] instance Memory place for the structure.
145 * @param[in] regs Device's I/O registers range.
146 * @param[in] interrupts True if w interrupts should be used
147 * @return Error code
148 */
149int hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
150{
151 hc_t *instance = hcd_to_hc(hcd);
152 assert(hw_res);
153 if (hw_res->mem_ranges.count != 1 ||
154 hw_res->mem_ranges.ranges[0].size <
155 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
156 return EINVAL;
157
158 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
159 (void **)&instance->caps);
160 if (ret != EOK) {
161 usb_log_error("HC(%p): Failed to gain access to device "
162 "registers: %s.\n", instance, str_error(ret));
163 return ret;
164 }
165
166 usb_log_info("HC(%p): Device registers at %"PRIx64" (%zuB) accessible.",
167 instance, hw_res->mem_ranges.ranges[0].address.absolute,
168 hw_res->mem_ranges.ranges[0].size);
169 instance->registers =
170 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
171 usb_log_info("HC(%p): Device control registers at %" PRIx64, instance,
172 hw_res->mem_ranges.ranges[0].address.absolute
173 + EHCI_RD8(instance->caps->caplength));
174
175 list_initialize(&instance->pending_batches);
176 fibril_mutex_initialize(&instance->guard);
177 fibril_condvar_initialize(&instance->async_doorbell);
178
179 ret = hc_init_memory(instance);
180 if (ret != EOK) {
181 usb_log_error("HC(%p): Failed to create EHCI memory structures:"
182 " %s.", instance, str_error(ret));
183 return ret;
184 }
185
186 usb_log_info("HC(%p): Initializing RH(%p).", instance, &instance->rh);
187 ehci_rh_init(
188 &instance->rh, instance->caps, instance->registers, "ehci rh");
189
190 ehci_bus_init(&instance->bus, instance);
191 hc_device_setup(hcd, (bus_t *) &instance->bus);
192 return EOK;
193}
194
195/** Safely dispose host controller internal structures
196 *
197 * @param[in] instance Host controller structure to use.
198 */
199int hc_gone(hc_device_t *hcd)
200{
201 hc_t *hc = hcd_to_hc(hcd);
202 endpoint_list_fini(&hc->async_list);
203 endpoint_list_fini(&hc->int_list);
204 dma_buffer_free(&hc->dma_buffer);
205 return EOK;
206};
207
208void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
209{
210 assert(instance);
211 assert(ep);
212 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
213 usb_log_debug("HC(%p) enqueue EP(%d:%d:%s:%s)\n", instance,
214 ep->device->address, ep->endpoint,
215 usb_str_transfer_type_short(ep->transfer_type),
216 usb_str_direction(ep->direction));
217 switch (ep->transfer_type)
218 {
219 case USB_TRANSFER_CONTROL:
220 case USB_TRANSFER_BULK:
221 endpoint_list_append_ep(&instance->async_list, ehci_ep);
222 break;
223 case USB_TRANSFER_INTERRUPT:
224 endpoint_list_append_ep(&instance->int_list, ehci_ep);
225 break;
226 case USB_TRANSFER_ISOCHRONOUS:
227 /* NOT SUPPORTED */
228 break;
229 }
230}
231
232void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
233{
234 assert(instance);
235 assert(ep);
236 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
237 usb_log_debug("HC(%p) dequeue EP(?:%d:%s:%s)\n", instance,
238 ep->endpoint,
239 usb_str_transfer_type_short(ep->transfer_type),
240 usb_str_direction(ep->direction));
241 switch (ep->transfer_type)
242 {
243 case USB_TRANSFER_INTERRUPT:
244 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
245 /* Fall through */
246 case USB_TRANSFER_ISOCHRONOUS:
247 /* NOT SUPPORTED */
248 return;
249 case USB_TRANSFER_CONTROL:
250 case USB_TRANSFER_BULK:
251 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
252 break;
253 }
254 fibril_mutex_lock(&instance->guard);
255 usb_log_debug("HC(%p): Waiting for doorbell", instance);
256 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
257 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
258 usb_log_debug2("HC(%p): Got doorbell", instance);
259 fibril_mutex_unlock(&instance->guard);
260}
261
262int ehci_hc_status(bus_t *bus_base, uint32_t *status)
263{
264 assert(bus_base);
265 assert(status);
266
267 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
268 hc_t *hc = bus->hc;
269 assert(hc);
270
271 *status = 0;
272 if (hc->registers) {
273 *status = EHCI_RD(hc->registers->usbsts);
274 EHCI_WR(hc->registers->usbsts, *status);
275 }
276 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
277 return EOK;
278}
279
280/** Add USB transfer to the schedule.
281 *
282 * @param[in] hcd HCD driver structure.
283 * @param[in] batch Batch representing the transfer.
284 * @return Error code.
285 */
286int ehci_hc_schedule(usb_transfer_batch_t *batch)
287{
288 assert(batch);
289
290 ehci_bus_t *bus = (ehci_bus_t *) endpoint_get_bus(batch->ep);
291 hc_t *hc = bus->hc;
292 assert(hc);
293
294 /* Check for root hub communication */
295 if (batch->target.address == ehci_rh_get_address(&hc->rh)) {
296 usb_log_debug("HC(%p): Scheduling BATCH(%p) for RH(%p)",
297 hc, batch, &hc->rh);
298 return ehci_rh_schedule(&hc->rh, batch);
299 }
300
301 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
302
303 const int err = ehci_transfer_batch_prepare(ehci_batch);
304 if (err)
305 return err;
306
307 fibril_mutex_lock(&hc->guard);
308 usb_log_debug2("HC(%p): Appending BATCH(%p)", hc, batch);
309 list_append(&ehci_batch->link, &hc->pending_batches);
310 usb_log_debug("HC(%p): Committing BATCH(%p)", hc, batch);
311 ehci_transfer_batch_commit(ehci_batch);
312
313 fibril_mutex_unlock(&hc->guard);
314 return EOK;
315}
316
317/** Interrupt handling routine
318 *
319 * @param[in] hcd HCD driver structure.
320 * @param[in] status Value of the status register at the time of interrupt.
321 */
322void ehci_hc_interrupt(bus_t *bus_base, uint32_t status)
323{
324 assert(bus_base);
325
326 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
327 hc_t *hc = bus->hc;
328 assert(hc);
329
330 usb_log_debug2("HC(%p): Interrupt: %"PRIx32, hc, status);
331 if (status & USB_STS_PORT_CHANGE_FLAG) {
332 ehci_rh_interrupt(&hc->rh);
333 }
334
335 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
336 fibril_mutex_lock(&hc->guard);
337 usb_log_debug2("HC(%p): Signaling doorbell", hc);
338 fibril_condvar_broadcast(&hc->async_doorbell);
339 fibril_mutex_unlock(&hc->guard);
340 }
341
342 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
343 fibril_mutex_lock(&hc->guard);
344
345 usb_log_debug2("HC(%p): Scanning %lu pending batches", hc,
346 list_count(&hc->pending_batches));
347 list_foreach_safe(hc->pending_batches, current, next) {
348 ehci_transfer_batch_t *batch =
349 ehci_transfer_batch_from_link(current);
350
351 if (ehci_transfer_batch_check_completed(batch)) {
352 list_remove(current);
353 usb_transfer_batch_finish(&batch->base);
354 }
355 }
356 fibril_mutex_unlock(&hc->guard);
357 }
358
359 if (status & USB_STS_HOST_ERROR_FLAG) {
360 usb_log_fatal("HCD(%p): HOST SYSTEM ERROR!", hc);
361 //TODO do something here
362 }
363}
364
365/** EHCI hw initialization routine.
366 *
367 * @param[in] instance EHCI hc driver structure.
368 */
369int hc_start(hc_device_t *hcd)
370{
371 hc_t *instance = hcd_to_hc(hcd);
372 usb_log_debug("HC(%p): Starting HW.", instance);
373
374 /* Turn off the HC if it's running, Reseting a running device is
375 * undefined */
376 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
377 /* disable all interrupts */
378 EHCI_WR(instance->registers->usbintr, 0);
379 /* ack all interrupts */
380 EHCI_WR(instance->registers->usbsts, 0x3f);
381 /* Stop HC hw */
382 EHCI_WR(instance->registers->usbcmd, 0);
383 /* Wait until hc is halted */
384 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
385 async_usleep(1);
386 }
387 usb_log_info("HC(%p): EHCI turned off.", instance);
388 } else {
389 usb_log_info("HC(%p): EHCI was not running.", instance);
390 }
391
392 /* Hw initialization sequence, see page 53 (pdf 63) */
393 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
394 usb_log_info("HC(%p): Waiting for HW reset.", instance);
395 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
396 async_usleep(1);
397 }
398 usb_log_debug("HC(%p): HW reset OK.", instance);
399
400 /* Use the lowest 4G segment */
401 EHCI_WR(instance->registers->ctrldssegment, 0);
402
403 /* Enable periodic list */
404 assert(instance->periodic_list);
405 uintptr_t phys_base =
406 addr_to_phys((void*)instance->periodic_list);
407 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
408 EHCI_WR(instance->registers->periodiclistbase, phys_base);
409 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
410 usb_log_debug("HC(%p): Enabled periodic list.", instance);
411
412
413 /* Enable Async schedule */
414 phys_base = addr_to_phys((void*)instance->async_list.list_head);
415 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
416 EHCI_WR(instance->registers->asynclistaddr, phys_base);
417 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
418 usb_log_debug("HC(%p): Enabled async list.", instance);
419
420 /* Start hc and get all ports */
421 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
422 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
423 usb_log_debug("HC(%p): HW started.", instance);
424
425 usb_log_debug2("HC(%p): Registers: \n"
426 "\tUSBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
427 "\tUSBSTS(%p): %x(0x00001000 = HC halted)\n"
428 "\tUSBINT(%p): %x(0x0 = no interrupts).\n"
429 "\tCONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
430 instance,
431 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
432 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
433 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
434 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
435 /* Clear and Enable interrupts */
436 EHCI_WR(instance->registers->usbsts, EHCI_RD(instance->registers->usbsts));
437 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
438
439 return EOK;
440}
441
442/** Initialize memory structures used by the EHCI hcd.
443 *
444 * @param[in] instance EHCI hc driver structure.
445 * @return Error code.
446 */
447int hc_init_memory(hc_t *instance)
448{
449 assert(instance);
450 usb_log_debug2("HC(%p): Initializing Async list(%p).", instance,
451 &instance->async_list);
452 int ret = endpoint_list_init(&instance->async_list, "ASYNC");
453 if (ret != EOK) {
454 usb_log_error("HC(%p): Failed to setup ASYNC list: %s",
455 instance, str_error(ret));
456 return ret;
457 }
458 /* Specs say "Software must set queue head horizontal pointer T-bits to
459 * a zero for queue heads in the asynchronous schedule" (4.4.0).
460 * So we must maintain circular buffer (all horizontal pointers
461 * have to be valid */
462 endpoint_list_chain(&instance->async_list, &instance->async_list);
463
464 usb_log_debug2("HC(%p): Initializing Interrupt list (%p).", instance,
465 &instance->int_list);
466 ret = endpoint_list_init(&instance->int_list, "INT");
467 if (ret != EOK) {
468 usb_log_error("HC(%p): Failed to setup INT list: %s",
469 instance, str_error(ret));
470 endpoint_list_fini(&instance->async_list);
471 return ret;
472 }
473
474 /* Take 1024 periodic list heads, we ignore low mem options */
475 if (dma_buffer_alloc(&instance->dma_buffer, PAGE_SIZE)) {
476 usb_log_error("HC(%p): Failed to get ISO schedule page.",
477 instance);
478 endpoint_list_fini(&instance->async_list);
479 endpoint_list_fini(&instance->int_list);
480 return ENOMEM;
481 }
482 instance->periodic_list = instance->dma_buffer.virt;
483
484 usb_log_debug2("HC(%p): Initializing Periodic list.", instance);
485 for (unsigned i = 0; i < PAGE_SIZE/sizeof(link_pointer_t); ++i)
486 {
487 /* Disable everything for now */
488 instance->periodic_list[i] =
489 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
490 }
491 return EOK;
492}
493
494/**
495 * @}
496 */
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