source: mainline/uspace/drv/bus/usb/ehci/hc.c@ 2896ff6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2896ff6 was 741bcdeb, checked in by Ondřej Hlavatý <aearsis@…>, 8 years ago

WIP usbhost refactoring: ehci completed

vhc to go…
  • Property mode set to 100644
File size: 14.7 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbehcihc
30 * @{
31 */
32/** @file
33 * @brief EHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <stdint.h>
43#include <str_error.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47#include <usb/host/utils/malloc32.h>
48
49#include "ehci_batch.h"
50
51#include "hc.h"
52
53#define EHCI_USED_INTERRUPTS \
54 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
55 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
56
57static const irq_pio_range_t ehci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ehci_regs_t)
61 }
62};
63
64static const irq_cmd_t ehci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static int hc_init_memory(hc_t *instance);
92
93/** Generate IRQ code.
94 * @param[out] ranges PIO ranges buffer.
95 * @param[in] hw_res Device's resources.
96 *
97 * @return Error code.
98 */
99int ehci_hc_gen_irq_code(irq_code_t *code, hcd_t *hcd, const hw_res_list_parsed_t *hw_res)
100{
101 assert(code);
102 assert(hw_res);
103
104 hc_t *instance = hcd_get_driver_data(hcd);
105
106 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
107 return EINVAL;
108
109 addr_range_t regs = hw_res->mem_ranges.ranges[0];
110
111 if (RNGSZ(regs) < sizeof(ehci_regs_t))
112 return EOVERFLOW;
113
114 code->ranges = malloc(sizeof(ehci_pio_ranges));
115 if (code->ranges == NULL)
116 return ENOMEM;
117
118 code->cmds = malloc(sizeof(ehci_irq_commands));
119 if (code->cmds == NULL) {
120 free(code->ranges);
121 return ENOMEM;
122 }
123
124 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
125 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
126
127 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
128 code->ranges[0].base = RNGABS(regs);
129
130 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
131
132 ehci_regs_t *registers =
133 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength));
134 code->cmds[0].addr = (void *) &registers->usbsts;
135 code->cmds[3].addr = (void *) &registers->usbsts;
136 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
137
138 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
139 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
140
141 return hw_res->irqs.irqs[0];
142}
143
144/** Initialize EHCI hc driver structure
145 *
146 * @param[in] instance Memory place for the structure.
147 * @param[in] regs Device's I/O registers range.
148 * @param[in] interrupts True if w interrupts should be used
149 * @return Error code
150 */
151int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res)
152{
153 assert(instance);
154 assert(hw_res);
155 if (hw_res->mem_ranges.count != 1 ||
156 hw_res->mem_ranges.ranges[0].size <
157 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
158 return EINVAL;
159
160 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
161 (void **)&instance->caps);
162 if (ret != EOK) {
163 usb_log_error("HC(%p): Failed to gain access to device "
164 "registers: %s.\n", instance, str_error(ret));
165 return ret;
166 }
167
168 usb_log_info("HC(%p): Device registers at %"PRIx64" (%zuB) accessible.",
169 instance, hw_res->mem_ranges.ranges[0].address.absolute,
170 hw_res->mem_ranges.ranges[0].size);
171 instance->registers =
172 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
173 usb_log_info("HC(%p): Device control registers at %" PRIx64, instance,
174 hw_res->mem_ranges.ranges[0].address.absolute
175 + EHCI_RD8(instance->caps->caplength));
176
177 list_initialize(&instance->pending_batches);
178 fibril_mutex_initialize(&instance->guard);
179 fibril_condvar_initialize(&instance->async_doorbell);
180
181 ret = hc_init_memory(instance);
182 if (ret != EOK) {
183 usb_log_error("HC(%p): Failed to create EHCI memory structures:"
184 " %s.", instance, str_error(ret));
185 return ret;
186 }
187
188 usb_log_info("HC(%p): Initializing RH(%p).", instance, &instance->rh);
189 ehci_rh_init(
190 &instance->rh, instance->caps, instance->registers, "ehci rh");
191
192 ehci_bus_init(&instance->bus, instance);
193 return EOK;
194}
195
196/** Safely dispose host controller internal structures
197 *
198 * @param[in] instance Host controller structure to use.
199 */
200void hc_fini(hc_t *instance)
201{
202 assert(instance);
203 //TODO: stop the hw
204#if 0
205 endpoint_list_fini(&instance->async_list);
206 endpoint_list_fini(&instance->int_list);
207 return_page(instance->periodic_list_base);
208#endif
209};
210
211void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
212{
213 assert(instance);
214 assert(ep);
215 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
216 usb_log_debug("HC(%p) enqueue EP(%d:%d:%s:%s)\n", instance,
217 ep->target.address, ep->target.endpoint,
218 usb_str_transfer_type_short(ep->transfer_type),
219 usb_str_direction(ep->direction));
220 switch (ep->transfer_type)
221 {
222 case USB_TRANSFER_CONTROL:
223 case USB_TRANSFER_BULK:
224 endpoint_list_append_ep(&instance->async_list, ehci_ep);
225 break;
226 case USB_TRANSFER_INTERRUPT:
227 endpoint_list_append_ep(&instance->int_list, ehci_ep);
228 break;
229 case USB_TRANSFER_ISOCHRONOUS:
230 /* NOT SUPPORTED */
231 break;
232 }
233}
234
235void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
236{
237 assert(instance);
238 assert(ep);
239 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
240 usb_log_debug("HC(%p) dequeue EP(%d:%d:%s:%s)\n", instance,
241 ep->target.address, ep->target.endpoint,
242 usb_str_transfer_type_short(ep->transfer_type),
243 usb_str_direction(ep->direction));
244 switch (ep->transfer_type)
245 {
246 case USB_TRANSFER_INTERRUPT:
247 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
248 /* Fall through */
249 case USB_TRANSFER_ISOCHRONOUS:
250 /* NOT SUPPORTED */
251 return;
252 case USB_TRANSFER_CONTROL:
253 case USB_TRANSFER_BULK:
254 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
255 break;
256 }
257 fibril_mutex_lock(&instance->guard);
258 usb_log_debug("HC(%p): Waiting for doorbell", instance);
259 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
260 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
261 usb_log_debug2("HC(%p): Got doorbell", instance);
262 fibril_mutex_unlock(&instance->guard);
263}
264
265int ehci_hc_status(hcd_t *hcd, uint32_t *status)
266{
267 assert(hcd);
268 hc_t *instance = hcd_get_driver_data(hcd);
269 assert(instance);
270 assert(status);
271 *status = 0;
272 if (instance->registers) {
273 *status = EHCI_RD(instance->registers->usbsts);
274 EHCI_WR(instance->registers->usbsts, *status);
275 }
276 usb_log_debug2("HC(%p): Read status: %x", instance, *status);
277 return EOK;
278}
279
280/** Add USB transfer to the schedule.
281 *
282 * @param[in] hcd HCD driver structure.
283 * @param[in] batch Batch representing the transfer.
284 * @return Error code.
285 */
286int ehci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
287{
288 assert(hcd);
289 hc_t *instance = hcd_get_driver_data(hcd);
290 assert(instance);
291
292 /* Check for root hub communication */
293 if (batch->ep->target.address == ehci_rh_get_address(&instance->rh)) {
294 usb_log_debug("HC(%p): Scheduling BATCH(%p) for RH(%p)",
295 instance, batch, &instance->rh);
296 return ehci_rh_schedule(&instance->rh, batch);
297 }
298 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
299 if (!ehci_batch)
300 return ENOMEM;
301
302 fibril_mutex_lock(&instance->guard);
303 usb_log_debug2("HC(%p): Appending BATCH(%p)", instance, batch);
304 list_append(&ehci_batch->link, &instance->pending_batches);
305 usb_log_debug("HC(%p): Committing BATCH(%p)", instance, batch);
306 ehci_transfer_batch_commit(ehci_batch);
307
308 fibril_mutex_unlock(&instance->guard);
309 return EOK;
310}
311
312/** Interrupt handling routine
313 *
314 * @param[in] hcd HCD driver structure.
315 * @param[in] status Value of the status register at the time of interrupt.
316 */
317void ehci_hc_interrupt(hcd_t *hcd, uint32_t status)
318{
319 assert(hcd);
320 hc_t *instance = hcd_get_driver_data(hcd);
321 status = EHCI_RD(status);
322 assert(instance);
323
324 usb_log_debug2("HC(%p): Interrupt: %"PRIx32, instance, status);
325 if (status & USB_STS_PORT_CHANGE_FLAG) {
326 ehci_rh_interrupt(&instance->rh);
327 }
328
329 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
330 fibril_mutex_lock(&instance->guard);
331 usb_log_debug2("HC(%p): Signaling doorbell", instance);
332 fibril_condvar_broadcast(&instance->async_doorbell);
333 fibril_mutex_unlock(&instance->guard);
334 }
335
336 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
337 fibril_mutex_lock(&instance->guard);
338
339 usb_log_debug2("HC(%p): Scanning %lu pending batches", instance,
340 list_count(&instance->pending_batches));
341 list_foreach_safe(instance->pending_batches, current, next) {
342 ehci_transfer_batch_t *batch =
343 ehci_transfer_batch_from_link(current);
344
345 if (ehci_transfer_batch_is_complete(batch)) {
346 list_remove(current);
347 ehci_transfer_batch_finish_dispose(batch);
348 }
349 }
350 fibril_mutex_unlock(&instance->guard);
351 }
352
353 if (status & USB_STS_HOST_ERROR_FLAG) {
354 usb_log_fatal("HCD(%p): HOST SYSTEM ERROR!", instance);
355 //TODO do something here
356 }
357}
358
359/** EHCI hw initialization routine.
360 *
361 * @param[in] instance EHCI hc driver structure.
362 */
363int hc_start(hc_t *instance, bool interrupts)
364{
365 assert(instance);
366 usb_log_debug("HC(%p): Starting HW.", instance);
367
368 /* Turn off the HC if it's running, Reseting a running device is
369 * undefined */
370 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
371 /* disable all interrupts */
372 EHCI_WR(instance->registers->usbintr, 0);
373 /* ack all interrupts */
374 EHCI_WR(instance->registers->usbsts, 0x3f);
375 /* Stop HC hw */
376 EHCI_WR(instance->registers->usbcmd, 0);
377 /* Wait until hc is halted */
378 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
379 async_usleep(1);
380 }
381 usb_log_info("HC(%p): EHCI turned off.", instance);
382 } else {
383 usb_log_info("HC(%p): EHCI was not running.", instance);
384 }
385
386 /* Hw initialization sequence, see page 53 (pdf 63) */
387 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
388 usb_log_info("HC(%p): Waiting for HW reset.", instance);
389 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
390 async_usleep(1);
391 }
392 usb_log_debug("HC(%p): HW reset OK.", instance);
393
394 /* Use the lowest 4G segment */
395 EHCI_WR(instance->registers->ctrldssegment, 0);
396
397 /* Enable periodic list */
398 assert(instance->periodic_list_base);
399 uintptr_t phys_base =
400 addr_to_phys((void*)instance->periodic_list_base);
401 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
402 EHCI_WR(instance->registers->periodiclistbase, phys_base);
403 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
404 usb_log_debug("HC(%p): Enabled periodic list.", instance);
405
406
407 /* Enable Async schedule */
408 phys_base = addr_to_phys((void*)instance->async_list.list_head);
409 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
410 EHCI_WR(instance->registers->asynclistaddr, phys_base);
411 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
412 usb_log_debug("HC(%p): Enabled async list.", instance);
413
414 /* Start hc and get all ports */
415 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
416 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
417 usb_log_debug("HC(%p): HW started.", instance);
418
419 usb_log_debug2("HC(%p): Registers: \n"
420 "\tUSBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
421 "\tUSBSTS(%p): %x(0x00001000 = HC halted)\n"
422 "\tUSBINT(%p): %x(0x0 = no interrupts).\n"
423 "\tCONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
424 instance,
425 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
426 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
427 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
428 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
429 /* Clear and Enable interrupts */
430 EHCI_WR(instance->registers->usbsts, EHCI_RD(instance->registers->usbsts));
431 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
432
433 return EOK;
434}
435
436/** Initialize memory structures used by the EHCI hcd.
437 *
438 * @param[in] instance EHCI hc driver structure.
439 * @return Error code.
440 */
441int hc_init_memory(hc_t *instance)
442{
443 assert(instance);
444 usb_log_debug2("HC(%p): Initializing Async list(%p).", instance,
445 &instance->async_list);
446 int ret = endpoint_list_init(&instance->async_list, "ASYNC");
447 if (ret != EOK) {
448 usb_log_error("HC(%p): Failed to setup ASYNC list: %s",
449 instance, str_error(ret));
450 return ret;
451 }
452 /* Specs say "Software must set queue head horizontal pointer T-bits to
453 * a zero for queue heads in the asynchronous schedule" (4.4.0).
454 * So we must maintain circular buffer (all horizontal pointers
455 * have to be valid */
456 endpoint_list_chain(&instance->async_list, &instance->async_list);
457
458 usb_log_debug2("HC(%p): Initializing Interrupt list (%p).", instance,
459 &instance->int_list);
460 ret = endpoint_list_init(&instance->int_list, "INT");
461 if (ret != EOK) {
462 usb_log_error("HC(%p): Failed to setup INT list: %s",
463 instance, str_error(ret));
464 endpoint_list_fini(&instance->async_list);
465 return ret;
466 }
467
468 /* Take 1024 periodic list heads, we ignore low mem options */
469 instance->periodic_list_base = get_page();
470 if (!instance->periodic_list_base) {
471 usb_log_error("HC(%p): Failed to get ISO schedule page.",
472 instance);
473 endpoint_list_fini(&instance->async_list);
474 endpoint_list_fini(&instance->int_list);
475 return ENOMEM;
476 }
477
478 usb_log_debug2("HC(%p): Initializing Periodic list.", instance);
479 for (unsigned i = 0;
480 i < PAGE_SIZE/sizeof(instance->periodic_list_base[0]); ++i)
481 {
482 /* Disable everything for now */
483 instance->periodic_list_base[i] =
484 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
485 }
486 return EOK;
487}
488
489/**
490 * @}
491 */
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