source: mainline/uspace/drv/bus/usb/ehci/hc.c@ 23e5471

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 23e5471 was bfff7fd, checked in by Jan Vesely <jano.vesely@…>, 12 years ago

ehci: use the same interrupt mask in init and irq code
  • Property mode set to 100644
File size: 12.2 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbehcihc
30 * @{
31 */
32/** @file
33 * @brief EHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <sys/types.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47
48//#include "ehci_endpoint.h"
49//#include "ehci_batch.h"
50#include "utils/malloc32.h"
51
52#include "hc.h"
53
54#define EHCI_USED_INTERRUPTS \
55 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
56 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
57
58static const irq_pio_range_t ehci_pio_ranges[] = {
59 {
60 .base = 0,
61 .size = sizeof(ehci_regs_t)
62 }
63};
64
65static const irq_cmd_t ehci_irq_commands[] = {
66 {
67 .cmd = CMD_PIO_READ_32,
68 .dstarg = 1,
69 .addr = NULL
70 },
71 {
72 .cmd = CMD_AND,
73 .srcarg = 1,
74 .dstarg = 2,
75 .value = 0
76 },
77 {
78 .cmd = CMD_PREDICATE,
79 .srcarg = 2,
80 .value = 2
81 },
82 {
83 .cmd = CMD_PIO_WRITE_A_32,
84 .srcarg = 1,
85 .addr = NULL
86 },
87 {
88 .cmd = CMD_ACCEPT
89 }
90};
91
92static void hc_start(hc_t *instance);
93static int hc_init_memory(hc_t *instance);
94
95/** Generate IRQ code.
96 * @param[out] ranges PIO ranges buffer.
97 * @param[in] hw_res Device's resources.
98 *
99 * @return Error code.
100 */
101int ehci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
102{
103 assert(code);
104 assert(hw_res);
105
106 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
107 return EINVAL;
108
109 addr_range_t regs = hw_res->mem_ranges.ranges[0];
110
111 if (RNGSZ(regs) < sizeof(ehci_regs_t))
112 return EOVERFLOW;
113
114 code->ranges = malloc(sizeof(ehci_pio_ranges));
115 if (code->ranges == NULL)
116 return ENOMEM;
117
118 code->cmds = malloc(sizeof(ehci_irq_commands));
119 if (code->cmds == NULL) {
120 free(code->ranges);
121 return ENOMEM;
122 }
123
124 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
125 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
126
127 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
128 code->ranges[0].base = RNGABS(regs);
129
130 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
131 ehci_caps_regs_t *caps = NULL;
132 int ret = pio_enable_range(&regs, (void**)&caps);
133 if (ret != EOK) {
134 return ret;
135 }
136 ehci_regs_t *registers =
137 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(caps->caplength));
138 code->cmds[0].addr = (void *) &registers->usbsts;
139 code->cmds[3].addr = (void *) &registers->usbsts;
140 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
141
142 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
143 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
144
145 return hw_res->irqs.irqs[0];
146}
147
148/** Initialize EHCI hc driver structure
149 *
150 * @param[in] instance Memory place for the structure.
151 * @param[in] regs Device's I/O registers range.
152 * @param[in] interrupts True if w interrupts should be used
153 * @return Error code
154 */
155int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
156{
157 assert(instance);
158 assert(hw_res);
159 if (hw_res->mem_ranges.count != 1 ||
160 hw_res->mem_ranges.ranges[0].size <
161 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
162 return EINVAL;
163
164 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
165 (void **)&instance->caps);
166 if (ret != EOK) {
167 usb_log_error("Failed to gain access to device registers: %s.\n",
168 str_error(ret));
169 return ret;
170 }
171 usb_log_debug("Device registers at %" PRIx64 " (%zuB) accessible.\n",
172 hw_res->mem_ranges.ranges[0].address.absolute,
173 hw_res->mem_ranges.ranges[0].size);
174 instance->registers =
175 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
176
177 list_initialize(&instance->pending_batches);
178 fibril_mutex_initialize(&instance->guard);
179 fibril_condvar_initialize(&instance->async_doorbell);
180
181 ret = hc_init_memory(instance);
182 if (ret != EOK) {
183 usb_log_error("Failed to create EHCI memory structures: %s.\n",
184 str_error(ret));
185 return ret;
186 }
187
188 ehci_rh_init(
189 &instance->rh, instance->caps, instance->registers, "ehci rh");
190 hc_start(instance);
191
192 return EOK;
193}
194
195/** Safely dispose host controller internal structures
196 *
197 * @param[in] instance Host controller structure to use.
198 */
199void hc_fini(hc_t *instance)
200{
201 assert(instance);
202 //TODO: stop the hw
203#if 0
204 endpoint_list_fini(&instance->async_list);
205 endpoint_list_fini(&instance->int_list);
206 return_page(instance->periodic_list_base);
207#endif
208};
209
210void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
211{
212 assert(instance);
213 assert(ep);
214 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
215 switch (ep->transfer_type)
216 {
217 case USB_TRANSFER_CONTROL:
218 case USB_TRANSFER_BULK:
219 endpoint_list_append_ep(&instance->async_list, ehci_ep);
220 break;
221 case USB_TRANSFER_INTERRUPT:
222 endpoint_list_append_ep(&instance->int_list, ehci_ep);
223 break;
224 case USB_TRANSFER_ISOCHRONOUS:
225 /* NOT SUPPORTED */
226 break;
227 }
228}
229
230void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
231{
232 assert(instance);
233 assert(ep);
234 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
235 switch (ep->transfer_type)
236 {
237 case USB_TRANSFER_INTERRUPT:
238 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
239 /* Fall through */
240 case USB_TRANSFER_ISOCHRONOUS:
241 /* NOT SUPPORTED */
242 return;
243 case USB_TRANSFER_CONTROL:
244 case USB_TRANSFER_BULK:
245 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
246 break;
247 }
248 fibril_mutex_lock(&instance->guard);
249 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
250 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
251 fibril_mutex_unlock(&instance->guard);
252}
253
254int ehci_hc_status(hcd_t *hcd, uint32_t *status)
255{
256 assert(hcd);
257 hc_t *instance = hcd->driver.data;
258 assert(instance);
259 assert(status);
260 *status = 0;
261 if (instance->registers) {
262 *status = EHCI_RD(instance->registers->usbsts);
263 EHCI_WR(instance->registers->usbsts, *status);
264 }
265 return EOK;
266}
267
268/** Add USB transfer to the schedule.
269 *
270 * @param[in] hcd HCD driver structure.
271 * @param[in] batch Batch representing the transfer.
272 * @return Error code.
273 */
274int ehci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
275{
276 assert(hcd);
277 hc_t *instance = hcd->driver.data;
278 assert(instance);
279
280 /* Check for root hub communication */
281 if (batch->ep->address == ehci_rh_get_address(&instance->rh)) {
282 usb_log_debug("EHCI root hub request.\n");
283 return ehci_rh_schedule(&instance->rh, batch);
284 }
285 return ENOTSUP;
286}
287
288/** Interrupt handling routine
289 *
290 * @param[in] hcd HCD driver structure.
291 * @param[in] status Value of the status register at the time of interrupt.
292 */
293void ehci_hc_interrupt(hcd_t *hcd, uint32_t status)
294{
295 assert(hcd);
296 hc_t *instance = hcd->driver.data;
297 status = EHCI_RD(status);
298 assert(instance);
299 if (status & USB_STS_PORT_CHANGE_FLAG) {
300 ehci_rh_interrupt(&instance->rh);
301 }
302 if (status & USB_STS_ASYNC_SCHED_FLAG) {
303 fibril_condvar_signal(&instance->async_doorbell);
304 }
305}
306
307/** EHCI hw initialization routine.
308 *
309 * @param[in] instance EHCI hc driver structure.
310 */
311void hc_start(hc_t *instance)
312{
313 assert(instance);
314 /* Turn of the HC if it's running, Reseting a running device is
315 * undefined */
316 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
317 /* disable all interrupts */
318 EHCI_WR(instance->registers->usbintr, 0);
319 /* ack all interrupts */
320 EHCI_WR(instance->registers->usbsts, 0x3f);
321 /* Stop HC hw */
322 EHCI_WR(instance->registers->usbcmd, 0);
323 /* Wait until hc is halted */
324 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
325 async_usleep(1);
326 }
327 usb_log_info("EHCI turned off.\n");
328 } else {
329 usb_log_info("EHCI was not running.\n");
330 }
331
332 /* Hw initialization sequence, see page 53 (pdf 63) */
333 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
334 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
335 async_usleep(1);
336 }
337 /* Enable interrupts */
338 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
339 /* Use the lowest 4G segment */
340 EHCI_WR(instance->registers->ctrldssegment, 0);
341 /* Set periodic list */
342 assert(instance->periodic_list_base);
343 const uintptr_t phys_base =
344 addr_to_phys((void*)instance->periodic_list_base);
345 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
346 EHCI_WR(instance->registers->periodiclistbase, phys_base);
347
348 /* start hc and get all ports */
349 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
350 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
351
352 /* Enable Async schedule */
353 assert((instance->async_list.list_head_pa & USB_ASYNCLIST_MASK) ==
354 instance->async_list.list_head_pa);
355 EHCI_WR(instance->registers->asynclistaddr,
356 instance->async_list.list_head_pa);
357 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
358#if 0
359 /*
360 * TURN OFF EHCI FOR NOW
361 */
362 usb_log_debug("USBCMD value: %x.\n",
363 EHCI_RD(instance->registers->usbcmd));
364 if (EHCI_RD(instance->registers->usbcmd) & USB_CMD_RUN_FLAG) {
365 /* disable all interrupts */
366 EHCI_WR(instance->registers->usbintr, 0);
367 /* ack all interrupts */
368 EHCI_WR(instance->registers->usbsts, 0x3f);
369 /* release RH ports */
370 EHCI_WR(instance->registers->configflag, 0);
371 EHCI_WR(instance->registers->usbcmd, 0);
372 /* Wait until hc is halted */
373 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0);
374 usb_log_info("EHCI turned off.\n");
375 } else {
376 usb_log_info("EHCI was not running.\n");
377 }
378#endif
379 usb_log_debug("Registers: \n"
380 "\t USBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
381 "\t USBSTS(%p): %x(0x00001000 = HC halted)\n"
382 "\t USBINT(%p): %x(0x0 = no interrupts).\n"
383 "\t CONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
384 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
385 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
386 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
387 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
388}
389
390/** Initialize memory structures used by the EHCI hcd.
391 *
392 * @param[in] instance EHCI hc driver structure.
393 * @return Error code.
394 */
395int hc_init_memory(hc_t *instance)
396{
397 assert(instance);
398 int ret = endpoint_list_init(&instance->async_list, "ASYNC");
399 if (ret != EOK) {
400 usb_log_error("Failed to setup ASYNC list: %s", str_error(ret));
401 return ret;
402 }
403
404 ret = endpoint_list_init(&instance->int_list, "INT");
405 if (ret != EOK) {
406 usb_log_error("Failed to setup INT list: %s", str_error(ret));
407 endpoint_list_fini(&instance->async_list);
408 return ret;
409 }
410 /* Loop async list */
411 endpoint_list_chain(&instance->async_list, &instance->async_list);
412
413 /* Take 1024 periodic list heads, we ignore low mem options */
414 instance->periodic_list_base = get_page();
415 if (!instance->periodic_list_base) {
416 usb_log_error("Failed to get ISO schedule page.");
417 endpoint_list_fini(&instance->async_list);
418 endpoint_list_fini(&instance->int_list);
419 return ENOMEM;
420 }
421 for (unsigned i = 0;
422 i < PAGE_SIZE/sizeof(instance->periodic_list_base[0]); ++i)
423 {
424 /* Disable everything for now */
425 instance->periodic_list_base[i] =
426 LINK_POINTER_QH(instance->int_list.list_head_pa);
427 }
428 return EOK;
429}
430
431/**
432 * @}
433 */
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