source: mainline/uspace/drv/bus/usb/ehci/hc.c@ ce25903

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ce25903 was 45cbf897, checked in by Jan Vesely <jano.vesely@…>, 10 years ago

ehci, libusbhost: Move malloc32 to libusbhost.

So it can be shared with other HCDs.
Make sure the memory is mapped before returning from malloc32.
Add poison.

Fixes non-cntl transfers for ehci
  • Property mode set to 100644
File size: 13.2 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbehcihc
30 * @{
31 */
32/** @file
33 * @brief EHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <sys/types.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47#include <usb/host/utils/malloc32.h>
48
49#include "ehci_batch.h"
50
51#include "hc.h"
52
53#define EHCI_USED_INTERRUPTS \
54 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
55 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
56
57static const irq_pio_range_t ehci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ehci_regs_t)
61 }
62};
63
64static const irq_cmd_t ehci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static void hc_start(hc_t *instance);
92static int hc_init_memory(hc_t *instance);
93
94/** Generate IRQ code.
95 * @param[out] ranges PIO ranges buffer.
96 * @param[in] hw_res Device's resources.
97 *
98 * @return Error code.
99 */
100int ehci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
101{
102 assert(code);
103 assert(hw_res);
104
105 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
106 return EINVAL;
107
108 addr_range_t regs = hw_res->mem_ranges.ranges[0];
109
110 if (RNGSZ(regs) < sizeof(ehci_regs_t))
111 return EOVERFLOW;
112
113 code->ranges = malloc(sizeof(ehci_pio_ranges));
114 if (code->ranges == NULL)
115 return ENOMEM;
116
117 code->cmds = malloc(sizeof(ehci_irq_commands));
118 if (code->cmds == NULL) {
119 free(code->ranges);
120 return ENOMEM;
121 }
122
123 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
124 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
125
126 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
127 code->ranges[0].base = RNGABS(regs);
128
129 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
130 ehci_caps_regs_t *caps = NULL;
131
132 int ret = pio_enable_range(&regs, (void**)&caps);
133 if (ret != EOK) {
134 free(code->ranges);
135 free(code->cmds);
136 return ret;
137 }
138
139 ehci_regs_t *registers =
140 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(caps->caplength));
141 code->cmds[0].addr = (void *) &registers->usbsts;
142 code->cmds[3].addr = (void *) &registers->usbsts;
143 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
144
145 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
146 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
147
148 return hw_res->irqs.irqs[0];
149}
150
151/** Initialize EHCI hc driver structure
152 *
153 * @param[in] instance Memory place for the structure.
154 * @param[in] regs Device's I/O registers range.
155 * @param[in] interrupts True if w interrupts should be used
156 * @return Error code
157 */
158int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
159{
160 assert(instance);
161 assert(hw_res);
162 if (hw_res->mem_ranges.count != 1 ||
163 hw_res->mem_ranges.ranges[0].size <
164 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
165 return EINVAL;
166
167 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
168 (void **)&instance->caps);
169 if (ret != EOK) {
170 usb_log_error("Failed to gain access to device registers: %s.\n",
171 str_error(ret));
172 return ret;
173 }
174 usb_log_info("Device registers at %" PRIx64 " (%zuB) accessible.\n",
175 hw_res->mem_ranges.ranges[0].address.absolute,
176 hw_res->mem_ranges.ranges[0].size);
177 instance->registers =
178 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
179 usb_log_info("Device control registers at %" PRIx64 "\n",
180 hw_res->mem_ranges.ranges[0].address.absolute
181 + EHCI_RD8(instance->caps->caplength));
182
183 list_initialize(&instance->pending_batches);
184 fibril_mutex_initialize(&instance->guard);
185 fibril_condvar_initialize(&instance->async_doorbell);
186
187 ret = hc_init_memory(instance);
188 if (ret != EOK) {
189 usb_log_error("Failed to create EHCI memory structures: %s.\n",
190 str_error(ret));
191 return ret;
192 }
193
194 ehci_rh_init(
195 &instance->rh, instance->caps, instance->registers, "ehci rh");
196 hc_start(instance);
197
198 return EOK;
199}
200
201/** Safely dispose host controller internal structures
202 *
203 * @param[in] instance Host controller structure to use.
204 */
205void hc_fini(hc_t *instance)
206{
207 assert(instance);
208 //TODO: stop the hw
209#if 0
210 endpoint_list_fini(&instance->async_list);
211 endpoint_list_fini(&instance->int_list);
212 return_page(instance->periodic_list_base);
213#endif
214};
215
216void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
217{
218 assert(instance);
219 assert(ep);
220 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
221 usb_log_debug("HCD(%p) enqueue EP(%d:%d:%s:%s)\n", instance,
222 ep->address, ep->endpoint,
223 usb_str_transfer_type_short(ep->transfer_type),
224 usb_str_direction(ep->direction));
225 switch (ep->transfer_type)
226 {
227 case USB_TRANSFER_CONTROL:
228 case USB_TRANSFER_BULK:
229 endpoint_list_append_ep(&instance->async_list, ehci_ep);
230 break;
231 case USB_TRANSFER_INTERRUPT:
232 endpoint_list_append_ep(&instance->int_list, ehci_ep);
233 break;
234 case USB_TRANSFER_ISOCHRONOUS:
235 /* NOT SUPPORTED */
236 break;
237 }
238}
239
240void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
241{
242 assert(instance);
243 assert(ep);
244 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
245 usb_log_debug("HCD(%p) dequeue EP(%d:%d:%s:%s)\n", instance,
246 ep->address, ep->endpoint,
247 usb_str_transfer_type_short(ep->transfer_type),
248 usb_str_direction(ep->direction));
249 switch (ep->transfer_type)
250 {
251 case USB_TRANSFER_INTERRUPT:
252 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
253 /* Fall through */
254 case USB_TRANSFER_ISOCHRONOUS:
255 /* NOT SUPPORTED */
256 return;
257 case USB_TRANSFER_CONTROL:
258 case USB_TRANSFER_BULK:
259 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
260 break;
261 }
262 fibril_mutex_lock(&instance->guard);
263 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
264 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
265 fibril_mutex_unlock(&instance->guard);
266}
267
268int ehci_hc_status(hcd_t *hcd, uint32_t *status)
269{
270 assert(hcd);
271 hc_t *instance = hcd->driver.data;
272 assert(instance);
273 assert(status);
274 *status = 0;
275 if (instance->registers) {
276 *status = EHCI_RD(instance->registers->usbsts);
277 EHCI_WR(instance->registers->usbsts, *status);
278 }
279 return EOK;
280}
281
282/** Add USB transfer to the schedule.
283 *
284 * @param[in] hcd HCD driver structure.
285 * @param[in] batch Batch representing the transfer.
286 * @return Error code.
287 */
288int ehci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
289{
290 assert(hcd);
291 hc_t *instance = hcd->driver.data;
292 assert(instance);
293
294 /* Check for root hub communication */
295 if (batch->ep->address == ehci_rh_get_address(&instance->rh)) {
296 return ehci_rh_schedule(&instance->rh, batch);
297 }
298 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
299 if (!ehci_batch)
300 return ENOMEM;
301
302 fibril_mutex_lock(&instance->guard);
303 list_append(&ehci_batch->link, &instance->pending_batches);
304 ehci_transfer_batch_commit(ehci_batch);
305
306 fibril_mutex_unlock(&instance->guard);
307 return EOK;
308}
309
310/** Interrupt handling routine
311 *
312 * @param[in] hcd HCD driver structure.
313 * @param[in] status Value of the status register at the time of interrupt.
314 */
315void ehci_hc_interrupt(hcd_t *hcd, uint32_t status)
316{
317 assert(hcd);
318 hc_t *instance = hcd->driver.data;
319 status = EHCI_RD(status);
320 assert(instance);
321
322 if (status & USB_STS_PORT_CHANGE_FLAG) {
323 ehci_rh_interrupt(&instance->rh);
324 }
325
326 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
327 fibril_mutex_lock(&instance->guard);
328 fibril_condvar_broadcast(&instance->async_doorbell);
329 fibril_mutex_unlock(&instance->guard);
330 }
331
332 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
333 fibril_mutex_lock(&instance->guard);
334
335 list_foreach_safe(instance->pending_batches, current, next) {
336 ehci_transfer_batch_t *batch =
337 ehci_transfer_batch_from_link(current);
338
339 if (ehci_transfer_batch_is_complete(batch)) {
340 list_remove(current);
341 ehci_transfer_batch_finish_dispose(batch);
342 }
343 }
344 fibril_mutex_unlock(&instance->guard);
345 }
346
347 if (status & USB_STS_HOST_ERROR_FLAG) {
348 usb_log_fatal("HOST CONTROLLER SYSTEM ERROR!\n");
349 //TODO do something here
350 }
351}
352
353/** EHCI hw initialization routine.
354 *
355 * @param[in] instance EHCI hc driver structure.
356 */
357void hc_start(hc_t *instance)
358{
359 assert(instance);
360 /* Turn off the HC if it's running, Reseting a running device is
361 * undefined */
362 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
363 /* disable all interrupts */
364 EHCI_WR(instance->registers->usbintr, 0);
365 /* ack all interrupts */
366 EHCI_WR(instance->registers->usbsts, 0x3f);
367 /* Stop HC hw */
368 EHCI_WR(instance->registers->usbcmd, 0);
369 /* Wait until hc is halted */
370 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
371 async_usleep(1);
372 }
373 usb_log_info("EHCI turned off.\n");
374 } else {
375 usb_log_info("EHCI was not running.\n");
376 }
377
378 /* Hw initialization sequence, see page 53 (pdf 63) */
379 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
380 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
381 async_usleep(1);
382 }
383 /* Enable interrupts */
384 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
385 /* Use the lowest 4G segment */
386 EHCI_WR(instance->registers->ctrldssegment, 0);
387
388 /* Enable periodic list */
389 assert(instance->periodic_list_base);
390 uintptr_t phys_base =
391 addr_to_phys((void*)instance->periodic_list_base);
392 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
393 EHCI_WR(instance->registers->periodiclistbase, phys_base);
394 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
395
396
397 /* Enable Async schedule */
398 phys_base = addr_to_phys((void*)instance->async_list.list_head);
399 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
400 EHCI_WR(instance->registers->asynclistaddr, phys_base);
401 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
402
403 /* Start hc and get all ports */
404 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
405 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
406
407 usb_log_debug("Registers: \n"
408 "\t USBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
409 "\t USBSTS(%p): %x(0x00001000 = HC halted)\n"
410 "\t USBINT(%p): %x(0x0 = no interrupts).\n"
411 "\t CONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
412 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
413 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
414 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
415 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
416}
417
418/** Initialize memory structures used by the EHCI hcd.
419 *
420 * @param[in] instance EHCI hc driver structure.
421 * @return Error code.
422 */
423int hc_init_memory(hc_t *instance)
424{
425 assert(instance);
426 int ret = endpoint_list_init(&instance->async_list, "ASYNC");
427 if (ret != EOK) {
428 usb_log_error("Failed to setup ASYNC list: %s", str_error(ret));
429 return ret;
430 }
431 /* Specs say "Software must set queue head horizontal pointer T-bits to
432 * a zero for queue heads in the asynchronous schedule" (4.4.0).
433 * So we must maintain circular buffer (all horizontal pointers
434 * have to be valid */
435 endpoint_list_chain(&instance->async_list, &instance->async_list);
436
437 ret = endpoint_list_init(&instance->int_list, "INT");
438 if (ret != EOK) {
439 usb_log_error("Failed to setup INT list: %s", str_error(ret));
440 endpoint_list_fini(&instance->async_list);
441 return ret;
442 }
443
444 /* Take 1024 periodic list heads, we ignore low mem options */
445 instance->periodic_list_base = get_page();
446 if (!instance->periodic_list_base) {
447 usb_log_error("Failed to get ISO schedule page.");
448 endpoint_list_fini(&instance->async_list);
449 endpoint_list_fini(&instance->int_list);
450 return ENOMEM;
451 }
452 for (unsigned i = 0;
453 i < PAGE_SIZE/sizeof(instance->periodic_list_base[0]); ++i)
454 {
455 /* Disable everything for now */
456 instance->periodic_list_base[i] =
457 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
458 }
459 return EOK;
460}
461
462/**
463 * @}
464 */
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