source: mainline/uspace/drv/bus/usb/ehci/hc.c@ ac96b11

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ac96b11 was 50362c6, checked in by Jan Vesely <jano.vesely@…>, 10 years ago

ehci, ep list: stop using list_head_pa.
  • Property mode set to 100644
File size: 13.4 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbehcihc
30 * @{
31 */
32/** @file
33 * @brief EHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <str_error.h>
43#include <sys/types.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47
48//#include "ehci_endpoint.h"
49#include "ehci_batch.h"
50#include "utils/malloc32.h"
51
52#include "hc.h"
53
54#define EHCI_USED_INTERRUPTS \
55 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
56 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
57
58static const irq_pio_range_t ehci_pio_ranges[] = {
59 {
60 .base = 0,
61 .size = sizeof(ehci_regs_t)
62 }
63};
64
65static const irq_cmd_t ehci_irq_commands[] = {
66 {
67 .cmd = CMD_PIO_READ_32,
68 .dstarg = 1,
69 .addr = NULL
70 },
71 {
72 .cmd = CMD_AND,
73 .srcarg = 1,
74 .dstarg = 2,
75 .value = 0
76 },
77 {
78 .cmd = CMD_PREDICATE,
79 .srcarg = 2,
80 .value = 2
81 },
82 {
83 .cmd = CMD_PIO_WRITE_A_32,
84 .srcarg = 1,
85 .addr = NULL
86 },
87 {
88 .cmd = CMD_ACCEPT
89 }
90};
91
92static void hc_start(hc_t *instance);
93static int hc_init_memory(hc_t *instance);
94
95/** Generate IRQ code.
96 * @param[out] ranges PIO ranges buffer.
97 * @param[in] hw_res Device's resources.
98 *
99 * @return Error code.
100 */
101int ehci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
102{
103 assert(code);
104 assert(hw_res);
105
106 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
107 return EINVAL;
108
109 addr_range_t regs = hw_res->mem_ranges.ranges[0];
110
111 if (RNGSZ(regs) < sizeof(ehci_regs_t))
112 return EOVERFLOW;
113
114 code->ranges = malloc(sizeof(ehci_pio_ranges));
115 if (code->ranges == NULL)
116 return ENOMEM;
117
118 code->cmds = malloc(sizeof(ehci_irq_commands));
119 if (code->cmds == NULL) {
120 free(code->ranges);
121 return ENOMEM;
122 }
123
124 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
125 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
126
127 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
128 code->ranges[0].base = RNGABS(regs);
129
130 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
131 ehci_caps_regs_t *caps = NULL;
132
133 int ret = pio_enable_range(&regs, (void**)&caps);
134 if (ret != EOK) {
135 free(code->ranges);
136 free(code->cmds);
137 return ret;
138 }
139
140 ehci_regs_t *registers =
141 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(caps->caplength));
142 code->cmds[0].addr = (void *) &registers->usbsts;
143 code->cmds[3].addr = (void *) &registers->usbsts;
144 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
145
146 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
147 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
148
149 return hw_res->irqs.irqs[0];
150}
151
152/** Initialize EHCI hc driver structure
153 *
154 * @param[in] instance Memory place for the structure.
155 * @param[in] regs Device's I/O registers range.
156 * @param[in] interrupts True if w interrupts should be used
157 * @return Error code
158 */
159int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
160{
161 assert(instance);
162 assert(hw_res);
163 if (hw_res->mem_ranges.count != 1 ||
164 hw_res->mem_ranges.ranges[0].size <
165 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
166 return EINVAL;
167
168 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
169 (void **)&instance->caps);
170 if (ret != EOK) {
171 usb_log_error("Failed to gain access to device registers: %s.\n",
172 str_error(ret));
173 return ret;
174 }
175 usb_log_info("Device registers at %" PRIx64 " (%zuB) accessible.\n",
176 hw_res->mem_ranges.ranges[0].address.absolute,
177 hw_res->mem_ranges.ranges[0].size);
178 instance->registers =
179 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
180 usb_log_info("Device control registers at %" PRIx64 "\n",
181 hw_res->mem_ranges.ranges[0].address.absolute
182 + EHCI_RD8(instance->caps->caplength));
183
184 list_initialize(&instance->pending_batches);
185 fibril_mutex_initialize(&instance->guard);
186 fibril_condvar_initialize(&instance->async_doorbell);
187
188 ret = hc_init_memory(instance);
189 if (ret != EOK) {
190 usb_log_error("Failed to create EHCI memory structures: %s.\n",
191 str_error(ret));
192 return ret;
193 }
194
195 ehci_rh_init(
196 &instance->rh, instance->caps, instance->registers, "ehci rh");
197 hc_start(instance);
198
199 return EOK;
200}
201
202/** Safely dispose host controller internal structures
203 *
204 * @param[in] instance Host controller structure to use.
205 */
206void hc_fini(hc_t *instance)
207{
208 assert(instance);
209 //TODO: stop the hw
210#if 0
211 endpoint_list_fini(&instance->async_list);
212 endpoint_list_fini(&instance->int_list);
213 return_page(instance->periodic_list_base);
214#endif
215};
216
217void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
218{
219 assert(instance);
220 assert(ep);
221 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
222 usb_log_debug("HCD(%p) enqueue EP(%d:%d:%s:%s)\n", instance,
223 ep->address, ep->endpoint,
224 usb_str_transfer_type_short(ep->transfer_type),
225 usb_str_direction(ep->direction));
226 switch (ep->transfer_type)
227 {
228 case USB_TRANSFER_CONTROL:
229 case USB_TRANSFER_BULK:
230 endpoint_list_append_ep(&instance->async_list, ehci_ep);
231 break;
232 case USB_TRANSFER_INTERRUPT:
233 endpoint_list_append_ep(&instance->int_list, ehci_ep);
234 break;
235 case USB_TRANSFER_ISOCHRONOUS:
236 /* NOT SUPPORTED */
237 break;
238 }
239}
240
241void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
242{
243 assert(instance);
244 assert(ep);
245 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
246 usb_log_debug("HCD(%p) dequeue EP(%d:%d:%s:%s)\n", instance,
247 ep->address, ep->endpoint,
248 usb_str_transfer_type_short(ep->transfer_type),
249 usb_str_direction(ep->direction));
250 switch (ep->transfer_type)
251 {
252 case USB_TRANSFER_INTERRUPT:
253 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
254 /* Fall through */
255 case USB_TRANSFER_ISOCHRONOUS:
256 /* NOT SUPPORTED */
257 return;
258 case USB_TRANSFER_CONTROL:
259 case USB_TRANSFER_BULK:
260 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
261 break;
262 }
263 fibril_mutex_lock(&instance->guard);
264 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
265 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
266 fibril_mutex_unlock(&instance->guard);
267}
268
269int ehci_hc_status(hcd_t *hcd, uint32_t *status)
270{
271 assert(hcd);
272 hc_t *instance = hcd->driver.data;
273 assert(instance);
274 assert(status);
275 *status = 0;
276 if (instance->registers) {
277 *status = EHCI_RD(instance->registers->usbsts);
278 EHCI_WR(instance->registers->usbsts, *status);
279 }
280 return EOK;
281}
282
283/** Add USB transfer to the schedule.
284 *
285 * @param[in] hcd HCD driver structure.
286 * @param[in] batch Batch representing the transfer.
287 * @return Error code.
288 */
289int ehci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
290{
291 assert(hcd);
292 hc_t *instance = hcd->driver.data;
293 assert(instance);
294
295 /* Check for root hub communication */
296 if (batch->ep->address == ehci_rh_get_address(&instance->rh)) {
297 return ehci_rh_schedule(&instance->rh, batch);
298 }
299 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
300 if (!ehci_batch)
301 return ENOMEM;
302
303 fibril_mutex_lock(&instance->guard);
304 list_append(&ehci_batch->link, &instance->pending_batches);
305 ehci_transfer_batch_commit(ehci_batch);
306
307 fibril_mutex_unlock(&instance->guard);
308 return EOK;
309}
310
311/** Interrupt handling routine
312 *
313 * @param[in] hcd HCD driver structure.
314 * @param[in] status Value of the status register at the time of interrupt.
315 */
316void ehci_hc_interrupt(hcd_t *hcd, uint32_t status)
317{
318 assert(hcd);
319 hc_t *instance = hcd->driver.data;
320 status = EHCI_RD(status);
321 assert(instance);
322
323 if (status & USB_STS_PORT_CHANGE_FLAG) {
324 ehci_rh_interrupt(&instance->rh);
325 }
326
327 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
328 fibril_mutex_lock(&instance->guard);
329 fibril_condvar_broadcast(&instance->async_doorbell);
330 fibril_mutex_unlock(&instance->guard);
331 }
332
333 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
334 fibril_mutex_lock(&instance->guard);
335
336 link_t *current = list_first(&instance->pending_batches);
337 while (current && current != &instance->pending_batches.head) {
338 link_t *next = current->next;
339 ehci_transfer_batch_t *batch =
340 ehci_transfer_batch_from_link(current);
341
342 if (ehci_transfer_batch_is_complete(batch)) {
343 list_remove(current);
344 ehci_transfer_batch_finish_dispose(batch);
345 }
346 current = next;
347 }
348 fibril_mutex_unlock(&instance->guard);
349 }
350
351 if (status & USB_STS_HOST_ERROR_FLAG) {
352 usb_log_fatal("HOST CONTROLLER SYSTEM ERROR!\n");
353 //TODO do something here
354 }
355}
356
357/** EHCI hw initialization routine.
358 *
359 * @param[in] instance EHCI hc driver structure.
360 */
361void hc_start(hc_t *instance)
362{
363 assert(instance);
364 /* Turn off the HC if it's running, Reseting a running device is
365 * undefined */
366 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
367 /* disable all interrupts */
368 EHCI_WR(instance->registers->usbintr, 0);
369 /* ack all interrupts */
370 EHCI_WR(instance->registers->usbsts, 0x3f);
371 /* Stop HC hw */
372 EHCI_WR(instance->registers->usbcmd, 0);
373 /* Wait until hc is halted */
374 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
375 async_usleep(1);
376 }
377 usb_log_info("EHCI turned off.\n");
378 } else {
379 usb_log_info("EHCI was not running.\n");
380 }
381
382 /* Hw initialization sequence, see page 53 (pdf 63) */
383 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
384 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
385 async_usleep(1);
386 }
387 /* Enable interrupts */
388 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
389 /* Use the lowest 4G segment */
390 EHCI_WR(instance->registers->ctrldssegment, 0);
391
392 /* Enable periodic list */
393 assert(instance->periodic_list_base);
394 uintptr_t phys_base =
395 addr_to_phys((void*)instance->periodic_list_base);
396 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
397 EHCI_WR(instance->registers->periodiclistbase, phys_base);
398 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
399
400
401 /* Enable Async schedule */
402 phys_base = addr_to_phys((void*)instance->async_list.list_head);
403 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
404 EHCI_WR(instance->registers->asynclistaddr, phys_base);
405 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
406
407 /* Start hc and get all ports */
408 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
409 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
410
411 usb_log_debug("Registers: \n"
412 "\t USBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
413 "\t USBSTS(%p): %x(0x00001000 = HC halted)\n"
414 "\t USBINT(%p): %x(0x0 = no interrupts).\n"
415 "\t CONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
416 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
417 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
418 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
419 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
420}
421
422/** Initialize memory structures used by the EHCI hcd.
423 *
424 * @param[in] instance EHCI hc driver structure.
425 * @return Error code.
426 */
427int hc_init_memory(hc_t *instance)
428{
429 assert(instance);
430 int ret = endpoint_list_init(&instance->async_list, "ASYNC");
431 if (ret != EOK) {
432 usb_log_error("Failed to setup ASYNC list: %s", str_error(ret));
433 return ret;
434 }
435 /* Specs say "Software must set queue head horizontal pointer T-bits to
436 * a zero for queue heads in the asynchronous schedule" (4.4.0).
437 * So we must maintain circular buffer (all horizontal pointers
438 * have to be valid */
439 endpoint_list_chain(&instance->async_list, &instance->async_list);
440
441 ret = endpoint_list_init(&instance->int_list, "INT");
442 if (ret != EOK) {
443 usb_log_error("Failed to setup INT list: %s", str_error(ret));
444 endpoint_list_fini(&instance->async_list);
445 return ret;
446 }
447
448 /* Take 1024 periodic list heads, we ignore low mem options */
449 instance->periodic_list_base = get_page();
450 if (!instance->periodic_list_base) {
451 usb_log_error("Failed to get ISO schedule page.");
452 endpoint_list_fini(&instance->async_list);
453 endpoint_list_fini(&instance->int_list);
454 return ENOMEM;
455 }
456 for (unsigned i = 0;
457 i < PAGE_SIZE/sizeof(instance->periodic_list_base[0]); ++i)
458 {
459 /* Disable everything for now */
460 instance->periodic_list_base[i] =
461 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
462 }
463 return EOK;
464}
465
466/**
467 * @}
468 */
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