source: mainline/uspace/drv/bus/usb/ehci/hc.c@ 5cbccd4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5cbccd4 was 8d2dd7f2, checked in by Jakub Jermar <jakub@…>, 8 years ago

Reduce the number of files that include <sys/types.h>
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File size: 14.8 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbehcihc
30 * @{
31 */
32/** @file
33 * @brief EHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
42#include <stdint.h>
43#include <str_error.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
47#include <usb/host/utils/malloc32.h>
48
49#include "ehci_batch.h"
50
51#include "hc.h"
52
53#define EHCI_USED_INTERRUPTS \
54 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
55 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
56
57static const irq_pio_range_t ehci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ehci_regs_t)
61 }
62};
63
64static const irq_cmd_t ehci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
91static void hc_start(hc_t *instance);
92static int hc_init_memory(hc_t *instance);
93
94/** Generate IRQ code.
95 * @param[out] ranges PIO ranges buffer.
96 * @param[in] hw_res Device's resources.
97 *
98 * @return Error code.
99 */
100int ehci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res)
101{
102 assert(code);
103 assert(hw_res);
104
105 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
106 return EINVAL;
107
108 addr_range_t regs = hw_res->mem_ranges.ranges[0];
109
110 if (RNGSZ(regs) < sizeof(ehci_regs_t))
111 return EOVERFLOW;
112
113 code->ranges = malloc(sizeof(ehci_pio_ranges));
114 if (code->ranges == NULL)
115 return ENOMEM;
116
117 code->cmds = malloc(sizeof(ehci_irq_commands));
118 if (code->cmds == NULL) {
119 free(code->ranges);
120 return ENOMEM;
121 }
122
123 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
124 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
125
126 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
127 code->ranges[0].base = RNGABS(regs);
128
129 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
130 ehci_caps_regs_t *caps = NULL;
131
132 int ret = pio_enable_range(&regs, (void**)&caps);
133 if (ret != EOK) {
134 free(code->ranges);
135 free(code->cmds);
136 return ret;
137 }
138
139 ehci_regs_t *registers =
140 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(caps->caplength));
141 code->cmds[0].addr = (void *) &registers->usbsts;
142 code->cmds[3].addr = (void *) &registers->usbsts;
143 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
144
145 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n",
146 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
147
148 return hw_res->irqs.irqs[0];
149}
150
151/** Initialize EHCI hc driver structure
152 *
153 * @param[in] instance Memory place for the structure.
154 * @param[in] regs Device's I/O registers range.
155 * @param[in] interrupts True if w interrupts should be used
156 * @return Error code
157 */
158int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interrupts)
159{
160 assert(instance);
161 assert(hw_res);
162 if (hw_res->mem_ranges.count != 1 ||
163 hw_res->mem_ranges.ranges[0].size <
164 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
165 return EINVAL;
166
167 int ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
168 (void **)&instance->caps);
169 if (ret != EOK) {
170 usb_log_error("HC(%p): Failed to gain access to device "
171 "registers: %s.\n", instance, str_error(ret));
172 return ret;
173 }
174 usb_log_info("HC(%p): Device registers at %"PRIx64" (%zuB) accessible.",
175 instance, hw_res->mem_ranges.ranges[0].address.absolute,
176 hw_res->mem_ranges.ranges[0].size);
177 instance->registers =
178 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
179 usb_log_info("HC(%p): Device control registers at %" PRIx64, instance,
180 hw_res->mem_ranges.ranges[0].address.absolute
181 + EHCI_RD8(instance->caps->caplength));
182
183 list_initialize(&instance->pending_batches);
184 fibril_mutex_initialize(&instance->guard);
185 fibril_condvar_initialize(&instance->async_doorbell);
186
187 ret = hc_init_memory(instance);
188 if (ret != EOK) {
189 usb_log_error("HC(%p): Failed to create EHCI memory structures:"
190 " %s.", instance, str_error(ret));
191 return ret;
192 }
193
194 usb_log_info("HC(%p): Initializing RH(%p).", instance, &instance->rh);
195 ehci_rh_init(
196 &instance->rh, instance->caps, instance->registers, "ehci rh");
197 usb_log_debug("HC(%p): Starting HW.", instance);
198 hc_start(instance);
199
200 return EOK;
201}
202
203/** Safely dispose host controller internal structures
204 *
205 * @param[in] instance Host controller structure to use.
206 */
207void hc_fini(hc_t *instance)
208{
209 assert(instance);
210 //TODO: stop the hw
211#if 0
212 endpoint_list_fini(&instance->async_list);
213 endpoint_list_fini(&instance->int_list);
214 return_page(instance->periodic_list_base);
215#endif
216};
217
218void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
219{
220 assert(instance);
221 assert(ep);
222 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
223 usb_log_debug("HC(%p) enqueue EP(%d:%d:%s:%s)\n", instance,
224 ep->address, ep->endpoint,
225 usb_str_transfer_type_short(ep->transfer_type),
226 usb_str_direction(ep->direction));
227 switch (ep->transfer_type)
228 {
229 case USB_TRANSFER_CONTROL:
230 case USB_TRANSFER_BULK:
231 endpoint_list_append_ep(&instance->async_list, ehci_ep);
232 break;
233 case USB_TRANSFER_INTERRUPT:
234 endpoint_list_append_ep(&instance->int_list, ehci_ep);
235 break;
236 case USB_TRANSFER_ISOCHRONOUS:
237 /* NOT SUPPORTED */
238 break;
239 }
240}
241
242void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
243{
244 assert(instance);
245 assert(ep);
246 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
247 usb_log_debug("HC(%p) dequeue EP(%d:%d:%s:%s)\n", instance,
248 ep->address, ep->endpoint,
249 usb_str_transfer_type_short(ep->transfer_type),
250 usb_str_direction(ep->direction));
251 switch (ep->transfer_type)
252 {
253 case USB_TRANSFER_INTERRUPT:
254 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
255 /* Fall through */
256 case USB_TRANSFER_ISOCHRONOUS:
257 /* NOT SUPPORTED */
258 return;
259 case USB_TRANSFER_CONTROL:
260 case USB_TRANSFER_BULK:
261 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
262 break;
263 }
264 fibril_mutex_lock(&instance->guard);
265 usb_log_debug("HC(%p): Waiting for doorbell", instance);
266 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
267 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
268 usb_log_debug2("HC(%p): Got doorbell", instance);
269 fibril_mutex_unlock(&instance->guard);
270}
271
272int ehci_hc_status(hcd_t *hcd, uint32_t *status)
273{
274 assert(hcd);
275 hc_t *instance = hcd_get_driver_data(hcd);
276 assert(instance);
277 assert(status);
278 *status = 0;
279 if (instance->registers) {
280 *status = EHCI_RD(instance->registers->usbsts);
281 EHCI_WR(instance->registers->usbsts, *status);
282 }
283 usb_log_debug2("HC(%p): Read status: %x", instance, *status);
284 return EOK;
285}
286
287/** Add USB transfer to the schedule.
288 *
289 * @param[in] hcd HCD driver structure.
290 * @param[in] batch Batch representing the transfer.
291 * @return Error code.
292 */
293int ehci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
294{
295 assert(hcd);
296 hc_t *instance = hcd_get_driver_data(hcd);
297 assert(instance);
298
299 /* Check for root hub communication */
300 if (batch->ep->address == ehci_rh_get_address(&instance->rh)) {
301 usb_log_debug("HC(%p): Scheduling BATCH(%p) for RH(%p)",
302 instance, batch, &instance->rh);
303 return ehci_rh_schedule(&instance->rh, batch);
304 }
305 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
306 if (!ehci_batch)
307 return ENOMEM;
308
309 fibril_mutex_lock(&instance->guard);
310 usb_log_debug2("HC(%p): Appending BATCH(%p)", instance, batch);
311 list_append(&ehci_batch->link, &instance->pending_batches);
312 usb_log_debug("HC(%p): Committing BATCH(%p)", instance, batch);
313 ehci_transfer_batch_commit(ehci_batch);
314
315 fibril_mutex_unlock(&instance->guard);
316 return EOK;
317}
318
319/** Interrupt handling routine
320 *
321 * @param[in] hcd HCD driver structure.
322 * @param[in] status Value of the status register at the time of interrupt.
323 */
324void ehci_hc_interrupt(hcd_t *hcd, uint32_t status)
325{
326 assert(hcd);
327 hc_t *instance = hcd_get_driver_data(hcd);
328 status = EHCI_RD(status);
329 assert(instance);
330
331 usb_log_debug2("HC(%p): Interrupt: %"PRIx32, instance, status);
332 if (status & USB_STS_PORT_CHANGE_FLAG) {
333 ehci_rh_interrupt(&instance->rh);
334 }
335
336 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
337 fibril_mutex_lock(&instance->guard);
338 usb_log_debug2("HC(%p): Signaling doorbell", instance);
339 fibril_condvar_broadcast(&instance->async_doorbell);
340 fibril_mutex_unlock(&instance->guard);
341 }
342
343 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
344 fibril_mutex_lock(&instance->guard);
345
346 usb_log_debug2("HC(%p): Scanning %lu pending batches", instance,
347 list_count(&instance->pending_batches));
348 list_foreach_safe(instance->pending_batches, current, next) {
349 ehci_transfer_batch_t *batch =
350 ehci_transfer_batch_from_link(current);
351
352 if (ehci_transfer_batch_is_complete(batch)) {
353 list_remove(current);
354 ehci_transfer_batch_finish_dispose(batch);
355 }
356 }
357 fibril_mutex_unlock(&instance->guard);
358 }
359
360 if (status & USB_STS_HOST_ERROR_FLAG) {
361 usb_log_fatal("HCD(%p): HOST SYSTEM ERROR!", instance);
362 //TODO do something here
363 }
364}
365
366/** EHCI hw initialization routine.
367 *
368 * @param[in] instance EHCI hc driver structure.
369 */
370void hc_start(hc_t *instance)
371{
372 assert(instance);
373 /* Turn off the HC if it's running, Reseting a running device is
374 * undefined */
375 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
376 /* disable all interrupts */
377 EHCI_WR(instance->registers->usbintr, 0);
378 /* ack all interrupts */
379 EHCI_WR(instance->registers->usbsts, 0x3f);
380 /* Stop HC hw */
381 EHCI_WR(instance->registers->usbcmd, 0);
382 /* Wait until hc is halted */
383 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
384 async_usleep(1);
385 }
386 usb_log_info("HC(%p): EHCI turned off.", instance);
387 } else {
388 usb_log_info("HC(%p): EHCI was not running.", instance);
389 }
390
391 /* Hw initialization sequence, see page 53 (pdf 63) */
392 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
393 usb_log_info("HC(%p): Waiting for HW reset.", instance);
394 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
395 async_usleep(1);
396 }
397 usb_log_debug("HC(%p): HW reset OK.", instance);
398
399 /* Use the lowest 4G segment */
400 EHCI_WR(instance->registers->ctrldssegment, 0);
401
402 /* Enable periodic list */
403 assert(instance->periodic_list_base);
404 uintptr_t phys_base =
405 addr_to_phys((void*)instance->periodic_list_base);
406 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
407 EHCI_WR(instance->registers->periodiclistbase, phys_base);
408 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
409 usb_log_debug("HC(%p): Enabled periodic list.", instance);
410
411
412 /* Enable Async schedule */
413 phys_base = addr_to_phys((void*)instance->async_list.list_head);
414 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
415 EHCI_WR(instance->registers->asynclistaddr, phys_base);
416 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
417 usb_log_debug("HC(%p): Enabled async list.", instance);
418
419 /* Start hc and get all ports */
420 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
421 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
422 usb_log_debug("HC(%p): HW started.", instance);
423
424 usb_log_debug2("HC(%p): Registers: \n"
425 "\tUSBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)\n"
426 "\tUSBSTS(%p): %x(0x00001000 = HC halted)\n"
427 "\tUSBINT(%p): %x(0x0 = no interrupts).\n"
428 "\tCONFIG(%p): %x(0x0 = ports controlled by companion hc).\n",
429 instance,
430 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
431 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
432 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
433 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
434 /* Clear and Enable interrupts */
435 EHCI_WR(instance->registers->usbsts, EHCI_RD(instance->registers->usbsts));
436 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
437}
438
439/** Initialize memory structures used by the EHCI hcd.
440 *
441 * @param[in] instance EHCI hc driver structure.
442 * @return Error code.
443 */
444int hc_init_memory(hc_t *instance)
445{
446 assert(instance);
447 usb_log_debug2("HC(%p): Initializing Async list(%p).", instance,
448 &instance->async_list);
449 int ret = endpoint_list_init(&instance->async_list, "ASYNC");
450 if (ret != EOK) {
451 usb_log_error("HC(%p): Failed to setup ASYNC list: %s",
452 instance, str_error(ret));
453 return ret;
454 }
455 /* Specs say "Software must set queue head horizontal pointer T-bits to
456 * a zero for queue heads in the asynchronous schedule" (4.4.0).
457 * So we must maintain circular buffer (all horizontal pointers
458 * have to be valid */
459 endpoint_list_chain(&instance->async_list, &instance->async_list);
460
461 usb_log_debug2("HC(%p): Initializing Interrupt list (%p).", instance,
462 &instance->int_list);
463 ret = endpoint_list_init(&instance->int_list, "INT");
464 if (ret != EOK) {
465 usb_log_error("HC(%p): Failed to setup INT list: %s",
466 instance, str_error(ret));
467 endpoint_list_fini(&instance->async_list);
468 return ret;
469 }
470
471 /* Take 1024 periodic list heads, we ignore low mem options */
472 instance->periodic_list_base = get_page();
473 if (!instance->periodic_list_base) {
474 usb_log_error("HC(%p): Failed to get ISO schedule page.",
475 instance);
476 endpoint_list_fini(&instance->async_list);
477 endpoint_list_fini(&instance->int_list);
478 return ENOMEM;
479 }
480
481 usb_log_debug2("HC(%p): Initializing Periodic list.", instance);
482 for (unsigned i = 0;
483 i < PAGE_SIZE/sizeof(instance->periodic_list_base[0]); ++i)
484 {
485 /* Disable everything for now */
486 instance->periodic_list_base[i] =
487 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
488 }
489 return EOK;
490}
491
492/**
493 * @}
494 */
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