source: mainline/uspace/drv/bus/usb/ehci/hc.c@ 2ca5a198

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2ca5a198 was 5a6cc679, checked in by Jenda <jenda.jzqk73@…>, 8 years ago

Merge commit '50f19b7ee8e94570b5c63896736c4eb49cfa18db' into forwardport

Not all ints are converted to errno_t in xhci tree yet, however it compiles and works :)

  • Property mode set to 100644
File size: 15.3 KB
RevLine 
[6297465]1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbehcihc
30 * @{
31 */
32/** @file
33 * @brief EHCI Host controller driver routines
34 */
35
36#include <assert.h>
37#include <async.h>
38#include <errno.h>
39#include <macros.h>
40#include <mem.h>
41#include <stdlib.h>
[8d2dd7f2]42#include <stdint.h>
[6297465]43#include <str_error.h>
44
45#include <usb/debug.h>
46#include <usb/usb.h>
[c6f82e5]47#include <usb/host/utility.h>
[6297465]48
[e9c5bd9]49#include "ehci_batch.h"
[6297465]50
51#include "hc.h"
52
53#define EHCI_USED_INTERRUPTS \
[bfff7fd]54 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
55 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
[6297465]56
57static const irq_pio_range_t ehci_pio_ranges[] = {
58 {
59 .base = 0,
60 .size = sizeof(ehci_regs_t)
61 }
62};
63
64static const irq_cmd_t ehci_irq_commands[] = {
65 {
66 .cmd = CMD_PIO_READ_32,
67 .dstarg = 1,
68 .addr = NULL
69 },
70 {
71 .cmd = CMD_AND,
72 .srcarg = 1,
73 .dstarg = 2,
74 .value = 0
75 },
76 {
77 .cmd = CMD_PREDICATE,
78 .srcarg = 2,
79 .value = 2
80 },
81 {
82 .cmd = CMD_PIO_WRITE_A_32,
83 .srcarg = 1,
84 .addr = NULL
85 },
86 {
87 .cmd = CMD_ACCEPT
88 }
89};
90
[5a6cc679]91static errno_t hc_init_memory(hc_t *instance);
[6297465]92
93/** Generate IRQ code.
94 * @param[out] ranges PIO ranges buffer.
[ba4a03a5]95 * @param[in] hw_res Device's resources.
[6297465]96 *
[68e5406]97 * @param[out] irq
98 *
[6297465]99 * @return Error code.
100 */
[5a6cc679]101errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
[6297465]102{
103 assert(code);
[ba4a03a5]104 assert(hw_res);
[32fb6bce]105 hc_t *instance = hcd_to_hc(hcd);
[e4d7363]106
[ba4a03a5]107 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
108 return EINVAL;
109
110 addr_range_t regs = hw_res->mem_ranges.ranges[0];
111
112 if (RNGSZ(regs) < sizeof(ehci_regs_t))
[6297465]113 return EOVERFLOW;
114
115 code->ranges = malloc(sizeof(ehci_pio_ranges));
116 if (code->ranges == NULL)
117 return ENOMEM;
118
119 code->cmds = malloc(sizeof(ehci_irq_commands));
120 if (code->cmds == NULL) {
121 free(code->ranges);
122 return ENOMEM;
123 }
124
125 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
126 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
127
128 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
[ba4a03a5]129 code->ranges[0].base = RNGABS(regs);
[6297465]130
131 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
[dca8fe5]132
[d09d108]133 ehci_regs_t *registers =
134 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength));
135 code->cmds[0].addr = (void *) &registers->usbsts;
136 code->cmds[3].addr = (void *) &registers->usbsts;
[6297465]137 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
138
[a1732929]139 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
[ba4a03a5]140 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
141
[68e5406]142 *irq = hw_res->irqs.irqs[0];
143 return EOK;
[6297465]144}
145
146/** Initialize EHCI hc driver structure
147 *
148 * @param[in] instance Memory place for the structure.
149 * @param[in] regs Device's I/O registers range.
150 * @param[in] interrupts True if w interrupts should be used
151 * @return Error code
152 */
[5a6cc679]153errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
[6297465]154{
[32fb6bce]155 hc_t *instance = hcd_to_hc(hcd);
[7813516]156 assert(hw_res);
157 if (hw_res->mem_ranges.count != 1 ||
158 hw_res->mem_ranges.ranges[0].size <
159 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
160 return EINVAL;
[6297465]161
[5a6cc679]162 errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
[7813516]163 (void **)&instance->caps);
[6297465]164 if (ret != EOK) {
[05b51e37]165 usb_log_error("HC(%p): Failed to gain access to device "
[a1732929]166 "registers: %s.", instance, str_error(ret));
[6297465]167 return ret;
168 }
[e4d7363]169
[05b51e37]170 usb_log_info("HC(%p): Device registers at %"PRIx64" (%zuB) accessible.",
171 instance, hw_res->mem_ranges.ranges[0].address.absolute,
[7813516]172 hw_res->mem_ranges.ranges[0].size);
[6297465]173 instance->registers =
174 (void*)instance->caps + EHCI_RD8(instance->caps->caplength);
[05b51e37]175 usb_log_info("HC(%p): Device control registers at %" PRIx64, instance,
[d97f91f]176 hw_res->mem_ranges.ranges[0].address.absolute
177 + EHCI_RD8(instance->caps->caplength));
[6297465]178
[8ad2b0a]179 list_initialize(&instance->pending_endpoints);
[6297465]180 fibril_mutex_initialize(&instance->guard);
[763dbcb]181 fibril_condvar_initialize(&instance->async_doorbell);
[6297465]182
183 ret = hc_init_memory(instance);
184 if (ret != EOK) {
[05b51e37]185 usb_log_error("HC(%p): Failed to create EHCI memory structures:"
186 " %s.", instance, str_error(ret));
[6297465]187 return ret;
188 }
189
[05b51e37]190 usb_log_info("HC(%p): Initializing RH(%p).", instance, &instance->rh);
[6297465]191 ehci_rh_init(
[ddbd088]192 &instance->rh, instance->caps, instance->registers, &instance->guard,
193 "ehci rh");
[6297465]194
[32fb6bce]195 ehci_bus_init(&instance->bus, instance);
196 hc_device_setup(hcd, (bus_t *) &instance->bus);
[6297465]197 return EOK;
198}
199
[7813516]200/** Safely dispose host controller internal structures
201 *
202 * @param[in] instance Host controller structure to use.
203 */
[35c37fc]204int hc_gone(hc_device_t *hcd)
[7813516]205{
[35c37fc]206 hc_t *hc = hcd_to_hc(hcd);
207 endpoint_list_fini(&hc->async_list);
208 endpoint_list_fini(&hc->int_list);
209 dma_buffer_free(&hc->dma_buffer);
[32fb6bce]210 return EOK;
[7813516]211};
212
[6297465]213void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
214{
[5f5321ee]215 assert(instance);
216 assert(ep);
217 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
[a1732929]218 usb_log_debug("HC(%p) enqueue EP(%d:%d:%s:%s)", instance,
[a5b3de6]219 ep->device->address, ep->endpoint,
[92900e2]220 usb_str_transfer_type_short(ep->transfer_type),
221 usb_str_direction(ep->direction));
[5f5321ee]222 switch (ep->transfer_type)
223 {
224 case USB_TRANSFER_CONTROL:
225 case USB_TRANSFER_BULK:
226 endpoint_list_append_ep(&instance->async_list, ehci_ep);
227 break;
228 case USB_TRANSFER_INTERRUPT:
229 endpoint_list_append_ep(&instance->int_list, ehci_ep);
230 break;
231 case USB_TRANSFER_ISOCHRONOUS:
232 /* NOT SUPPORTED */
233 break;
234 }
[6297465]235}
236
237void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
238{
[763dbcb]239 assert(instance);
240 assert(ep);
241 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
[7278cbc9]242 usb_log_debug("HC(%p) dequeue EP(%d:%d:%s:%s)", instance,
243 ep->device->address, ep->endpoint,
[92900e2]244 usb_str_transfer_type_short(ep->transfer_type),
245 usb_str_direction(ep->direction));
[763dbcb]246 switch (ep->transfer_type)
247 {
248 case USB_TRANSFER_INTERRUPT:
[ce735cc2]249 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
[763dbcb]250 /* Fall through */
251 case USB_TRANSFER_ISOCHRONOUS:
252 /* NOT SUPPORTED */
253 return;
254 case USB_TRANSFER_CONTROL:
255 case USB_TRANSFER_BULK:
256 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
257 break;
258 }
259 fibril_mutex_lock(&instance->guard);
[05b51e37]260 usb_log_debug("HC(%p): Waiting for doorbell", instance);
[1803b7d]261 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
[763dbcb]262 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
[05b51e37]263 usb_log_debug2("HC(%p): Got doorbell", instance);
[763dbcb]264 fibril_mutex_unlock(&instance->guard);
[6297465]265}
266
[5a6cc679]267errno_t ehci_hc_status(bus_t *bus_base, uint32_t *status)
[c9e954c]268{
[32fb6bce]269 assert(bus_base);
[c9e954c]270 assert(status);
[32fb6bce]271
272 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
273 hc_t *hc = bus->hc;
274 assert(hc);
275
[c9e954c]276 *status = 0;
[32fb6bce]277 if (hc->registers) {
278 *status = EHCI_RD(hc->registers->usbsts);
279 EHCI_WR(hc->registers->usbsts, *status);
[c9e954c]280 }
[32fb6bce]281 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
[c9e954c]282 return EOK;
283}
284
[6297465]285/** Add USB transfer to the schedule.
286 *
[c9e954c]287 * @param[in] hcd HCD driver structure.
[6297465]288 * @param[in] batch Batch representing the transfer.
289 * @return Error code.
290 */
[5a6cc679]291errno_t ehci_hc_schedule(usb_transfer_batch_t *batch)
[6297465]292{
[32fb6bce]293 assert(batch);
294
295 ehci_bus_t *bus = (ehci_bus_t *) endpoint_get_bus(batch->ep);
296 hc_t *hc = bus->hc;
297 assert(hc);
[6297465]298
299 /* Check for root hub communication */
[32fb6bce]300 if (batch->target.address == ehci_rh_get_address(&hc->rh)) {
[05b51e37]301 usb_log_debug("HC(%p): Scheduling BATCH(%p) for RH(%p)",
[32fb6bce]302 hc, batch, &hc->rh);
303 return ehci_rh_schedule(&hc->rh, batch);
[6297465]304 }
[5fd9c30]305
[8ad2b0a]306 endpoint_t * const ep = batch->ep;
307 ehci_endpoint_t * const ehci_ep = ehci_endpoint_get(ep);
[4db49344]308 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
[8ad2b0a]309
[4db49344]310 int err;
[5fd9c30]311
[4db49344]312 if ((err = ehci_transfer_batch_prepare(ehci_batch)))
313 return err;
[8ad2b0a]314
[4db49344]315 fibril_mutex_lock(&hc->guard);
316
317 if ((err = endpoint_activate_locked(ep, batch))) {
318 fibril_mutex_unlock(&hc->guard);
[5fd9c30]319 return err;
[8ad2b0a]320 }
[e9c5bd9]321
[32fb6bce]322 usb_log_debug("HC(%p): Committing BATCH(%p)", hc, batch);
[e9c5bd9]323 ehci_transfer_batch_commit(ehci_batch);
[8ad2b0a]324
325 /* Enqueue endpoint to the checked list */
326 usb_log_debug2("HC(%p): Appending BATCH(%p)", hc, batch);
327 list_append(&ehci_ep->pending_link, &hc->pending_endpoints);
328
[4db49344]329 fibril_mutex_unlock(&hc->guard);
[e9c5bd9]330 return EOK;
[6297465]331}
332
333/** Interrupt handling routine
334 *
[c9e954c]335 * @param[in] hcd HCD driver structure.
[6297465]336 * @param[in] status Value of the status register at the time of interrupt.
337 */
[32fb6bce]338void ehci_hc_interrupt(bus_t *bus_base, uint32_t status)
[6297465]339{
[32fb6bce]340 assert(bus_base);
341
342 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
343 hc_t *hc = bus->hc;
344 assert(hc);
[07645906]345
[32fb6bce]346 usb_log_debug2("HC(%p): Interrupt: %"PRIx32, hc, status);
[6297465]347 if (status & USB_STS_PORT_CHANGE_FLAG) {
[32fb6bce]348 ehci_rh_interrupt(&hc->rh);
[6297465]349 }
[07645906]350
[580b330]351 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
[32fb6bce]352 fibril_mutex_lock(&hc->guard);
353 usb_log_debug2("HC(%p): Signaling doorbell", hc);
354 fibril_condvar_broadcast(&hc->async_doorbell);
355 fibril_mutex_unlock(&hc->guard);
[763dbcb]356 }
[07645906]357
[e9c5bd9]358 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
[32fb6bce]359 fibril_mutex_lock(&hc->guard);
[e9c5bd9]360
[8ad2b0a]361 usb_log_debug2("HC(%p): Scanning %lu pending endpoints", hc,
362 list_count(&hc->pending_endpoints));
363 list_foreach_safe(hc->pending_endpoints, current, next) {
364 ehci_endpoint_t *ep
365 = list_get_instance(current, ehci_endpoint_t, pending_link);
366
367 ehci_transfer_batch_t *batch
368 = ehci_transfer_batch_get(ep->base.active_batch);
369 assert(batch);
[e9c5bd9]370
[5fd9c30]371 if (ehci_transfer_batch_check_completed(batch)) {
[8ad2b0a]372 endpoint_deactivate_locked(&ep->base);
[e9c5bd9]373 list_remove(current);
[c6f82e5]374 hc_reset_toggles(&batch->base, &ehci_ep_toggle_reset);
[5fd9c30]375 usb_transfer_batch_finish(&batch->base);
[e9c5bd9]376 }
377 }
[32fb6bce]378 fibril_mutex_unlock(&hc->guard);
[8ad2b0a]379
380
[e9c5bd9]381 }
382
[07645906]383 if (status & USB_STS_HOST_ERROR_FLAG) {
[32fb6bce]384 usb_log_fatal("HCD(%p): HOST SYSTEM ERROR!", hc);
[07645906]385 //TODO do something here
386 }
[6297465]387}
388
389/** EHCI hw initialization routine.
390 *
391 * @param[in] instance EHCI hc driver structure.
392 */
[32fb6bce]393int hc_start(hc_device_t *hcd)
[6297465]394{
[32fb6bce]395 hc_t *instance = hcd_to_hc(hcd);
[e4d7363]396 usb_log_debug("HC(%p): Starting HW.", instance);
397
[3eb0c85]398 /* Turn off the HC if it's running, Reseting a running device is
[478e243]399 * undefined */
400 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
401 /* disable all interrupts */
402 EHCI_WR(instance->registers->usbintr, 0);
403 /* ack all interrupts */
404 EHCI_WR(instance->registers->usbsts, 0x3f);
405 /* Stop HC hw */
406 EHCI_WR(instance->registers->usbcmd, 0);
407 /* Wait until hc is halted */
408 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
409 async_usleep(1);
410 }
[05b51e37]411 usb_log_info("HC(%p): EHCI turned off.", instance);
[478e243]412 } else {
[05b51e37]413 usb_log_info("HC(%p): EHCI was not running.", instance);
[478e243]414 }
415
416 /* Hw initialization sequence, see page 53 (pdf 63) */
417 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
[05b51e37]418 usb_log_info("HC(%p): Waiting for HW reset.", instance);
[478e243]419 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
420 async_usleep(1);
421 }
[05b51e37]422 usb_log_debug("HC(%p): HW reset OK.", instance);
423
[763dbcb]424 /* Use the lowest 4G segment */
[478e243]425 EHCI_WR(instance->registers->ctrldssegment, 0);
[3eb0c85]426
427 /* Enable periodic list */
[35c37fc]428 assert(instance->periodic_list);
[50362c6]429 uintptr_t phys_base =
[35c37fc]430 addr_to_phys((void*)instance->periodic_list);
[478e243]431 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
432 EHCI_WR(instance->registers->periodiclistbase, phys_base);
[44b9b44]433 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
[05b51e37]434 usb_log_debug("HC(%p): Enabled periodic list.", instance);
[478e243]435
[763dbcb]436
[0a751aa]437 /* Enable Async schedule */
[50362c6]438 phys_base = addr_to_phys((void*)instance->async_list.list_head);
439 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
440 EHCI_WR(instance->registers->asynclistaddr, phys_base);
[0a751aa]441 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
[05b51e37]442 usb_log_debug("HC(%p): Enabled async list.", instance);
[44b9b44]443
[3eb0c85]444 /* Start hc and get all ports */
[44b9b44]445 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
446 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
[05b51e37]447 usb_log_debug("HC(%p): HW started.", instance);
448
[a1732929]449 usb_log_debug2("HC(%p): Registers: "
450 "\tUSBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)"
451 "\tUSBSTS(%p): %x(0x00001000 = HC halted)"
452 "\tUSBINT(%p): %x(0x0 = no interrupts)."
453 "\tCONFIG(%p): %x(0x0 = ports controlled by companion hc).",
[05b51e37]454 instance,
[615abda]455 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
456 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
457 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
458 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
[495547d]459 /* Clear and Enable interrupts */
460 EHCI_WR(instance->registers->usbsts, EHCI_RD(instance->registers->usbsts));
461 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
[e4d7363]462
463 return EOK;
[6297465]464}
465
[129b821f]466/**
467 * Setup roothub as a virtual hub.
468 */
469int hc_setup_roothub(hc_device_t *hcd)
470{
471 return hc_setup_virtual_root_hub(hcd, USB_SPEED_HIGH);
472}
473
[6297465]474/** Initialize memory structures used by the EHCI hcd.
475 *
476 * @param[in] instance EHCI hc driver structure.
477 * @return Error code.
478 */
[5a6cc679]479errno_t hc_init_memory(hc_t *instance)
[6297465]480{
[478e243]481 assert(instance);
[05b51e37]482 usb_log_debug2("HC(%p): Initializing Async list(%p).", instance,
483 &instance->async_list);
[5a6cc679]484 errno_t ret = endpoint_list_init(&instance->async_list, "ASYNC");
[5f5321ee]485 if (ret != EOK) {
[05b51e37]486 usb_log_error("HC(%p): Failed to setup ASYNC list: %s",
487 instance, str_error(ret));
[5f5321ee]488 return ret;
489 }
[50362c6]490 /* Specs say "Software must set queue head horizontal pointer T-bits to
491 * a zero for queue heads in the asynchronous schedule" (4.4.0).
492 * So we must maintain circular buffer (all horizontal pointers
493 * have to be valid */
494 endpoint_list_chain(&instance->async_list, &instance->async_list);
[5f5321ee]495
[05b51e37]496 usb_log_debug2("HC(%p): Initializing Interrupt list (%p).", instance,
497 &instance->int_list);
[5f5321ee]498 ret = endpoint_list_init(&instance->int_list, "INT");
499 if (ret != EOK) {
[05b51e37]500 usb_log_error("HC(%p): Failed to setup INT list: %s",
501 instance, str_error(ret));
[5f5321ee]502 endpoint_list_fini(&instance->async_list);
503 return ret;
504 }
[478e243]505
506 /* Take 1024 periodic list heads, we ignore low mem options */
[35c37fc]507 if (dma_buffer_alloc(&instance->dma_buffer, PAGE_SIZE)) {
[05b51e37]508 usb_log_error("HC(%p): Failed to get ISO schedule page.",
509 instance);
[5f5321ee]510 endpoint_list_fini(&instance->async_list);
511 endpoint_list_fini(&instance->int_list);
[478e243]512 return ENOMEM;
[5f5321ee]513 }
[35c37fc]514 instance->periodic_list = instance->dma_buffer.virt;
[05b51e37]515
516 usb_log_debug2("HC(%p): Initializing Periodic list.", instance);
[35c37fc]517 for (unsigned i = 0; i < PAGE_SIZE/sizeof(link_pointer_t); ++i)
[478e243]518 {
519 /* Disable everything for now */
[35c37fc]520 instance->periodic_list[i] =
[50362c6]521 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
[478e243]522 }
[6297465]523 return EOK;
524}
525
526/**
527 * @}
528 */
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