source: mainline/uspace/drv/bus/usb/ehci/hc.c

Last change on this file was 9dfb034, checked in by Jiri Svoboda <jiri@…>, 4 months ago

Implement quiesce for EHCI and OHCI.

  • Property mode set to 100644
File size: 16.5 KB
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[6297465]1/*
[9dfb034]2 * Copyright (c) 2025 Jiri Svoboda
[6297465]3 * Copyright (c) 2011 Jan Vesely
[e0a5d4c]4 * Copyright (c) 2018 Ondrej Hlavaty
[6297465]5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
[c8ea6eca]31/** @addtogroup drvusbehci
[6297465]32 * @{
33 */
34/** @file
35 * @brief EHCI Host controller driver routines
36 */
37
38#include <assert.h>
39#include <async.h>
40#include <errno.h>
41#include <macros.h>
42#include <mem.h>
43#include <stdlib.h>
[8d2dd7f2]44#include <stdint.h>
[6297465]45#include <str_error.h>
46
47#include <usb/debug.h>
48#include <usb/usb.h>
[c6f82e5]49#include <usb/host/utility.h>
[6297465]50
[e9c5bd9]51#include "ehci_batch.h"
[6297465]52
53#include "hc.h"
54
55#define EHCI_USED_INTERRUPTS \
[bfff7fd]56 (USB_INTR_IRQ_FLAG | USB_INTR_ERR_IRQ_FLAG | USB_INTR_PORT_CHANGE_FLAG | \
57 USB_INTR_ASYNC_ADVANCE_FLAG | USB_INTR_HOST_ERR_FLAG)
[6297465]58
59static const irq_pio_range_t ehci_pio_ranges[] = {
60 {
61 .base = 0,
62 .size = sizeof(ehci_regs_t)
63 }
64};
65
66static const irq_cmd_t ehci_irq_commands[] = {
67 {
68 .cmd = CMD_PIO_READ_32,
69 .dstarg = 1,
70 .addr = NULL
71 },
72 {
73 .cmd = CMD_AND,
74 .srcarg = 1,
75 .dstarg = 2,
76 .value = 0
77 },
78 {
79 .cmd = CMD_PREDICATE,
80 .srcarg = 2,
81 .value = 2
82 },
83 {
84 .cmd = CMD_PIO_WRITE_A_32,
85 .srcarg = 1,
86 .addr = NULL
87 },
88 {
89 .cmd = CMD_ACCEPT
90 }
91};
92
[5a6cc679]93static errno_t hc_init_memory(hc_t *instance);
[6297465]94
95/** Generate IRQ code.
96 * @param[out] ranges PIO ranges buffer.
[ba4a03a5]97 * @param[in] hw_res Device's resources.
[6297465]98 *
[68e5406]99 * @param[out] irq
100 *
[6297465]101 * @return Error code.
102 */
[5a6cc679]103errno_t hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
[6297465]104{
105 assert(code);
[ba4a03a5]106 assert(hw_res);
[32fb6bce]107 hc_t *instance = hcd_to_hc(hcd);
[e4d7363]108
[ba4a03a5]109 if (hw_res->irqs.count != 1 || hw_res->mem_ranges.count != 1)
110 return EINVAL;
111
112 addr_range_t regs = hw_res->mem_ranges.ranges[0];
113
114 if (RNGSZ(regs) < sizeof(ehci_regs_t))
[6297465]115 return EOVERFLOW;
116
117 code->ranges = malloc(sizeof(ehci_pio_ranges));
118 if (code->ranges == NULL)
119 return ENOMEM;
120
121 code->cmds = malloc(sizeof(ehci_irq_commands));
122 if (code->cmds == NULL) {
123 free(code->ranges);
124 return ENOMEM;
125 }
126
127 code->rangecount = ARRAY_SIZE(ehci_pio_ranges);
128 code->cmdcount = ARRAY_SIZE(ehci_irq_commands);
129
130 memcpy(code->ranges, ehci_pio_ranges, sizeof(ehci_pio_ranges));
[ba4a03a5]131 code->ranges[0].base = RNGABS(regs);
[6297465]132
133 memcpy(code->cmds, ehci_irq_commands, sizeof(ehci_irq_commands));
[dca8fe5]134
[d09d108]135 ehci_regs_t *registers =
[3bacee1]136 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength));
[d09d108]137 code->cmds[0].addr = (void *) &registers->usbsts;
138 code->cmds[3].addr = (void *) &registers->usbsts;
[6297465]139 EHCI_WR(code->cmds[1].value, EHCI_USED_INTERRUPTS);
140
[a1732929]141 usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.",
[ba4a03a5]142 RNGABSPTR(regs), RNGSZ(regs), hw_res->irqs.irqs[0]);
143
[68e5406]144 *irq = hw_res->irqs.irqs[0];
145 return EOK;
[6297465]146}
147
148/** Initialize EHCI hc driver structure
149 *
150 * @param[in] instance Memory place for the structure.
151 * @param[in] regs Device's I/O registers range.
152 * @param[in] interrupts True if w interrupts should be used
153 * @return Error code
154 */
[5a6cc679]155errno_t hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res)
[6297465]156{
[32fb6bce]157 hc_t *instance = hcd_to_hc(hcd);
[7813516]158 assert(hw_res);
159 if (hw_res->mem_ranges.count != 1 ||
160 hw_res->mem_ranges.ranges[0].size <
[3bacee1]161 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))
162 return EINVAL;
[6297465]163
[5a6cc679]164 errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0],
[7813516]165 (void **)&instance->caps);
[6297465]166 if (ret != EOK) {
[05b51e37]167 usb_log_error("HC(%p): Failed to gain access to device "
[a1732929]168 "registers: %s.", instance, str_error(ret));
[6297465]169 return ret;
170 }
[e4d7363]171
[3bacee1]172 usb_log_info("HC(%p): Device registers at %" PRIx64 " (%zuB) accessible.",
[05b51e37]173 instance, hw_res->mem_ranges.ranges[0].address.absolute,
[7813516]174 hw_res->mem_ranges.ranges[0].size);
[6297465]175 instance->registers =
[3bacee1]176 (void *)instance->caps + EHCI_RD8(instance->caps->caplength);
[05b51e37]177 usb_log_info("HC(%p): Device control registers at %" PRIx64, instance,
[3bacee1]178 hw_res->mem_ranges.ranges[0].address.absolute +
179 EHCI_RD8(instance->caps->caplength));
[6297465]180
[8ad2b0a]181 list_initialize(&instance->pending_endpoints);
[6297465]182 fibril_mutex_initialize(&instance->guard);
[763dbcb]183 fibril_condvar_initialize(&instance->async_doorbell);
[6297465]184
185 ret = hc_init_memory(instance);
186 if (ret != EOK) {
[05b51e37]187 usb_log_error("HC(%p): Failed to create EHCI memory structures:"
188 " %s.", instance, str_error(ret));
[6297465]189 return ret;
190 }
191
[05b51e37]192 usb_log_info("HC(%p): Initializing RH(%p).", instance, &instance->rh);
[6297465]193 ehci_rh_init(
[ddbd088]194 &instance->rh, instance->caps, instance->registers, &instance->guard,
195 "ehci rh");
[6297465]196
[32fb6bce]197 ehci_bus_init(&instance->bus, instance);
198 hc_device_setup(hcd, (bus_t *) &instance->bus);
[6297465]199 return EOK;
200}
201
[7813516]202/** Safely dispose host controller internal structures
203 *
204 * @param[in] instance Host controller structure to use.
205 */
[35c37fc]206int hc_gone(hc_device_t *hcd)
[7813516]207{
[35c37fc]208 hc_t *hc = hcd_to_hc(hcd);
209 endpoint_list_fini(&hc->async_list);
210 endpoint_list_fini(&hc->int_list);
211 dma_buffer_free(&hc->dma_buffer);
[32fb6bce]212 return EOK;
[84239b1]213}
[7813516]214
[9dfb034]215/** Quiesce host controller
216 *
217 * @param hcd Host controller device
218 */
219int hc_quiesce(hc_device_t *hcd)
220{
221 hc_t *instance = hcd_to_hc(hcd);
222
223 /*
224 * Turn off the HC if it's running, Reseting a running device is
225 * undefined
226 */
227 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
228 /* disable all interrupts */
229 EHCI_WR(instance->registers->usbintr, 0);
230 /* ack all interrupts */
231 EHCI_WR(instance->registers->usbsts, 0x3f);
232 /* Stop HC hw */
233 EHCI_WR(instance->registers->usbcmd, 0);
234 /* Wait until hc is halted */
235 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
236 fibril_usleep(1);
237 }
238 usb_log_info("HC(%p): EHCI turned off.", instance);
239 } else {
240 usb_log_info("HC(%p): EHCI was not running.", instance);
241 }
242
243 /* Hw initialization sequence, see page 53 (pdf 63) */
244 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
245 usb_log_info("HC(%p): Waiting for HW reset.", instance);
246 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
247 fibril_usleep(1);
248 }
249 usb_log_debug("HC(%p): HW reset OK.", instance);
250
251 return EOK;
252}
253
[6297465]254void hc_enqueue_endpoint(hc_t *instance, const endpoint_t *ep)
255{
[5f5321ee]256 assert(instance);
257 assert(ep);
258 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
[a1732929]259 usb_log_debug("HC(%p) enqueue EP(%d:%d:%s:%s)", instance,
[a5b3de6]260 ep->device->address, ep->endpoint,
[92900e2]261 usb_str_transfer_type_short(ep->transfer_type),
262 usb_str_direction(ep->direction));
[3bacee1]263 switch (ep->transfer_type) {
[5f5321ee]264 case USB_TRANSFER_CONTROL:
265 case USB_TRANSFER_BULK:
266 endpoint_list_append_ep(&instance->async_list, ehci_ep);
267 break;
268 case USB_TRANSFER_INTERRUPT:
269 endpoint_list_append_ep(&instance->int_list, ehci_ep);
270 break;
271 case USB_TRANSFER_ISOCHRONOUS:
272 /* NOT SUPPORTED */
273 break;
274 }
[6297465]275}
276
277void hc_dequeue_endpoint(hc_t *instance, const endpoint_t *ep)
278{
[763dbcb]279 assert(instance);
280 assert(ep);
281 ehci_endpoint_t *ehci_ep = ehci_endpoint_get(ep);
[7278cbc9]282 usb_log_debug("HC(%p) dequeue EP(%d:%d:%s:%s)", instance,
283 ep->device->address, ep->endpoint,
[92900e2]284 usb_str_transfer_type_short(ep->transfer_type),
285 usb_str_direction(ep->direction));
[3bacee1]286 switch (ep->transfer_type) {
[763dbcb]287 case USB_TRANSFER_INTERRUPT:
[ce735cc2]288 endpoint_list_remove_ep(&instance->int_list, ehci_ep);
[763dbcb]289 /* Fall through */
290 case USB_TRANSFER_ISOCHRONOUS:
291 /* NOT SUPPORTED */
292 return;
293 case USB_TRANSFER_CONTROL:
294 case USB_TRANSFER_BULK:
295 endpoint_list_remove_ep(&instance->async_list, ehci_ep);
296 break;
297 }
298 fibril_mutex_lock(&instance->guard);
[05b51e37]299 usb_log_debug("HC(%p): Waiting for doorbell", instance);
[1803b7d]300 EHCI_SET(instance->registers->usbcmd, USB_CMD_IRQ_ASYNC_DOORBELL);
[763dbcb]301 fibril_condvar_wait(&instance->async_doorbell, &instance->guard);
[05b51e37]302 usb_log_debug2("HC(%p): Got doorbell", instance);
[763dbcb]303 fibril_mutex_unlock(&instance->guard);
[6297465]304}
305
[5a6cc679]306errno_t ehci_hc_status(bus_t *bus_base, uint32_t *status)
[c9e954c]307{
[32fb6bce]308 assert(bus_base);
[c9e954c]309 assert(status);
[32fb6bce]310
311 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
312 hc_t *hc = bus->hc;
313 assert(hc);
314
[c9e954c]315 *status = 0;
[32fb6bce]316 if (hc->registers) {
317 *status = EHCI_RD(hc->registers->usbsts);
318 EHCI_WR(hc->registers->usbsts, *status);
[c9e954c]319 }
[32fb6bce]320 usb_log_debug2("HC(%p): Read status: %x", hc, *status);
[c9e954c]321 return EOK;
322}
323
[6297465]324/** Add USB transfer to the schedule.
325 *
[c9e954c]326 * @param[in] hcd HCD driver structure.
[6297465]327 * @param[in] batch Batch representing the transfer.
328 * @return Error code.
329 */
[5a6cc679]330errno_t ehci_hc_schedule(usb_transfer_batch_t *batch)
[6297465]331{
[32fb6bce]332 assert(batch);
333
334 ehci_bus_t *bus = (ehci_bus_t *) endpoint_get_bus(batch->ep);
335 hc_t *hc = bus->hc;
336 assert(hc);
[6297465]337
338 /* Check for root hub communication */
[32fb6bce]339 if (batch->target.address == ehci_rh_get_address(&hc->rh)) {
[05b51e37]340 usb_log_debug("HC(%p): Scheduling BATCH(%p) for RH(%p)",
[32fb6bce]341 hc, batch, &hc->rh);
342 return ehci_rh_schedule(&hc->rh, batch);
[6297465]343 }
[5fd9c30]344
[3bacee1]345 endpoint_t *const ep = batch->ep;
346 ehci_endpoint_t *const ehci_ep = ehci_endpoint_get(ep);
[4db49344]347 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch);
[8ad2b0a]348
[4db49344]349 int err;
[5fd9c30]350
[4db49344]351 if ((err = ehci_transfer_batch_prepare(ehci_batch)))
352 return err;
[8ad2b0a]353
[4db49344]354 fibril_mutex_lock(&hc->guard);
355
356 if ((err = endpoint_activate_locked(ep, batch))) {
357 fibril_mutex_unlock(&hc->guard);
[5fd9c30]358 return err;
[8ad2b0a]359 }
[e9c5bd9]360
[32fb6bce]361 usb_log_debug("HC(%p): Committing BATCH(%p)", hc, batch);
[e9c5bd9]362 ehci_transfer_batch_commit(ehci_batch);
[8ad2b0a]363
364 /* Enqueue endpoint to the checked list */
365 usb_log_debug2("HC(%p): Appending BATCH(%p)", hc, batch);
366 list_append(&ehci_ep->pending_link, &hc->pending_endpoints);
367
[4db49344]368 fibril_mutex_unlock(&hc->guard);
[e9c5bd9]369 return EOK;
[6297465]370}
371
372/** Interrupt handling routine
373 *
[c9e954c]374 * @param[in] hcd HCD driver structure.
[6297465]375 * @param[in] status Value of the status register at the time of interrupt.
376 */
[32fb6bce]377void ehci_hc_interrupt(bus_t *bus_base, uint32_t status)
[6297465]378{
[32fb6bce]379 assert(bus_base);
380
381 ehci_bus_t *bus = (ehci_bus_t *) bus_base;
382 hc_t *hc = bus->hc;
383 assert(hc);
[07645906]384
[3bacee1]385 usb_log_debug2("HC(%p): Interrupt: %" PRIx32, hc, status);
[6297465]386 if (status & USB_STS_PORT_CHANGE_FLAG) {
[32fb6bce]387 ehci_rh_interrupt(&hc->rh);
[6297465]388 }
[07645906]389
[580b330]390 if (status & USB_STS_IRQ_ASYNC_ADVANCE_FLAG) {
[32fb6bce]391 fibril_mutex_lock(&hc->guard);
392 usb_log_debug2("HC(%p): Signaling doorbell", hc);
393 fibril_condvar_broadcast(&hc->async_doorbell);
394 fibril_mutex_unlock(&hc->guard);
[763dbcb]395 }
[07645906]396
[e9c5bd9]397 if (status & (USB_STS_IRQ_FLAG | USB_STS_ERR_IRQ_FLAG)) {
[32fb6bce]398 fibril_mutex_lock(&hc->guard);
[e9c5bd9]399
[36795edf]400 usb_log_debug2("HC(%p): Scanning %zu pending endpoints", hc,
[3bacee1]401 list_count(&hc->pending_endpoints));
[8ad2b0a]402 list_foreach_safe(hc->pending_endpoints, current, next) {
[3bacee1]403 ehci_endpoint_t *ep =
404 list_get_instance(current, ehci_endpoint_t, pending_link);
[8ad2b0a]405
[3bacee1]406 ehci_transfer_batch_t *batch =
407 ehci_transfer_batch_get(ep->base.active_batch);
[8ad2b0a]408 assert(batch);
[e9c5bd9]409
[5fd9c30]410 if (ehci_transfer_batch_check_completed(batch)) {
[8ad2b0a]411 endpoint_deactivate_locked(&ep->base);
[e9c5bd9]412 list_remove(current);
[c6f82e5]413 hc_reset_toggles(&batch->base, &ehci_ep_toggle_reset);
[5fd9c30]414 usb_transfer_batch_finish(&batch->base);
[e9c5bd9]415 }
416 }
[32fb6bce]417 fibril_mutex_unlock(&hc->guard);
[8ad2b0a]418
[e9c5bd9]419 }
420
[07645906]421 if (status & USB_STS_HOST_ERROR_FLAG) {
[32fb6bce]422 usb_log_fatal("HCD(%p): HOST SYSTEM ERROR!", hc);
[07645906]423 //TODO do something here
424 }
[6297465]425}
426
427/** EHCI hw initialization routine.
428 *
429 * @param[in] instance EHCI hc driver structure.
430 */
[32fb6bce]431int hc_start(hc_device_t *hcd)
[6297465]432{
[32fb6bce]433 hc_t *instance = hcd_to_hc(hcd);
[e4d7363]434 usb_log_debug("HC(%p): Starting HW.", instance);
435
[7c3fb9b]436 /*
437 * Turn off the HC if it's running, Reseting a running device is
438 * undefined
439 */
[478e243]440 if (!(EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG)) {
441 /* disable all interrupts */
442 EHCI_WR(instance->registers->usbintr, 0);
443 /* ack all interrupts */
444 EHCI_WR(instance->registers->usbsts, 0x3f);
445 /* Stop HC hw */
446 EHCI_WR(instance->registers->usbcmd, 0);
447 /* Wait until hc is halted */
448 while ((EHCI_RD(instance->registers->usbsts) & USB_STS_HC_HALTED_FLAG) == 0) {
[5f97ef44]449 fibril_usleep(1);
[478e243]450 }
[05b51e37]451 usb_log_info("HC(%p): EHCI turned off.", instance);
[478e243]452 } else {
[05b51e37]453 usb_log_info("HC(%p): EHCI was not running.", instance);
[478e243]454 }
455
456 /* Hw initialization sequence, see page 53 (pdf 63) */
457 EHCI_SET(instance->registers->usbcmd, USB_CMD_HC_RESET_FLAG);
[05b51e37]458 usb_log_info("HC(%p): Waiting for HW reset.", instance);
[478e243]459 while (EHCI_RD(instance->registers->usbcmd) & USB_CMD_HC_RESET_FLAG) {
[5f97ef44]460 fibril_usleep(1);
[478e243]461 }
[05b51e37]462 usb_log_debug("HC(%p): HW reset OK.", instance);
463
[763dbcb]464 /* Use the lowest 4G segment */
[478e243]465 EHCI_WR(instance->registers->ctrldssegment, 0);
[3eb0c85]466
467 /* Enable periodic list */
[35c37fc]468 assert(instance->periodic_list);
[50362c6]469 uintptr_t phys_base =
[3bacee1]470 addr_to_phys((void *)instance->periodic_list);
[478e243]471 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base);
472 EHCI_WR(instance->registers->periodiclistbase, phys_base);
[44b9b44]473 EHCI_SET(instance->registers->usbcmd, USB_CMD_PERIODIC_SCHEDULE_FLAG);
[05b51e37]474 usb_log_debug("HC(%p): Enabled periodic list.", instance);
[478e243]475
[0a751aa]476 /* Enable Async schedule */
[3bacee1]477 phys_base = addr_to_phys((void *)instance->async_list.list_head);
[50362c6]478 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base);
479 EHCI_WR(instance->registers->asynclistaddr, phys_base);
[0a751aa]480 EHCI_SET(instance->registers->usbcmd, USB_CMD_ASYNC_SCHEDULE_FLAG);
[05b51e37]481 usb_log_debug("HC(%p): Enabled async list.", instance);
[44b9b44]482
[3eb0c85]483 /* Start hc and get all ports */
[44b9b44]484 EHCI_SET(instance->registers->usbcmd, USB_CMD_RUN_FLAG);
485 EHCI_SET(instance->registers->configflag, USB_CONFIG_FLAG_FLAG);
[05b51e37]486 usb_log_debug("HC(%p): HW started.", instance);
487
[a1732929]488 usb_log_debug2("HC(%p): Registers: "
489 "\tUSBCMD(%p): %x(0x00080000 = at least 1ms between interrupts)"
490 "\tUSBSTS(%p): %x(0x00001000 = HC halted)"
491 "\tUSBINT(%p): %x(0x0 = no interrupts)."
492 "\tCONFIG(%p): %x(0x0 = ports controlled by companion hc).",
[05b51e37]493 instance,
[615abda]494 &instance->registers->usbcmd, EHCI_RD(instance->registers->usbcmd),
495 &instance->registers->usbsts, EHCI_RD(instance->registers->usbsts),
496 &instance->registers->usbintr, EHCI_RD(instance->registers->usbintr),
497 &instance->registers->configflag, EHCI_RD(instance->registers->configflag));
[495547d]498 /* Clear and Enable interrupts */
499 EHCI_WR(instance->registers->usbsts, EHCI_RD(instance->registers->usbsts));
500 EHCI_WR(instance->registers->usbintr, EHCI_USED_INTERRUPTS);
[e4d7363]501
502 return EOK;
[6297465]503}
504
[129b821f]505/**
506 * Setup roothub as a virtual hub.
507 */
508int hc_setup_roothub(hc_device_t *hcd)
509{
510 return hc_setup_virtual_root_hub(hcd, USB_SPEED_HIGH);
511}
512
[6297465]513/** Initialize memory structures used by the EHCI hcd.
514 *
515 * @param[in] instance EHCI hc driver structure.
516 * @return Error code.
517 */
[5a6cc679]518errno_t hc_init_memory(hc_t *instance)
[6297465]519{
[478e243]520 assert(instance);
[05b51e37]521 usb_log_debug2("HC(%p): Initializing Async list(%p).", instance,
522 &instance->async_list);
[5a6cc679]523 errno_t ret = endpoint_list_init(&instance->async_list, "ASYNC");
[5f5321ee]524 if (ret != EOK) {
[05b51e37]525 usb_log_error("HC(%p): Failed to setup ASYNC list: %s",
526 instance, str_error(ret));
[5f5321ee]527 return ret;
528 }
[7c3fb9b]529 /*
530 * Specs say "Software must set queue head horizontal pointer T-bits to
[50362c6]531 * a zero for queue heads in the asynchronous schedule" (4.4.0).
532 * So we must maintain circular buffer (all horizontal pointers
[7c3fb9b]533 * have to be valid
534 */
[50362c6]535 endpoint_list_chain(&instance->async_list, &instance->async_list);
[5f5321ee]536
[05b51e37]537 usb_log_debug2("HC(%p): Initializing Interrupt list (%p).", instance,
538 &instance->int_list);
[5f5321ee]539 ret = endpoint_list_init(&instance->int_list, "INT");
540 if (ret != EOK) {
[05b51e37]541 usb_log_error("HC(%p): Failed to setup INT list: %s",
542 instance, str_error(ret));
[5f5321ee]543 endpoint_list_fini(&instance->async_list);
544 return ret;
545 }
[478e243]546
547 /* Take 1024 periodic list heads, we ignore low mem options */
[35c37fc]548 if (dma_buffer_alloc(&instance->dma_buffer, PAGE_SIZE)) {
[05b51e37]549 usb_log_error("HC(%p): Failed to get ISO schedule page.",
550 instance);
[5f5321ee]551 endpoint_list_fini(&instance->async_list);
552 endpoint_list_fini(&instance->int_list);
[478e243]553 return ENOMEM;
[5f5321ee]554 }
[35c37fc]555 instance->periodic_list = instance->dma_buffer.virt;
[05b51e37]556
557 usb_log_debug2("HC(%p): Initializing Periodic list.", instance);
[3bacee1]558 for (unsigned i = 0; i < PAGE_SIZE / sizeof(link_pointer_t); ++i) {
[478e243]559 /* Disable everything for now */
[35c37fc]560 instance->periodic_list[i] =
[50362c6]561 LINK_POINTER_QH(addr_to_phys(instance->int_list.list_head));
[478e243]562 }
[6297465]563 return EOK;
564}
565
566/**
567 * @}
568 */
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