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source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 876f6463

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Last change on this file since 876f6463 was 2df6f6fe, checked in by Martin Decky <martin@…>, 13 years ago
cstyle and cleanup (no change in functionality)
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1	/*
2	* Copyright (c) 2010 Lenka Trochtova
3	* Copyright (c) 2011 Jiri Svoboda
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	*
10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/
29
30	/**
31	* @defgroup pciintel pci bus driver for intel method 1.
32	* @brief HelenOS root pci bus driver for intel method 1.
33	* @{
34	*/
35
36	/** @file
37	*/
38
39	#include <assert.h>
40	#include <stdio.h>
41	#include <errno.h>
42	#include <bool.h>
43	#include <fibril_synch.h>
44	#include <str.h>
45	#include <ctype.h>
46	#include <macros.h>
47	#include <str_error.h>
48
49	#include <ddf/driver.h>
50	#include <ddf/log.h>
51	#include <devman.h>
52	#include <ipc/devman.h>
53	#include <ipc/dev_iface.h>
54	#include <ipc/irc.h>
55	#include <ns.h>
56	#include <ipc/services.h>
57	#include <sysinfo.h>
58	#include <ops/hw_res.h>
59	#include <device/hw_res.h>
60	#include <ddi.h>
61	#include <libarch/ddi.h>
62	#include <pci_dev_iface.h>
63
64	#include "pci.h"
65
66	#define NAME "pciintel"
67
68	#define CONF_ADDR(bus, dev, fn, reg) \
69	((1 << 31) \| (bus << 16) \| (dev << 11) \| (fn << 8) \| (reg & ~3))
70
71	/** Obtain PCI function soft-state from DDF function node */
72	#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
73
74	/** Obtain PCI bus soft-state from DDF device node */
75	#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
76
77	/** Obtain PCI bus soft-state from function soft-state */
78	#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
79
80	/** Max is 47, align to something nice. */
81	#define ID_MAX_STR_LEN 50
82
83	static hw_resource_list_t pciintel_get_resources(ddf_fun_t fnode)
84	{
85	pci_fun_t *fun = PCI_FUN(fnode);
86
87	if (fun == NULL)
88	return NULL;
89	return &fun->hw_resources;
90	}
91
92	static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
93	{
94	/* This is an old ugly way */
95	assert(fnode);
96	pci_fun_t dev_data = (pci_fun_t ) fnode->driver_data;
97
98	sysarg_t apic;
99	sysarg_t i8259;
100
101	async_sess_t *irc_sess = NULL;
102
103	if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
104	\|\| ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
105	irc_sess = service_connect_blocking(EXCHANGE_SERIALIZE,
106	SERVICE_IRC, 0, 0);
107	}
108
109	if (!irc_sess)
110	return false;
111
112	size_t i = 0;
113	hw_resource_list_t *res = &dev_data->hw_resources;
114	for (; i < res->count; i++) {
115	if (res->resources[i].type == INTERRUPT) {
116	const int irq = res->resources[i].res.interrupt.irq;
117
118	async_exch_t *exch = async_exchange_begin(irc_sess);
119	const int rc =
120	async_req_1_0(exch, IRC_ENABLE_INTERRUPT, irq);
121	async_exchange_end(exch);
122
123	if (rc != EOK) {
124	async_hangup(irc_sess);
125	return false;
126	}
127	}
128	}
129
130	async_hangup(irc_sess);
131	return true;
132	}
133
134	static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
135	uint32_t data)
136	{
137	if (address > 252)
138	return EINVAL;
139	pci_conf_write_32(PCI_FUN(fun), address, data);
140	return EOK;
141	}
142
143	static int pci_config_space_write_16(
144	ddf_fun_t *fun, uint32_t address, uint16_t data)
145	{
146	if (address > 254)
147	return EINVAL;
148	pci_conf_write_16(PCI_FUN(fun), address, data);
149	return EOK;
150	}
151
152	static int pci_config_space_write_8(
153	ddf_fun_t *fun, uint32_t address, uint8_t data)
154	{
155	if (address > 255)
156	return EINVAL;
157	pci_conf_write_8(PCI_FUN(fun), address, data);
158	return EOK;
159	}
160
161	static int pci_config_space_read_32(
162	ddf_fun_t fun, uint32_t address, uint32_t data)
163	{
164	if (address > 252)
165	return EINVAL;
166	*data = pci_conf_read_32(PCI_FUN(fun), address);
167	return EOK;
168	}
169
170	static int pci_config_space_read_16(
171	ddf_fun_t fun, uint32_t address, uint16_t data)
172	{
173	if (address > 254)
174	return EINVAL;
175	*data = pci_conf_read_16(PCI_FUN(fun), address);
176	return EOK;
177	}
178
179	static int pci_config_space_read_8(
180	ddf_fun_t fun, uint32_t address, uint8_t data)
181	{
182	if (address > 255)
183	return EINVAL;
184	*data = pci_conf_read_8(PCI_FUN(fun), address);
185	return EOK;
186	}
187
188	static hw_res_ops_t pciintel_hw_res_ops = {
189	.get_resource_list = &pciintel_get_resources,
190	.enable_interrupt = &pciintel_enable_interrupt,
191	};
192
193	static pci_dev_iface_t pci_dev_ops = {
194	.config_space_read_8 = &pci_config_space_read_8,
195	.config_space_read_16 = &pci_config_space_read_16,
196	.config_space_read_32 = &pci_config_space_read_32,
197	.config_space_write_8 = &pci_config_space_write_8,
198	.config_space_write_16 = &pci_config_space_write_16,
199	.config_space_write_32 = &pci_config_space_write_32
200	};
201
202	static ddf_dev_ops_t pci_fun_ops = {
203	.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
204	.interfaces[PCI_DEV_IFACE] = &pci_dev_ops
205	};
206
207	static int pci_dev_add(ddf_dev_t *);
208	static int pci_fun_online(ddf_fun_t *);
209	static int pci_fun_offline(ddf_fun_t *);
210
211	/** PCI bus driver standard operations */
212	static driver_ops_t pci_ops = {
213	.dev_add = &pci_dev_add,
214	.fun_online = &pci_fun_online,
215	.fun_offline = &pci_fun_offline,
216	};
217
218	/** PCI bus driver structure */
219	static driver_t pci_driver = {
220	.name = NAME,
221	.driver_ops = &pci_ops
222	};
223
224	static void pci_conf_read(pci_fun_t fun, int reg, uint8_t buf, size_t len)
225	{
226	pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
227
228	fibril_mutex_lock(&bus->conf_mutex);
229
230	const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
231	void *addr = bus->conf_data_port + (reg & 3);
232
233	pio_write_32(bus->conf_addr_port, conf_addr);
234
235	switch (len) {
236	case 1:
237	buf[0] = pio_read_8(addr);
238	break;
239	case 2:
240	((uint16_t *) buf)[0] = pio_read_16(addr);
241	break;
242	case 4:
243	((uint32_t *) buf)[0] = pio_read_32(addr);
244	break;
245	}
246
247	fibril_mutex_unlock(&bus->conf_mutex);
248	}
249
250	static void pci_conf_write(pci_fun_t fun, int reg, uint8_t buf, size_t len)
251	{
252	pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
253
254	fibril_mutex_lock(&bus->conf_mutex);
255
256	uint32_t conf_addr;
257	conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
258	void *addr = bus->conf_data_port + (reg & 3);
259
260	pio_write_32(bus->conf_addr_port, conf_addr);
261
262	switch (len) {
263	case 1:
264	pio_write_8(addr, buf[0]);
265	break;
266	case 2:
267	pio_write_16(addr, ((uint16_t *) buf)[0]);
268	break;
269	case 4:
270	pio_write_32(addr, ((uint32_t *) buf)[0]);
271	break;
272	}
273
274	fibril_mutex_unlock(&bus->conf_mutex);
275	}
276
277	uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
278	{
279	uint8_t res;
280	pci_conf_read(fun, reg, &res, 1);
281	return res;
282	}
283
284	uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
285	{
286	uint16_t res;
287	pci_conf_read(fun, reg, (uint8_t *) &res, 2);
288	return res;
289	}
290
291	uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
292	{
293	uint32_t res;
294	pci_conf_read(fun, reg, (uint8_t *) &res, 4);
295	return res;
296	}
297
298	void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
299	{
300	pci_conf_write(fun, reg, (uint8_t *) &val, 1);
301	}
302
303	void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
304	{
305	pci_conf_write(fun, reg, (uint8_t *) &val, 2);
306	}
307
308	void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
309	{
310	pci_conf_write(fun, reg, (uint8_t *) &val, 4);
311	}
312
313	void pci_fun_create_match_ids(pci_fun_t *fun)
314	{
315	int rc;
316	char match_id_str[ID_MAX_STR_LEN];
317
318	/* Vendor ID & Device ID, length(incl \0) 22 */
319	rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04x&dev=%04x",
320	fun->vendor_id, fun->device_id);
321	if (rc < 0) {
322	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
323	str_error(rc));
324	}
325
326	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
327	if (rc != EOK) {
328	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
329	}
330
331	/* Class, subclass, prog IF, revision, length(incl \0) 47 */
332	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
333	"pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
334	fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
335	if (rc < 0) {
336	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
337	str_error(rc));
338	}
339
340	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
341	if (rc != EOK) {
342	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
343	}
344
345	/* Class, subclass, prog IF, length(incl \0) 35 */
346	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
347	"pci/class=%02x&subclass=%02x&progif=%02x",
348	fun->class_code, fun->subclass_code, fun->prog_if);
349	if (rc < 0) {
350	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
351	str_error(rc));
352	}
353
354	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
355	if (rc != EOK) {
356	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
357	}
358
359	/* Class, subclass, length(incl \0) 25 */
360	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
361	"pci/class=%02x&subclass=%02x",
362	fun->class_code, fun->subclass_code);
363	if (rc < 0) {
364	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
365	str_error(rc));
366	}
367
368	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
369	if (rc != EOK) {
370	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
371	}
372
373	/* Class, length(incl \0) 13 */
374	rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
375	fun->class_code);
376	if (rc < 0) {
377	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
378	str_error(rc));
379	}
380
381	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
382	if (rc != EOK) {
383	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
384	}
385
386	/* TODO add subsys ids, but those exist only in header type 0 */
387	}
388
389	void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
390	bool io)
391	{
392	hw_resource_list_t *hw_res_list = &fun->hw_resources;
393	hw_resource_t *hw_resources = hw_res_list->resources;
394	size_t count = hw_res_list->count;
395
396	assert(hw_resources != NULL);
397	assert(count < PCI_MAX_HW_RES);
398
399	if (io) {
400	hw_resources[count].type = IO_RANGE;
401	hw_resources[count].res.io_range.address = range_addr;
402	hw_resources[count].res.io_range.size = range_size;
403	hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
404	} else {
405	hw_resources[count].type = MEM_RANGE;
406	hw_resources[count].res.mem_range.address = range_addr;
407	hw_resources[count].res.mem_range.size = range_size;
408	hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
409	}
410
411	hw_res_list->count++;
412	}
413
414	/** Read the base address register (BAR) of the device and if it contains valid
415	* address add it to the devices hw resource list.
416	*
417	* @param fun PCI function
418	* @param addr The address of the BAR in the PCI configuration address space of
419	* the device
420	* @return The addr the address of the BAR which should be read next
421	*/
422	int pci_read_bar(pci_fun_t *fun, int addr)
423	{
424	/* Value of the BAR */
425	uint32_t val, mask;
426	/* IO space address */
427	bool io;
428	/* 64-bit wide address */
429	bool addrw64;
430
431	/* Size of the io or memory range specified by the BAR */
432	size_t range_size;
433	/* Beginning of the io or memory range specified by the BAR */
434	uint64_t range_addr;
435
436	/* Get the value of the BAR. */
437	val = pci_conf_read_32(fun, addr);
438
439	#define IO_MASK (~0x3)
440	#define MEM_MASK (~0xf)
441
442	io = (bool) (val & 1);
443	if (io) {
444	addrw64 = false;
445	mask = IO_MASK;
446	} else {
447	mask = MEM_MASK;
448	switch ((val >> 1) & 3) {
449	case 0:
450	addrw64 = false;
451	break;
452	case 2:
453	addrw64 = true;
454	break;
455	default:
456	/* reserved, go to the next BAR */
457	return addr + 4;
458	}
459	}
460
461	/* Get the address mask. */
462	pci_conf_write_32(fun, addr, 0xffffffff);
463	mask &= pci_conf_read_32(fun, addr);
464
465	/* Restore the original value. */
466	pci_conf_write_32(fun, addr, val);
467	val = pci_conf_read_32(fun, addr);
468
469	range_size = pci_bar_mask_to_size(mask);
470
471	if (addrw64) {
472	range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) \|
473	(val & 0xfffffff0);
474	} else {
475	range_addr = (val & 0xfffffff0);
476	}
477
478	if (range_addr != 0) {
479	ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
480	", size = %x", fun->fnode->name, range_addr,
481	(unsigned int) range_size);
482	}
483
484	pci_add_range(fun, range_addr, range_size, io);
485
486	if (addrw64)
487	return addr + 8;
488
489	return addr + 4;
490	}
491
492	void pci_add_interrupt(pci_fun_t *fun, int irq)
493	{
494	hw_resource_list_t *hw_res_list = &fun->hw_resources;
495	hw_resource_t *hw_resources = hw_res_list->resources;
496	size_t count = hw_res_list->count;
497
498	assert(NULL != hw_resources);
499	assert(count < PCI_MAX_HW_RES);
500
501	hw_resources[count].type = INTERRUPT;
502	hw_resources[count].res.interrupt.irq = irq;
503
504	hw_res_list->count++;
505
506	ddf_msg(LVL_NOTE, "Function %s uses irq %x.", fun->fnode->name, irq);
507	}
508
509	void pci_read_interrupt(pci_fun_t *fun)
510	{
511	uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
512	if (irq != 0xff)
513	pci_add_interrupt(fun, irq);
514	}
515
516	/** Enumerate (recursively) and register the devices connected to a pci bus.
517	*
518	* @param bus Host-to-PCI bridge
519	* @param bus_num Bus number
520	*/
521	void pci_bus_scan(pci_bus_t *bus, int bus_num)
522	{
523	ddf_fun_t *fnode;
524	pci_fun_t *fun;
525
526	int child_bus = 0;
527	int dnum, fnum;
528	bool multi;
529	uint8_t header_type;
530
531	fun = pci_fun_new(bus);
532
533	for (dnum = 0; dnum < 32; dnum++) {
534	multi = true;
535	for (fnum = 0; multi && fnum < 8; fnum++) {
536	pci_fun_init(fun, bus_num, dnum, fnum);
537	if (fun->vendor_id == 0xffff) {
538	/*
539	* The device is not present, go on scanning the
540	* bus.
541	*/
542	if (fnum == 0)
543	break;
544	else
545	continue;
546	}
547
548	header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
549	if (fnum == 0) {
550	/* Is the device multifunction? */
551	multi = header_type >> 7;
552	}
553	/* Clear the multifunction bit. */
554	header_type = header_type & 0x7F;
555
556	char *fun_name = pci_fun_create_name(fun);
557	if (fun_name == NULL) {
558	ddf_msg(LVL_ERROR, "Out of memory.");
559	return;
560	}
561
562	fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
563	free(fun_name);
564	if (fnode == NULL) {
565	ddf_msg(LVL_ERROR, "Failed creating function.");
566	return;
567	}
568
569	fun->fnode = fnode;
570
571	pci_alloc_resource_list(fun);
572	pci_read_bars(fun);
573	pci_read_interrupt(fun);
574
575	fnode->ops = &pci_fun_ops;
576	fnode->driver_data = fun;
577
578	ddf_msg(LVL_DEBUG, "Adding new function %s.",
579	fnode->name);
580
581	pci_fun_create_match_ids(fun);
582
583	if (ddf_fun_bind(fnode) != EOK) {
584	pci_clean_resource_list(fun);
585	clean_match_ids(&fnode->match_ids);
586	free((char *) fnode->name);
587	fnode->name = NULL;
588	continue;
589	}
590
591	if (header_type == PCI_HEADER_TYPE_BRIDGE \|\|
592	header_type == PCI_HEADER_TYPE_CARDBUS) {
593	child_bus = pci_conf_read_8(fun,
594	PCI_BRIDGE_SEC_BUS_NUM);
595	ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
596	"bridge, secondary bus number = %d.",
597	bus_num);
598	if (child_bus > bus_num)
599	pci_bus_scan(bus, child_bus);
600	}
601
602	fun = pci_fun_new(bus);
603	}
604	}
605
606	if (fun->vendor_id == 0xffff) {
607	/* Free the auxiliary function structure. */
608	pci_fun_delete(fun);
609	}
610	}
611
612	static int pci_dev_add(ddf_dev_t *dnode)
613	{
614	pci_bus_t *bus = NULL;
615	ddf_fun_t *ctl = NULL;
616	bool got_res = false;
617	int rc;
618
619	ddf_msg(LVL_DEBUG, "pci_dev_add");
620	dnode->parent_sess = NULL;
621
622	bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
623	if (bus == NULL) {
624	ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
625	rc = ENOMEM;
626	goto fail;
627	}
628	fibril_mutex_initialize(&bus->conf_mutex);
629
630	bus->dnode = dnode;
631	dnode->driver_data = bus;
632
633	dnode->parent_sess = devman_parent_device_connect(EXCHANGE_SERIALIZE,
634	dnode->handle, IPC_FLAG_BLOCKING);
635	if (!dnode->parent_sess) {
636	ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
637	"parent driver.");
638	rc = ENOENT;
639	goto fail;
640	}
641
642	hw_resource_list_t hw_resources;
643
644	rc = hw_res_get_resource_list(dnode->parent_sess, &hw_resources);
645	if (rc != EOK) {
646	ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
647	"for the device.");
648	goto fail;
649	}
650	got_res = true;
651
652	ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
653	hw_resources.resources[0].res.io_range.address);
654
655	assert(hw_resources.count > 0);
656	assert(hw_resources.resources[0].type == IO_RANGE);
657	assert(hw_resources.resources[0].res.io_range.size == 8);
658
659	bus->conf_io_addr =
660	(uint32_t) hw_resources.resources[0].res.io_range.address;
661
662	if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
663	&bus->conf_addr_port)) {
664	ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
665	rc = EADDRNOTAVAIL;
666	goto fail;
667	}
668	bus->conf_data_port = (char *) bus->conf_addr_port + 4;
669
670	/* Make the bus device more visible. It has no use yet. */
671	ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
672
673	ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
674	if (ctl == NULL) {
675	ddf_msg(LVL_ERROR, "Failed creating control function.");
676	rc = ENOMEM;
677	goto fail;
678	}
679
680	rc = ddf_fun_bind(ctl);
681	if (rc != EOK) {
682	ddf_msg(LVL_ERROR, "Failed binding control function.");
683	goto fail;
684	}
685
686	/* Enumerate functions. */
687	ddf_msg(LVL_DEBUG, "Scanning the bus");
688	pci_bus_scan(bus, 0);
689
690	hw_res_clean_resource_list(&hw_resources);
691
692	return EOK;
693
694	fail:
695	if (dnode->parent_sess)
696	async_hangup(dnode->parent_sess);
697
698	if (got_res)
699	hw_res_clean_resource_list(&hw_resources);
700
701	if (ctl != NULL)
702	ddf_fun_destroy(ctl);
703
704	return rc;
705	}
706
707	static int pci_fun_online(ddf_fun_t *fun)
708	{
709	ddf_msg(LVL_DEBUG, "pci_fun_online()");
710	return ddf_fun_online(fun);
711	}
712
713	static int pci_fun_offline(ddf_fun_t *fun)
714	{
715	ddf_msg(LVL_DEBUG, "pci_fun_offline()");
716	return ddf_fun_offline(fun);
717	}
718
719	static void pciintel_init(void)
720	{
721	ddf_log_init(NAME, LVL_ERROR);
722	pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
723	pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
724	}
725
726	pci_fun_t pci_fun_new(pci_bus_t bus)
727	{
728	pci_fun_t *fun;
729
730	fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
731	if (fun == NULL)
732	return NULL;
733
734	fun->busptr = bus;
735	return fun;
736	}
737
738	void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
739	{
740	fun->bus = bus;
741	fun->dev = dev;
742	fun->fn = fn;
743	fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
744	fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
745	fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
746	fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
747	fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
748	fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
749	}
750
751	void pci_fun_delete(pci_fun_t *fun)
752	{
753	assert(fun != NULL);
754	hw_res_clean_resource_list(&fun->hw_resources);
755	free(fun);
756	}
757
758	char pci_fun_create_name(pci_fun_t fun)
759	{
760	char *name = NULL;
761
762	asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
763	fun->fn);
764	return name;
765	}
766
767	bool pci_alloc_resource_list(pci_fun_t *fun)
768	{
769	fun->hw_resources.resources = fun->resources;
770	return true;
771	}
772
773	void pci_clean_resource_list(pci_fun_t *fun)
774	{
775	fun->hw_resources.resources = NULL;
776	}
777
778	/** Read the base address registers (BARs) of the function and add the addresses
779	* to its HW resource list.
780	*
781	* @param fun PCI function
782	*/
783	void pci_read_bars(pci_fun_t *fun)
784	{
785	/*
786	* Position of the BAR in the PCI configuration address space of the
787	* device.
788	*/
789	int addr = PCI_BASE_ADDR_0;
790
791	while (addr <= PCI_BASE_ADDR_5)
792	addr = pci_read_bar(fun, addr);
793	}
794
795	size_t pci_bar_mask_to_size(uint32_t mask)
796	{
797	size_t size = mask & ~(mask - 1);
798	return size;
799	}
800
801	int main(int argc, char *argv[])
802	{
803	printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
804	pciintel_init();
805	return ddf_driver_main(&pci_driver);
806	}
807
808	/**
809	* @}
810	*/

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