source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 8049b79

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8049b79 was 46eb2c4, checked in by Jakub Jermar <jakub@…>, 12 years ago

Use pio_enable_resource() in pci.
  • Property mode set to 100644
File size: 21.4 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <byteorder.h>
41#include <stdio.h>
42#include <errno.h>
43#include <stdbool.h>
44#include <fibril_synch.h>
45#include <str.h>
46#include <ctype.h>
47#include <macros.h>
48#include <str_error.h>
49
50#include <ddf/driver.h>
51#include <ddf/log.h>
52#include <ipc/dev_iface.h>
53#include <ipc/irc.h>
54#include <ns.h>
55#include <ipc/services.h>
56#include <sysinfo.h>
57#include <ops/hw_res.h>
58#include <device/hw_res.h>
59#include <ops/pio_window.h>
60#include <device/pio_window.h>
61#include <ddi.h>
62#include <pci_dev_iface.h>
63
64#include "pci.h"
65
66#define NAME "pciintel"
67
68#define CONF_ADDR(bus, dev, fn, reg) \
69 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
70
71/** Obtain PCI function soft-state from DDF function node */
72static pci_fun_t *pci_fun(ddf_fun_t *fnode)
73{
74 return ddf_fun_data_get(fnode);
75}
76
77/** Obtain PCI bus soft-state from DDF device node */
78#if 0
79static pci_bus_t *pci_bus(ddf_dev_t *dnode)
80{
81 return ddf_dev_data_get(dnode);
82}
83#endif
84
85/** Obtain PCI bus soft-state from function soft-state */
86static pci_bus_t *pci_bus_from_fun(pci_fun_t *fun)
87{
88 return fun->busptr;
89}
90
91/** Max is 47, align to something nice. */
92#define ID_MAX_STR_LEN 50
93
94static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
95{
96 pci_fun_t *fun = pci_fun(fnode);
97
98 if (fun == NULL)
99 return NULL;
100 return &fun->hw_resources;
101}
102
103static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
104{
105 /* This is an old ugly way */
106 assert(fnode);
107 pci_fun_t *dev_data = pci_fun(fnode);
108
109 sysarg_t apic;
110 sysarg_t i8259;
111
112 async_sess_t *irc_sess = NULL;
113
114 if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
115 || ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
116 irc_sess = service_connect_blocking(EXCHANGE_SERIALIZE,
117 SERVICE_IRC, 0, 0);
118 }
119
120 if (!irc_sess)
121 return false;
122
123 size_t i = 0;
124 hw_resource_list_t *res = &dev_data->hw_resources;
125 for (; i < res->count; i++) {
126 if (res->resources[i].type == INTERRUPT) {
127 const int irq = res->resources[i].res.interrupt.irq;
128
129 async_exch_t *exch = async_exchange_begin(irc_sess);
130 const int rc =
131 async_req_1_0(exch, IRC_ENABLE_INTERRUPT, irq);
132 async_exchange_end(exch);
133
134 if (rc != EOK) {
135 async_hangup(irc_sess);
136 return false;
137 }
138 }
139 }
140
141 async_hangup(irc_sess);
142 return true;
143}
144
145static pio_window_t *pciintel_get_pio_window(ddf_fun_t *fnode)
146{
147 pci_fun_t *fun = pci_fun(fnode);
148
149 if (fun == NULL)
150 return NULL;
151 return &fun->pio_window;
152}
153
154
155static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
156 uint32_t data)
157{
158 if (address > 252)
159 return EINVAL;
160 pci_conf_write_32(pci_fun(fun), address, data);
161 return EOK;
162}
163
164static int pci_config_space_write_16(
165 ddf_fun_t *fun, uint32_t address, uint16_t data)
166{
167 if (address > 254)
168 return EINVAL;
169 pci_conf_write_16(pci_fun(fun), address, data);
170 return EOK;
171}
172
173static int pci_config_space_write_8(
174 ddf_fun_t *fun, uint32_t address, uint8_t data)
175{
176 if (address > 255)
177 return EINVAL;
178 pci_conf_write_8(pci_fun(fun), address, data);
179 return EOK;
180}
181
182static int pci_config_space_read_32(
183 ddf_fun_t *fun, uint32_t address, uint32_t *data)
184{
185 if (address > 252)
186 return EINVAL;
187 *data = pci_conf_read_32(pci_fun(fun), address);
188 return EOK;
189}
190
191static int pci_config_space_read_16(
192 ddf_fun_t *fun, uint32_t address, uint16_t *data)
193{
194 if (address > 254)
195 return EINVAL;
196 *data = pci_conf_read_16(pci_fun(fun), address);
197 return EOK;
198}
199
200static int pci_config_space_read_8(
201 ddf_fun_t *fun, uint32_t address, uint8_t *data)
202{
203 if (address > 255)
204 return EINVAL;
205 *data = pci_conf_read_8(pci_fun(fun), address);
206 return EOK;
207}
208
209static hw_res_ops_t pciintel_hw_res_ops = {
210 .get_resource_list = &pciintel_get_resources,
211 .enable_interrupt = &pciintel_enable_interrupt,
212};
213
214static pio_window_ops_t pciintel_pio_window_ops = {
215 .get_pio_window = &pciintel_get_pio_window
216};
217
218static pci_dev_iface_t pci_dev_ops = {
219 .config_space_read_8 = &pci_config_space_read_8,
220 .config_space_read_16 = &pci_config_space_read_16,
221 .config_space_read_32 = &pci_config_space_read_32,
222 .config_space_write_8 = &pci_config_space_write_8,
223 .config_space_write_16 = &pci_config_space_write_16,
224 .config_space_write_32 = &pci_config_space_write_32
225};
226
227static ddf_dev_ops_t pci_fun_ops = {
228 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
229 .interfaces[PIO_WINDOW_DEV_IFACE] = &pciintel_pio_window_ops,
230 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
231};
232
233static int pci_dev_add(ddf_dev_t *);
234static int pci_fun_online(ddf_fun_t *);
235static int pci_fun_offline(ddf_fun_t *);
236
237/** PCI bus driver standard operations */
238static driver_ops_t pci_ops = {
239 .dev_add = &pci_dev_add,
240 .fun_online = &pci_fun_online,
241 .fun_offline = &pci_fun_offline,
242};
243
244/** PCI bus driver structure */
245static driver_t pci_driver = {
246 .name = NAME,
247 .driver_ops = &pci_ops
248};
249
250static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
251{
252 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
253 pci_bus_t *bus = pci_bus_from_fun(fun);
254 uint32_t val;
255
256 fibril_mutex_lock(&bus->conf_mutex);
257
258 pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
259
260 /*
261 * Always read full 32-bits from the PCI conf_data_port register and
262 * get the desired portion of it afterwards. Some architectures do not
263 * support shorter PIO reads offset from this register.
264 */
265 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
266
267 switch (len) {
268 case 1:
269 *buf = (uint8_t) (val >> ((reg & 3) * 8));
270 break;
271 case 2:
272 *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8);
273 break;
274 case 4:
275 *((uint32_t *) buf) = (uint32_t) val;
276 break;
277 }
278
279 fibril_mutex_unlock(&bus->conf_mutex);
280}
281
282static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
283{
284 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
285 pci_bus_t *bus = pci_bus_from_fun(fun);
286 uint32_t val;
287
288 fibril_mutex_lock(&bus->conf_mutex);
289
290 /*
291 * Prepare to write full 32-bits to the PCI conf_data_port register.
292 * Some architectures do not support shorter PIO writes offset from this
293 * register.
294 */
295
296 if (len < 4) {
297 /*
298 * We have fewer than full 32-bits, so we need to read the
299 * missing bits first.
300 */
301 pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
302 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
303 }
304
305 switch (len) {
306 case 1:
307 val &= ~(0xffU << ((reg & 3) * 8));
308 val |= *buf << ((reg & 3) * 8);
309 break;
310 case 2:
311 val &= ~(0xffffU << ((reg & 3) * 8));
312 val |= *((uint16_t *) buf) << ((reg & 3) * 8);
313 break;
314 case 4:
315 val = *((uint32_t *) buf);
316 break;
317 }
318
319 pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
320 pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
321
322 fibril_mutex_unlock(&bus->conf_mutex);
323}
324
325uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
326{
327 uint8_t res;
328 pci_conf_read(fun, reg, &res, 1);
329 return res;
330}
331
332uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
333{
334 uint16_t res;
335 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
336 return res;
337}
338
339uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
340{
341 uint32_t res;
342 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
343 return res;
344}
345
346void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
347{
348 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
349}
350
351void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
352{
353 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
354}
355
356void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
357{
358 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
359}
360
361void pci_fun_create_match_ids(pci_fun_t *fun)
362{
363 int rc;
364 char match_id_str[ID_MAX_STR_LEN];
365
366 /* Vendor ID & Device ID, length(incl \0) 22 */
367 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04"
368 PRIx16 "&dev=%04" PRIx16, fun->vendor_id, fun->device_id);
369 if (rc < 0) {
370 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
371 str_error(rc));
372 }
373
374 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
375 if (rc != EOK) {
376 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
377 }
378
379 /* Class, subclass, prog IF, revision, length(incl \0) 47 */
380 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
381 "pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
382 fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
383 if (rc < 0) {
384 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
385 str_error(rc));
386 }
387
388 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
389 if (rc != EOK) {
390 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
391 }
392
393 /* Class, subclass, prog IF, length(incl \0) 35 */
394 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
395 "pci/class=%02x&subclass=%02x&progif=%02x",
396 fun->class_code, fun->subclass_code, fun->prog_if);
397 if (rc < 0) {
398 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
399 str_error(rc));
400 }
401
402 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
403 if (rc != EOK) {
404 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
405 }
406
407 /* Class, subclass, length(incl \0) 25 */
408 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
409 "pci/class=%02x&subclass=%02x",
410 fun->class_code, fun->subclass_code);
411 if (rc < 0) {
412 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
413 str_error(rc));
414 }
415
416 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
417 if (rc != EOK) {
418 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
419 }
420
421 /* Class, length(incl \0) 13 */
422 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
423 fun->class_code);
424 if (rc < 0) {
425 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
426 str_error(rc));
427 }
428
429 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
430 if (rc != EOK) {
431 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
432 }
433
434 /* TODO add subsys ids, but those exist only in header type 0 */
435}
436
437void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
438 bool io)
439{
440 hw_resource_list_t *hw_res_list = &fun->hw_resources;
441 hw_resource_t *hw_resources = hw_res_list->resources;
442 size_t count = hw_res_list->count;
443
444 assert(hw_resources != NULL);
445 assert(count < PCI_MAX_HW_RES);
446
447 if (io) {
448 hw_resources[count].type = IO_RANGE;
449 hw_resources[count].res.io_range.address = range_addr;
450 hw_resources[count].res.io_range.size = range_size;
451 hw_resources[count].res.io_range.relative = true;
452 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
453 } else {
454 hw_resources[count].type = MEM_RANGE;
455 hw_resources[count].res.mem_range.address = range_addr;
456 hw_resources[count].res.mem_range.size = range_size;
457 hw_resources[count].res.mem_range.relative = false;
458 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
459 }
460
461 hw_res_list->count++;
462}
463
464/** Read the base address register (BAR) of the device and if it contains valid
465 * address add it to the devices hw resource list.
466 *
467 * @param fun PCI function
468 * @param addr The address of the BAR in the PCI configuration address space of
469 * the device
470 * @return The addr the address of the BAR which should be read next
471 */
472int pci_read_bar(pci_fun_t *fun, int addr)
473{
474 /* Value of the BAR */
475 uint32_t val;
476 uint32_t bar;
477 uint32_t mask;
478
479 /* IO space address */
480 bool io;
481 /* 64-bit wide address */
482 bool addrw64;
483
484 /* Size of the io or memory range specified by the BAR */
485 size_t range_size;
486 /* Beginning of the io or memory range specified by the BAR */
487 uint64_t range_addr;
488
489 /* Get the value of the BAR. */
490 val = pci_conf_read_32(fun, addr);
491
492#define IO_MASK (~0x3)
493#define MEM_MASK (~0xf)
494
495 io = (bool) (val & 1);
496 if (io) {
497 addrw64 = false;
498 mask = IO_MASK;
499 } else {
500 mask = MEM_MASK;
501 switch ((val >> 1) & 3) {
502 case 0:
503 addrw64 = false;
504 break;
505 case 2:
506 addrw64 = true;
507 break;
508 default:
509 /* reserved, go to the next BAR */
510 return addr + 4;
511 }
512 }
513
514 /* Get the address mask. */
515 pci_conf_write_32(fun, addr, 0xffffffff);
516 bar = pci_conf_read_32(fun, addr);
517
518 /*
519 * Unimplemented BARs read back as all 0's.
520 */
521 if (!bar)
522 return addr + (addrw64 ? 8 : 4);
523
524 mask &= bar;
525
526 /* Restore the original value. */
527 pci_conf_write_32(fun, addr, val);
528 val = pci_conf_read_32(fun, addr);
529
530 range_size = pci_bar_mask_to_size(mask);
531
532 if (addrw64) {
533 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
534 (val & 0xfffffff0);
535 } else {
536 range_addr = (val & 0xfffffff0);
537 }
538
539 if (range_addr != 0) {
540 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
541 ", size = %x", ddf_fun_get_name(fun->fnode), range_addr,
542 (unsigned int) range_size);
543 }
544
545 pci_add_range(fun, range_addr, range_size, io);
546
547 if (addrw64)
548 return addr + 8;
549
550 return addr + 4;
551}
552
553void pci_add_interrupt(pci_fun_t *fun, int irq)
554{
555 hw_resource_list_t *hw_res_list = &fun->hw_resources;
556 hw_resource_t *hw_resources = hw_res_list->resources;
557 size_t count = hw_res_list->count;
558
559 assert(NULL != hw_resources);
560 assert(count < PCI_MAX_HW_RES);
561
562 hw_resources[count].type = INTERRUPT;
563 hw_resources[count].res.interrupt.irq = irq;
564
565 hw_res_list->count++;
566
567 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
568}
569
570void pci_read_interrupt(pci_fun_t *fun)
571{
572 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
573 uint8_t pin = pci_conf_read_8(fun, PCI_BRIDGE_INT_PIN);
574
575 if (pin != 0 && irq != 0xff)
576 pci_add_interrupt(fun, irq);
577}
578
579/** Enumerate (recursively) and register the devices connected to a pci bus.
580 *
581 * @param bus Host-to-PCI bridge
582 * @param bus_num Bus number
583 */
584void pci_bus_scan(pci_bus_t *bus, int bus_num)
585{
586 pci_fun_t *fun;
587 int rc;
588
589 int child_bus = 0;
590 int dnum, fnum;
591 bool multi;
592 uint8_t header_type;
593
594 for (dnum = 0; dnum < 32; dnum++) {
595 multi = true;
596 for (fnum = 0; multi && fnum < 8; fnum++) {
597 fun = pci_fun_new(bus);
598
599 pci_fun_init(fun, bus_num, dnum, fnum);
600 if (fun->vendor_id == 0xffff) {
601 pci_fun_delete(fun);
602 /*
603 * The device is not present, go on scanning the
604 * bus.
605 */
606 if (fnum == 0)
607 break;
608 else
609 continue;
610 }
611
612 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
613 if (fnum == 0) {
614 /* Is the device multifunction? */
615 multi = header_type >> 7;
616 }
617 /* Clear the multifunction bit. */
618 header_type = header_type & 0x7F;
619
620 char *fun_name = pci_fun_create_name(fun);
621 if (fun_name == NULL) {
622 ddf_msg(LVL_ERROR, "Out of memory.");
623 pci_fun_delete(fun);
624 return;
625 }
626
627 rc = ddf_fun_set_name(fun->fnode, fun_name);
628 free(fun_name);
629 if (rc != EOK) {
630 ddf_msg(LVL_ERROR, "Failed setting function name.");
631 pci_fun_delete(fun);
632 return;
633 }
634
635 pci_alloc_resource_list(fun);
636 pci_read_bars(fun);
637 pci_read_interrupt(fun);
638
639 /* Propagate the PIO window to the function. */
640 fun->pio_window = bus->pio_win;
641
642 ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
643
644 ddf_msg(LVL_DEBUG, "Adding new function %s.",
645 ddf_fun_get_name(fun->fnode));
646
647 pci_fun_create_match_ids(fun);
648
649 if (ddf_fun_bind(fun->fnode) != EOK) {
650 pci_clean_resource_list(fun);
651 pci_fun_delete(fun);
652 continue;
653 }
654
655 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
656 header_type == PCI_HEADER_TYPE_CARDBUS) {
657 child_bus = pci_conf_read_8(fun,
658 PCI_BRIDGE_SEC_BUS_NUM);
659 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
660 "bridge, secondary bus number = %d.",
661 bus_num);
662 if (child_bus > bus_num)
663 pci_bus_scan(bus, child_bus);
664 }
665 }
666 }
667}
668
669static int pci_dev_add(ddf_dev_t *dnode)
670{
671 hw_resource_list_t hw_resources;
672 pci_bus_t *bus = NULL;
673 ddf_fun_t *ctl = NULL;
674 bool got_res = false;
675 async_sess_t *sess;
676 int rc;
677
678 ddf_msg(LVL_DEBUG, "pci_dev_add");
679
680 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
681 if (bus == NULL) {
682 ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
683 rc = ENOMEM;
684 goto fail;
685 }
686 fibril_mutex_initialize(&bus->conf_mutex);
687
688 bus->dnode = dnode;
689
690 sess = ddf_dev_parent_sess_create(dnode, EXCHANGE_SERIALIZE);
691 if (sess == NULL) {
692 ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
693 "parent driver.");
694 rc = ENOENT;
695 goto fail;
696 }
697
698 rc = pio_window_get(sess, &bus->pio_win);
699 if (rc != EOK) {
700 ddf_msg(LVL_ERROR, "pci_dev_add failed to get PIO window "
701 "for the device.");
702 goto fail;
703 }
704
705 rc = hw_res_get_resource_list(sess, &hw_resources);
706 if (rc != EOK) {
707 ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
708 "for the device.");
709 goto fail;
710 }
711 got_res = true;
712
713
714 assert(hw_resources.count > 1);
715 assert(hw_resources.resources[0].type == IO_RANGE);
716 assert(hw_resources.resources[0].res.io_range.size >= 4);
717
718 assert(hw_resources.resources[1].type == IO_RANGE);
719 assert(hw_resources.resources[1].res.io_range.size >= 4);
720
721 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
722 hw_resources.resources[0].res.io_range.address);
723 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
724 hw_resources.resources[1].res.io_range.address);
725
726 if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0],
727 (void **) &bus->conf_addr_reg)) {
728 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
729 rc = EADDRNOTAVAIL;
730 goto fail;
731 }
732 if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1],
733 (void **) &bus->conf_data_reg)) {
734 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
735 rc = EADDRNOTAVAIL;
736 goto fail;
737 }
738
739 /* Make the bus device more visible. It has no use yet. */
740 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
741
742 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
743 if (ctl == NULL) {
744 ddf_msg(LVL_ERROR, "Failed creating control function.");
745 rc = ENOMEM;
746 goto fail;
747 }
748
749 rc = ddf_fun_bind(ctl);
750 if (rc != EOK) {
751 ddf_msg(LVL_ERROR, "Failed binding control function.");
752 goto fail;
753 }
754
755 /* Enumerate functions. */
756 ddf_msg(LVL_DEBUG, "Scanning the bus");
757 pci_bus_scan(bus, 0);
758
759 hw_res_clean_resource_list(&hw_resources);
760
761 return EOK;
762
763fail:
764 if (got_res)
765 hw_res_clean_resource_list(&hw_resources);
766
767 if (ctl != NULL)
768 ddf_fun_destroy(ctl);
769
770 return rc;
771}
772
773static int pci_fun_online(ddf_fun_t *fun)
774{
775 ddf_msg(LVL_DEBUG, "pci_fun_online()");
776 return ddf_fun_online(fun);
777}
778
779static int pci_fun_offline(ddf_fun_t *fun)
780{
781 ddf_msg(LVL_DEBUG, "pci_fun_offline()");
782 return ddf_fun_offline(fun);
783}
784
785static void pciintel_init(void)
786{
787 ddf_log_init(NAME);
788}
789
790pci_fun_t *pci_fun_new(pci_bus_t *bus)
791{
792 pci_fun_t *fun;
793 ddf_fun_t *fnode;
794
795 fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
796 if (fnode == NULL)
797 return NULL;
798
799 fun = ddf_fun_data_alloc(fnode, sizeof(pci_fun_t));
800 if (fun == NULL)
801 return NULL;
802
803 fun->busptr = bus;
804 fun->fnode = fnode;
805 return fun;
806}
807
808void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
809{
810 fun->bus = bus;
811 fun->dev = dev;
812 fun->fn = fn;
813 fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
814 fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
815
816 /* Explicitly enable PCI bus mastering */
817 fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
818 PCI_COMMAND_MASTER;
819 pci_conf_write_16(fun, PCI_COMMAND, fun->command);
820
821 fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
822 fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
823 fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
824 fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
825}
826
827void pci_fun_delete(pci_fun_t *fun)
828{
829 hw_res_clean_resource_list(&fun->hw_resources);
830 if (fun->fnode != NULL)
831 ddf_fun_destroy(fun->fnode);
832}
833
834char *pci_fun_create_name(pci_fun_t *fun)
835{
836 char *name = NULL;
837
838 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
839 fun->fn);
840 return name;
841}
842
843bool pci_alloc_resource_list(pci_fun_t *fun)
844{
845 fun->hw_resources.resources = fun->resources;
846 return true;
847}
848
849void pci_clean_resource_list(pci_fun_t *fun)
850{
851 fun->hw_resources.resources = NULL;
852}
853
854/** Read the base address registers (BARs) of the function and add the addresses
855 * to its HW resource list.
856 *
857 * @param fun PCI function
858 */
859void pci_read_bars(pci_fun_t *fun)
860{
861 /*
862 * Position of the BAR in the PCI configuration address space of the
863 * device.
864 */
865 int addr = PCI_BASE_ADDR_0;
866
867 while (addr <= PCI_BASE_ADDR_5)
868 addr = pci_read_bar(fun, addr);
869}
870
871size_t pci_bar_mask_to_size(uint32_t mask)
872{
873 size_t size = mask & ~(mask - 1);
874 return size;
875}
876
877int main(int argc, char *argv[])
878{
879 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
880 pciintel_init();
881 return ddf_driver_main(&pci_driver);
882}
883
884/**
885 * @}
886 */
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