source: mainline/uspace/drv/block/ata_bd/ata_hw.h@ 9bfa8c8

Last change on this file since 9bfa8c8 was d7f7a4a, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 3 years ago

Replace some license headers with SPDX identifier

Headers are replaced using tools/transorm-copyright.sh only
when it can be matched verbatim with the license header used
throughout most of the codebase.
  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*
2 * SPDX-FileCopyrightText: 2009 Jiri Svoboda
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/** @addtogroup ata_bd
8 * @{
9 */
10/** @file ATA hardware protocol (registers, data structures).
11 */
12
13#ifndef __ATA_HW_H__
14#define __ATA_HW_H__
15
16#include <stdint.h>
17
18enum {
19 CTL_READ_START = 0,
20 CTL_WRITE_START = 1,
21};
22
23enum {
24 STATUS_FAILURE = 0
25};
26
27enum {
28 MAX_DISKS = 2
29};
30
31/** ATA Command Register Block. */
32typedef union {
33 /* Read/Write */
34 struct {
35 uint16_t data_port;
36 uint8_t sector_count;
37 uint8_t sector_number;
38 uint8_t cylinder_low;
39 uint8_t cylinder_high;
40 uint8_t drive_head;
41 uint8_t pad_rw0;
42 };
43
44 /* Read Only */
45 struct {
46 uint8_t pad_ro0;
47 uint8_t error;
48 uint8_t pad_ro1[5];
49 uint8_t status;
50 };
51
52 /* Write Only */
53 struct {
54 uint8_t pad_wo0;
55 uint8_t features;
56 uint8_t pad_wo1[5];
57 uint8_t command;
58 };
59} ata_cmd_t;
60
61typedef union {
62 /* Read */
63 struct {
64 uint8_t pad0[6];
65 uint8_t alt_status;
66 uint8_t drive_address;
67 };
68
69 /* Write */
70 struct {
71 uint8_t pad1[6];
72 uint8_t device_control;
73 uint8_t pad2;
74 };
75} ata_ctl_t;
76
77enum devctl_bits {
78 DCR_SRST = 0x04, /**< Software Reset */
79 DCR_nIEN = 0x02 /**< Interrupt Enable (negated) */
80};
81
82enum status_bits {
83 SR_BSY = 0x80, /**< Busy */
84 SR_DRDY = 0x40, /**< Drive Ready */
85 SR_DWF = 0x20, /**< Drive Write Fault */
86 SR_DSC = 0x10, /**< Drive Seek Complete */
87 SR_DRQ = 0x08, /**< Data Request */
88 SR_CORR = 0x04, /**< Corrected Data */
89 SR_IDX = 0x02, /**< Index */
90 SR_ERR = 0x01 /**< Error */
91};
92
93enum drive_head_bits {
94 DHR_LBA = 0x40, /**< Use LBA addressing mode */
95 DHR_DRV = 0x10 /**< Select device 1 */
96};
97
98enum error_bits {
99 ER_BBK = 0x80, /**< Bad Block Detected */
100 ER_UNC = 0x40, /**< Uncorrectable Data Error */
101 ER_MC = 0x20, /**< Media Changed */
102 ER_IDNF = 0x10, /**< ID Not Found */
103 ER_MCR = 0x08, /**< Media Change Request */
104 ER_ABRT = 0x04, /**< Aborted Command */
105 ER_TK0NF = 0x02, /**< Track 0 Not Found */
106 ER_AMNF = 0x01 /**< Address Mark Not Found */
107};
108
109enum ata_command {
110 CMD_READ_SECTORS = 0x20,
111 CMD_READ_SECTORS_EXT = 0x24,
112 CMD_WRITE_SECTORS = 0x30,
113 CMD_WRITE_SECTORS_EXT = 0x34,
114 CMD_PACKET = 0xA0,
115 CMD_IDENTIFY_PKT_DEV = 0xA1,
116 CMD_IDENTIFY_DRIVE = 0xEC,
117 CMD_FLUSH_CACHE = 0xE7
118};
119
120/** Data returned from identify device and identify packet device command. */
121typedef struct {
122 uint16_t gen_conf;
123 uint16_t cylinders;
124 uint16_t _res2;
125 uint16_t heads;
126 uint16_t _vs4;
127 uint16_t _vs5;
128 uint16_t sectors;
129 uint16_t _vs7;
130 uint16_t _vs8;
131 uint16_t _vs9;
132
133 uint16_t serial_number[10];
134 uint16_t _vs20;
135 uint16_t _vs21;
136 uint16_t vs_bytes;
137 uint16_t firmware_rev[4];
138 uint16_t model_name[20];
139
140 uint16_t max_rw_multiple;
141 uint16_t _res48;
142 uint16_t caps; /* Different meaning for packet device */
143 uint16_t _res50;
144 uint16_t pio_timing;
145 uint16_t dma_timing;
146
147 uint16_t validity;
148 uint16_t cur_cyl;
149 uint16_t cur_heads;
150 uint16_t cur_sectors;
151 uint16_t cur_capacity0;
152 uint16_t cur_capacity1;
153 uint16_t mss;
154 uint16_t total_lba28_0;
155 uint16_t total_lba28_1;
156 uint16_t sw_dma;
157 uint16_t mw_dma;
158 uint16_t pio_modes;
159 uint16_t min_mw_dma_cycle;
160 uint16_t rec_mw_dma_cycle;
161 uint16_t min_raw_pio_cycle;
162 uint16_t min_iordy_pio_cycle;
163
164 uint16_t _res69;
165 uint16_t _res70;
166 uint16_t _res71;
167 uint16_t _res72;
168 uint16_t _res73;
169 uint16_t _res74;
170
171 uint16_t queue_depth;
172 uint16_t _res76[1 + 79 - 76];
173 uint16_t version_maj;
174 uint16_t version_min;
175 uint16_t cmd_set0;
176 uint16_t cmd_set1;
177 uint16_t csf_sup_ext;
178 uint16_t csf_enabled0;
179 uint16_t csf_enabled1;
180 uint16_t csf_default;
181 uint16_t udma;
182
183 uint16_t _res89[1 + 99 - 89];
184
185 /* Total number of blocks in LBA-48 addressing */
186 uint16_t total_lba48_0;
187 uint16_t total_lba48_1;
188 uint16_t total_lba48_2;
189 uint16_t total_lba48_3;
190
191 /* Note: more fields are defined in ATA/ATAPI-7 */
192 uint16_t _res104[1 + 127 - 104];
193 uint16_t _vs128[1 + 159 - 128];
194 uint16_t _res160[1 + 255 - 160];
195} identify_data_t;
196
197/** Capability bits for register device. */
198enum ata_regdev_caps {
199 rd_cap_iordy = 0x0800,
200 rd_cap_iordy_cbd = 0x0400,
201 rd_cap_lba = 0x0200,
202 rd_cap_dma = 0x0100
203};
204
205/** Capability bits for packet device. */
206enum ata_pktdev_caps {
207 pd_cap_ildma = 0x8000,
208 pd_cap_cmdqueue = 0x4000,
209 pd_cap_overlap = 0x2000,
210 pd_cap_need_softreset = 0x1000, /* Obsolete (ATAPI-6) */
211 pd_cap_iordy = 0x0800,
212 pd_cap_iordy_dis = 0x0400,
213 pd_cap_lba = 0x0200, /* Must be on */
214 pd_cap_dma = 0x0100
215};
216
217/** Bits of @c identify_data_t.cmd_set1 */
218enum ata_cs1 {
219 cs1_addr48 = 0x0400 /**< 48-bit address feature set */
220};
221
222/** Extract value of device type from scsi_std_inquiry_data_t.pqual_devtype */
223#define INQUIRY_PDEV_TYPE(val) ((val) & 0x1f)
224
225enum ata_pdev_signature {
226 /**
227 * Signature put by a packet device in byte count register
228 * in response to Identify command.
229 */
230 PDEV_SIGNATURE_BC = 0xEB14
231};
232
233#endif
234
235/** @}
236 */
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