source: mainline/uspace/drv/audio/hdaudio/spec/regs.h@ a35b458

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since a35b458 was 5b0cf63, checked in by Jiri Svoboda <jiri@…>, 8 years ago

A round of cstyle fixing (i.e. run make ccheck-fix).
  • Property mode set to 100644
File size: 7.4 KB
Line 
1/*
2 * Copyright (c) 2014 Jiri Svoboda
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup hdaudio
30 * @{
31 */
32/** @file High Definition Audio register interface
33 */
34
35#ifndef SPEC_REGS_H
36#define SPEC_REGS_H
37
38#include <stdint.h>
39
40/** Stream Descriptor registers */
41typedef struct {
42 /** Control 1 */
43 uint8_t ctl1;
44 /** Control 2 */
45 uint8_t ctl2;
46 /** Control 3 */
47 uint8_t ctl3;
48 /** Status */
49 uint8_t sts;
50 /** Link Position in Current Buffer */
51 uint32_t lpib;
52 /** Cyclic Buffer Length */
53 uint32_t cbl;
54 /** Last Valid Index */
55 uint16_t lvi;
56 /** Reserved */
57 uint8_t reserved1[2];
58 /** FIFO Size */
59 uint16_t fifod;
60 /** Format */
61 uint16_t fmt;
62 /** Reserved */
63 uint8_t reserved2[4];
64 /** Buffer Descriptor List Pointer - Lower */
65 uint32_t bdpl;
66 /** Buffer Descriptor List Pointer - Upper */
67 uint32_t bdpu;
68} hda_sdesc_regs_t;
69
70typedef struct {
71 /** Global Capabilities */
72 uint16_t gcap;
73 /** Minor Version */
74 uint8_t vmin;
75 /** Major Version */
76 uint8_t vmaj;
77 /** Output Payload Capability */
78 uint16_t outpay;
79 /** Input Payload Capability */
80 uint16_t inpay;
81 /** Global Control */
82 uint32_t gctl;
83 /** Wake Enable */
84 uint16_t wakeen;
85 /** State Change Status */
86 uint16_t statests;
87 /** Global Status */
88 uint16_t gsts;
89 /** Reserved */
90 uint8_t reserved1[6];
91 /** Output Stream Payload Capability */
92 uint16_t outstrmpay;
93 /** Input Stream Payload Capability */
94 uint16_t instrmpay;
95 /** Reserved */
96 uint8_t reserved2[4];
97 /** Interrupt Control */
98 uint32_t intctl;
99 /** Interrupt Status */
100 uint32_t intsts;
101 /** Reserved */
102 uint8_t reserved3[8];
103 /** Wall Clock Counter */
104 uint32_t walclk;
105 /** Reserved */
106 uint8_t reserved4[4];
107 /** Stream Synchronization */
108 uint32_t ssync;
109 /** Reserved */
110 uint8_t reserved5[4];
111 /** CORB Lower Base Address */
112 uint32_t corblbase;
113 /** CORB Upper Base Address */
114 uint32_t corbubase;
115 /** CORB Write Pointer */
116 uint16_t corbwp;
117 /** CORB Read Pointer */
118 uint16_t corbrp;
119 /** CORB Control */
120 uint8_t corbctl;
121 /** CORB Status */
122 uint8_t corbsts;
123 /** CORB Size */
124 uint8_t corbsize;
125 /** Reserved */
126 uint8_t reserved6[1];
127 /** RIRB Lower Base Address */
128 uint32_t rirblbase;
129 /** RIRB Upper Base Address */
130 uint32_t rirbubase;
131 /** RIRB Write Pointer */
132 uint16_t rirbwp;
133 /** Response Interrupt Count */
134 uint16_t rintcnt;
135 /** RIRB Control */
136 uint8_t rirbctl;
137 /** RIRB Status */
138 uint8_t rirbsts;
139 /** RIRB Size */
140 uint8_t rirbsize;
141 /** Reserved */
142 uint8_t reserved7[1];
143 /** Immediate Command Output Interface */
144 uint32_t icoi;
145 /** Immediate Command Input Interface */
146 uint32_t icii;
147 /** Immediate Command Status */
148 uint16_t icis;
149 /** Reserved */
150 uint8_t reserved8[6];
151 /** DMA Position Buffer Lower Base */
152 uint32_t dplbase;
153 /** DMA Position Buffer Upper Base */
154 uint32_t dpubase;
155 /** Reserved */
156 uint8_t reserved9[8];
157 /** Stream descriptor registers */
158 hda_sdesc_regs_t sdesc[64];
159 /** Fill up to 0x2030 */
160 uint8_t reserved10[6064];
161 /** Wall Clock Counter Alias */
162 uint32_t walclka;
163 /** Stream Descriptor Link Position in Current Buffer */
164 uint32_t sdlpiba[64];
165} hda_regs_t;
166
167typedef enum {
168 /** Descriptor Error Interrupt Enable */
169 sdctl1_deie = 4,
170 /** FIFO Error Interrupt Enable */
171 sdctl1_feie = 3,
172 /** Interrupt on Completion Enable */
173 sdctl1_ioce = 2,
174 /** Stream Run */
175 sdctl1_run = 1,
176 /** Stream Reset */
177 sdctl1_srst = 0
178} hda_sdesc_ctl1_bits;
179
180typedef enum {
181 /** Number of Output Streams Supported (H) */
182 gcap_oss_h = 15,
183 /** Number of Output Streams Supported (L) */
184 gcap_oss_l = 12,
185 /** Number of Input Streams Supported (H) */
186 gcap_iss_h = 11,
187 /** Number of Input Streams Supported (L) */
188 gcap_iss_l = 8,
189 /** Number of Bidirectional Streams Supported (H) */
190 gcap_bss_h = 7,
191 /** Number of Bidirectional Streams Supported (L) */
192 gcap_bss_l = 3,
193 /** Number of Serial Data Out Signals (H) */
194 gcap_nsdo_h = 2,
195 /** Number of Serial Data Out Signals (H) */
196 gcap_nsdo_l = 1,
197 /** 64 Bit Address Supported */
198 gcap_64ok = 0
199} hda_gcap_bits_t;
200
201typedef enum {
202 /** Accept Unsolicited Response Enable */
203 gctl_unsol = 8,
204 /** Flush Control */
205 gctl_fcntrl = 1,
206 /** Controller Reset */
207 gctl_crst = 0
208} hda_gctl_bits_t;
209
210typedef enum {
211 /** Global Interrupt Enable */
212 intctl_gie = 31,
213 /** Controller Interrupt Enable */
214 intctl_cie = 30,
215 /** Stream Interrupt Enable */
216 intctl_sie = 29
217} hda_intctl_bits_t;
218
219typedef enum {
220 /** CORB Read Pointer Reset */
221 corbrp_rst = 15,
222 /** CORB Read Pointer (H) */
223 corbrp_rp_h = 7,
224 /** CORB Read Pointer (L) */
225 corbrp_rp_l = 0
226} hda_corbrp_bits_t;
227
228typedef enum {
229 /** CORB Write Pointer (H) */
230 corbwp_wp_h = 7,
231 /** CORB Write Pointer (L) */
232 corbwp_wp_l = 0
233} hda_corbwp_bits_t;
234
235typedef enum {
236 /** Enable CORB DMA Engine */
237 corbctl_run = 1,
238 /** CORB Memory Error Interrupt Enable */
239 corbctl_meie = 0
240} hda_corbctl_bits_t;
241
242typedef enum {
243 /** CORB Size Capability (H) */
244 corbsize_cap_h = 7,
245 /** CORB Size Capability (L) */
246 corbsize_cap_l = 4,
247 /** CORB Size (H) */
248 corbsize_size_h = 1,
249 /** CORB Size (L) */
250 corbsize_size_l = 0
251} hda_corbsize_bits_t;
252
253typedef enum {
254 /** RIRB Write Pointer Reset */
255 rirbwp_rst = 15,
256 /** RIRB Write Pointer (H) */
257 rirbwp_wp_h = 7,
258 /** RIRB Write Pointer (L) */
259 rirbwp_wp_l = 0
260} hda_rirbwp_bits_t;
261
262typedef enum {
263 /** Response Overrun Interrupt Control */
264 rirbctl_oic = 2,
265 /** RIRB DMA Enable */
266 rirbctl_run = 1,
267 /** CORB Memory Error Interrupt Enable */
268 rirbctl_int = 0
269} hda_rirbctl_bits_t;
270
271typedef enum {
272 /** Response Overrun Interrupt Status */
273 rirbsts_ois = 2,
274 /** Response Interrupt */
275 rirbsts_intfl = 0
276} hda_rirbsts_bits_t;
277
278typedef enum {
279 /** RIRB Size Capability (H) */
280 rirbsize_cap_h = 7,
281 /** RIRB Size Capability (L) */
282 rirbsize_cap_l = 4,
283 /** RIRB Size (H) */
284 rirbsize_size_h = 1,
285 /** RIRB Size (L) */
286 rirbsize_size_l = 0
287} hda_rirbsize_bits_t;
288
289typedef struct {
290 /** Response - data received from codec */
291 uint32_t resp;
292 /** Response Extended - added by controller */
293 uint32_t respex;
294} hda_rirb_entry_t;
295
296typedef enum {
297 /** Unsolicited response */
298 respex_unsol = 4,
299 /** Codec Address (H) */
300 respex_addr_h = 3,
301 /** Codec Address (L) */
302 respex_addr_l = 0
303} hda_respex_bits_t;
304
305#endif
306
307/** @}
308 */
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