source: mainline/uspace/drv/audio/hdaudio/spec/regs.h

Last change on this file was 0d59ea7e, checked in by Jiri Svoboda <jiri@…>, 3 years ago

Multiple HD Audio converters cannot pull from a single stream

We select one arbitrary output converter for out PCM output, similar to what
we do for input.

We filter the 'other' VirtualBox output converters based on rates/formats
being zero.
  • Property mode set to 100644
File size: 7.7 KB
Line 
1/*
2 * Copyright (c) 2022 Jiri Svoboda
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup hdaudio
30 * @{
31 */
32/** @file High Definition Audio register interface
33 */
34
35#ifndef SPEC_REGS_H
36#define SPEC_REGS_H
37
38#include <stdint.h>
39
40/** Stream Descriptor registers */
41typedef struct {
42 /** Control 1 */
43 uint8_t ctl1;
44 /** Control 2 */
45 uint8_t ctl2;
46 /** Control 3 */
47 uint8_t ctl3;
48 /** Status */
49 uint8_t sts;
50 /** Link Position in Current Buffer */
51 uint32_t lpib;
52 /** Cyclic Buffer Length */
53 uint32_t cbl;
54 /** Last Valid Index */
55 uint16_t lvi;
56 /** Reserved */
57 uint8_t reserved1[2];
58 /** FIFO Size */
59 uint16_t fifod;
60 /** Format */
61 uint16_t fmt;
62 /** Reserved */
63 uint8_t reserved2[4];
64 /** Buffer Descriptor List Pointer - Lower */
65 uint32_t bdpl;
66 /** Buffer Descriptor List Pointer - Upper */
67 uint32_t bdpu;
68} hda_sdesc_regs_t;
69
70typedef struct {
71 /** Global Capabilities */
72 uint16_t gcap;
73 /** Minor Version */
74 uint8_t vmin;
75 /** Major Version */
76 uint8_t vmaj;
77 /** Output Payload Capability */
78 uint16_t outpay;
79 /** Input Payload Capability */
80 uint16_t inpay;
81 /** Global Control */
82 uint32_t gctl;
83 /** Wake Enable */
84 uint16_t wakeen;
85 /** State Change Status */
86 uint16_t statests;
87 /** Global Status */
88 uint16_t gsts;
89 /** Reserved */
90 uint8_t reserved1[6];
91 /** Output Stream Payload Capability */
92 uint16_t outstrmpay;
93 /** Input Stream Payload Capability */
94 uint16_t instrmpay;
95 /** Reserved */
96 uint8_t reserved2[4];
97 /** Interrupt Control */
98 uint32_t intctl;
99 /** Interrupt Status */
100 uint32_t intsts;
101 /** Reserved */
102 uint8_t reserved3[8];
103 /** Wall Clock Counter */
104 uint32_t walclk;
105 /** Reserved */
106 uint8_t reserved4[4];
107 /** Stream Synchronization */
108 uint32_t ssync;
109 /** Reserved */
110 uint8_t reserved5[4];
111 /** CORB Lower Base Address */
112 uint32_t corblbase;
113 /** CORB Upper Base Address */
114 uint32_t corbubase;
115 /** CORB Write Pointer */
116 uint16_t corbwp;
117 /** CORB Read Pointer */
118 uint16_t corbrp;
119 /** CORB Control */
120 uint8_t corbctl;
121 /** CORB Status */
122 uint8_t corbsts;
123 /** CORB Size */
124 uint8_t corbsize;
125 /** Reserved */
126 uint8_t reserved6[1];
127 /** RIRB Lower Base Address */
128 uint32_t rirblbase;
129 /** RIRB Upper Base Address */
130 uint32_t rirbubase;
131 /** RIRB Write Pointer */
132 uint16_t rirbwp;
133 /** Response Interrupt Count */
134 uint16_t rintcnt;
135 /** RIRB Control */
136 uint8_t rirbctl;
137 /** RIRB Status */
138 uint8_t rirbsts;
139 /** RIRB Size */
140 uint8_t rirbsize;
141 /** Reserved */
142 uint8_t reserved7[1];
143 /** Immediate Command Output Interface */
144 uint32_t icoi;
145 /** Immediate Command Input Interface */
146 uint32_t icii;
147 /** Immediate Command Status */
148 uint16_t icis;
149 /** Reserved */
150 uint8_t reserved8[6];
151 /** DMA Position Buffer Lower Base */
152 uint32_t dplbase;
153 /** DMA Position Buffer Upper Base */
154 uint32_t dpubase;
155 /** Reserved */
156 uint8_t reserved9[8];
157 /** Stream descriptor registers */
158 hda_sdesc_regs_t sdesc[64];
159 /** Fill up to 0x2030 */
160 uint8_t reserved10[6064];
161 /** Wall Clock Counter Alias */
162 uint32_t walclka;
163 /** Stream Descriptor Link Position in Current Buffer */
164 uint32_t sdlpiba[64];
165} hda_regs_t;
166
167/** Stream Descriptor Control bits */
168typedef enum {
169 /** Descriptor Error Interrupt Enable */
170 sdctl1_deie = 4,
171 /** FIFO Error Interrupt Enable */
172 sdctl1_feie = 3,
173 /** Interrupt on Completion Enable */
174 sdctl1_ioce = 2,
175 /** Stream Run */
176 sdctl1_run = 1,
177 /** Stream Reset */
178 sdctl1_srst = 0
179} hda_sdesc_ctl1_bits;
180
181/** Stream Descriptor Status bits */
182typedef enum {
183 /** FIFO Ready */
184 sdctl1_fifordy = 3,
185 /** Descriptor Error */
186 sdsts_dese = 2,
187 /** FIFO Error */
188 sdsts_fifoe = 1,
189 /** Buffer Completion Interrupt Status */
190 sdsts_bcis = 2
191} hda_sdesc_sts_bits;
192
193typedef enum {
194 /** Number of Output Streams Supported (H) */
195 gcap_oss_h = 15,
196 /** Number of Output Streams Supported (L) */
197 gcap_oss_l = 12,
198 /** Number of Input Streams Supported (H) */
199 gcap_iss_h = 11,
200 /** Number of Input Streams Supported (L) */
201 gcap_iss_l = 8,
202 /** Number of Bidirectional Streams Supported (H) */
203 gcap_bss_h = 7,
204 /** Number of Bidirectional Streams Supported (L) */
205 gcap_bss_l = 3,
206 /** Number of Serial Data Out Signals (H) */
207 gcap_nsdo_h = 2,
208 /** Number of Serial Data Out Signals (H) */
209 gcap_nsdo_l = 1,
210 /** 64 Bit Address Supported */
211 gcap_64ok = 0
212} hda_gcap_bits_t;
213
214typedef enum {
215 /** Accept Unsolicited Response Enable */
216 gctl_unsol = 8,
217 /** Flush Control */
218 gctl_fcntrl = 1,
219 /** Controller Reset */
220 gctl_crst = 0
221} hda_gctl_bits_t;
222
223typedef enum {
224 /** Global Interrupt Enable */
225 intctl_gie = 31,
226 /** Controller Interrupt Enable */
227 intctl_cie = 30,
228 /** Stream Interrupt Enable */
229 intctl_sie = 29
230} hda_intctl_bits_t;
231
232typedef enum {
233 /** CORB Read Pointer Reset */
234 corbrp_rst = 15,
235 /** CORB Read Pointer (H) */
236 corbrp_rp_h = 7,
237 /** CORB Read Pointer (L) */
238 corbrp_rp_l = 0
239} hda_corbrp_bits_t;
240
241typedef enum {
242 /** CORB Write Pointer (H) */
243 corbwp_wp_h = 7,
244 /** CORB Write Pointer (L) */
245 corbwp_wp_l = 0
246} hda_corbwp_bits_t;
247
248typedef enum {
249 /** Enable CORB DMA Engine */
250 corbctl_run = 1,
251 /** CORB Memory Error Interrupt Enable */
252 corbctl_meie = 0
253} hda_corbctl_bits_t;
254
255typedef enum {
256 /** CORB Size Capability (H) */
257 corbsize_cap_h = 7,
258 /** CORB Size Capability (L) */
259 corbsize_cap_l = 4,
260 /** CORB Size (H) */
261 corbsize_size_h = 1,
262 /** CORB Size (L) */
263 corbsize_size_l = 0
264} hda_corbsize_bits_t;
265
266typedef enum {
267 /** RIRB Write Pointer Reset */
268 rirbwp_rst = 15,
269 /** RIRB Write Pointer (H) */
270 rirbwp_wp_h = 7,
271 /** RIRB Write Pointer (L) */
272 rirbwp_wp_l = 0
273} hda_rirbwp_bits_t;
274
275typedef enum {
276 /** Response Overrun Interrupt Control */
277 rirbctl_oic = 2,
278 /** RIRB DMA Enable */
279 rirbctl_run = 1,
280 /** CORB Memory Error Interrupt Enable */
281 rirbctl_int = 0
282} hda_rirbctl_bits_t;
283
284typedef enum {
285 /** Response Overrun Interrupt Status */
286 rirbsts_ois = 2,
287 /** Response Interrupt */
288 rirbsts_intfl = 0
289} hda_rirbsts_bits_t;
290
291typedef enum {
292 /** RIRB Size Capability (H) */
293 rirbsize_cap_h = 7,
294 /** RIRB Size Capability (L) */
295 rirbsize_cap_l = 4,
296 /** RIRB Size (H) */
297 rirbsize_size_h = 1,
298 /** RIRB Size (L) */
299 rirbsize_size_l = 0
300} hda_rirbsize_bits_t;
301
302typedef struct {
303 /** Response - data received from codec */
304 uint32_t resp;
305 /** Response Extended - added by controller */
306 uint32_t respex;
307} hda_rirb_entry_t;
308
309typedef enum {
310 /** Unsolicited response */
311 respex_unsol = 4,
312 /** Codec Address (H) */
313 respex_addr_h = 3,
314 /** Codec Address (L) */
315 respex_addr_l = 0
316} hda_respex_bits_t;
317
318#endif
319
320/** @}
321 */
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