source: mainline/libc/arch/mips32/src/syscall.c@ 06b0d112

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 06b0d112 was 7fc78da, checked in by Ondrej Palkovsky <ondrap@…>, 19 years ago

New IPC synchronous call.
Widened syscall to support up to 5 parameters.

  • Property mode set to 100644
File size: 2.1 KB
RevLine 
[b861b58]1/*
2 * Copyright (C) 2005 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <libc.h>
30
[b419162]31sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2,
[7fc78da]32 const sysarg_t p3, const sysarg_t p4,
33 const syscall_t id)
[b861b58]34{
[3a6d6656]35 register sysarg_t __mips_reg_a0 asm("$4") = p1;
36 register sysarg_t __mips_reg_a1 asm("$5") = p2;
37 register sysarg_t __mips_reg_a2 asm("$6") = p3;
[7fc78da]38 register sysarg_t __mips_reg_a3 asm("$7") = p4;
39 register sysarg_t __mips_reg_t0 asm("$8") = id;
[3a6d6656]40 register sysarg_t __mips_reg_v0 asm("$2");
[b861b58]41
42 asm volatile (
43 "syscall\n"
[cc6f688]44 : "=r" (__mips_reg_v0)
[b861b58]45 : "r" (__mips_reg_a0),
46 "r" (__mips_reg_a1),
47 "r" (__mips_reg_a2),
[7fc78da]48 "r" (__mips_reg_a3),
49 "r" (__mips_reg_t0)
[b861b58]50 );
[cc6f688]51
52 return __mips_reg_v0;
[b861b58]53}
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