source: mainline/kernel/generic/src/mm/tlb.c@ 49eb681

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 49eb681 was 49eb681, checked in by Martin Decky <martin@…>, 15 years ago

code cleanup (no change in functionality)

  • Property mode set to 100644
File size: 5.1 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[cc73a8a1]29/** @addtogroup genericmm
[b45c443]30 * @{
31 */
32
[9179d0a]33/**
[b45c443]34 * @file
[da1bafb]35 * @brief Generic TLB shootdown algorithm.
[2bb8648]36 *
37 * The algorithm implemented here is based on the CMU TLB shootdown
38 * algorithm and is further simplified (e.g. all CPUs receive all TLB
39 * shootdown messages).
[9179d0a]40 */
41
[f761f1eb]42#include <mm/tlb.h>
[d1e414c]43#include <mm/asid.h>
[ce031f0]44#include <arch/mm/tlb.h>
[4ffa9e0]45#include <smp/ipi.h>
[169587a]46#include <synch/spinlock.h>
[23684b7]47#include <atomic.h>
[4ffa9e0]48#include <arch/interrupt.h>
[169587a]49#include <config.h>
[434f700]50#include <arch.h>
[02055415]51#include <panic.h>
[d1e414c]52#include <debug.h>
[b3f8fb7]53#include <cpu.h>
[f761f1eb]54
[169587a]55void tlb_init(void)
56{
[b00fdde]57 tlb_arch_init();
[169587a]58}
59
[5f85c91]60#ifdef CONFIG_SMP
[d1e414c]61
[da1bafb]62/**
63 * This lock is used for synchronisation between sender and
64 * recipients of TLB shootdown message. It must be acquired
65 * before CPU structure lock.
66 *
67 */
68IRQ_SPINLOCK_STATIC_INITIALIZE(tlblock);
69
[d1e414c]70/** Send TLB shootdown message.
71 *
72 * This function attempts to deliver TLB shootdown message
73 * to all other processors.
74 *
[05e3cb8]75 * @param type Type describing scope of shootdown.
76 * @param asid Address space, if required by type.
77 * @param page Virtual page address, if required by type.
78 * @param count Number of pages, if required by type.
[da1bafb]79 *
[402eda5]80 * @return The interrupt priority level as it existed prior to this call.
[05e3cb8]81 *
[d1e414c]82 */
[402eda5]83ipl_t tlb_shootdown_start(tlb_invalidate_type_t type, asid_t asid,
[98000fb]84 uintptr_t page, size_t count)
[169587a]85{
[05e3cb8]86 ipl_t ipl = interrupts_disable();
[da1bafb]87 CPU->tlb_active = false;
[402eda5]88 irq_spinlock_lock(&tlblock, false);
[4512d7e]89
[da1bafb]90 size_t i;
[d1e414c]91 for (i = 0; i < config.cpu_count; i++) {
92 if (i == CPU->id)
93 continue;
[da1bafb]94
[05e3cb8]95 cpu_t *cpu = &cpus[i];
[49eb681]96
[da1bafb]97 irq_spinlock_lock(&cpu->lock, false);
[d1e414c]98 if (cpu->tlb_messages_count == TLB_MESSAGE_QUEUE_LEN) {
99 /*
100 * The message queue is full.
101 * Erase the queue and store one TLB_INVL_ALL message.
102 */
103 cpu->tlb_messages_count = 1;
104 cpu->tlb_messages[0].type = TLB_INVL_ALL;
105 cpu->tlb_messages[0].asid = ASID_INVALID;
106 cpu->tlb_messages[0].page = 0;
107 cpu->tlb_messages[0].count = 0;
108 } else {
109 /*
110 * Enqueue the message.
111 */
[98000fb]112 size_t idx = cpu->tlb_messages_count++;
[4638401]113 cpu->tlb_messages[idx].type = type;
114 cpu->tlb_messages[idx].asid = asid;
115 cpu->tlb_messages[idx].page = page;
116 cpu->tlb_messages[idx].count = count;
[d1e414c]117 }
[da1bafb]118 irq_spinlock_unlock(&cpu->lock, false);
[d1e414c]119 }
[36b01bb2]120
[b109ebb]121 tlb_shootdown_ipi_send();
[da1bafb]122
123busy_wait:
[49eb681]124 for (i = 0; i < config.cpu_count; i++) {
[434f700]125 if (cpus[i].tlb_active)
126 goto busy_wait;
[49eb681]127 }
[05e3cb8]128
[402eda5]129 return ipl;
[169587a]130}
131
[da1bafb]132/** Finish TLB shootdown sequence.
133 *
[05e3cb8]134 * @param ipl Previous interrupt priority level.
135 *
[da1bafb]136 */
[402eda5]137void tlb_shootdown_finalize(ipl_t ipl)
[169587a]138{
[402eda5]139 irq_spinlock_unlock(&tlblock, false);
[da1bafb]140 CPU->tlb_active = true;
[402eda5]141 interrupts_restore(ipl);
[169587a]142}
143
[4ffa9e0]144void tlb_shootdown_ipi_send(void)
145{
146 ipi_broadcast(VECTOR_TLB_SHOOTDOWN_IPI);
147}
148
[da1bafb]149/** Receive TLB shootdown message.
150 *
151 */
[b109ebb]152void tlb_shootdown_ipi_recv(void)
[f761f1eb]153{
[97b64c9]154 ASSERT(CPU);
155
[da1bafb]156 CPU->tlb_active = false;
157 irq_spinlock_lock(&tlblock, false);
158 irq_spinlock_unlock(&tlblock, false);
[d1e414c]159
[da1bafb]160 irq_spinlock_lock(&CPU->lock, false);
[d1e414c]161 ASSERT(CPU->tlb_messages_count <= TLB_MESSAGE_QUEUE_LEN);
[da1bafb]162
163 size_t i;
[d1e414c]164 for (i = 0; i < CPU->tlb_messages_count; CPU->tlb_messages_count--) {
[da1bafb]165 tlb_invalidate_type_t type = CPU->tlb_messages[i].type;
166 asid_t asid = CPU->tlb_messages[i].asid;
167 uintptr_t page = CPU->tlb_messages[i].page;
168 size_t count = CPU->tlb_messages[i].count;
169
[d1e414c]170 switch (type) {
[00b38a3]171 case TLB_INVL_ALL:
[d1e414c]172 tlb_invalidate_all();
173 break;
[00b38a3]174 case TLB_INVL_ASID:
[d1e414c]175 tlb_invalidate_asid(asid);
176 break;
[00b38a3]177 case TLB_INVL_PAGES:
[da1bafb]178 ASSERT(count);
[d1e414c]179 tlb_invalidate_pages(asid, page, count);
180 break;
[00b38a3]181 default:
[f651e80]182 panic("Unknown type (%d).", type);
[d1e414c]183 break;
184 }
[da1bafb]185
[d1e414c]186 if (type == TLB_INVL_ALL)
187 break;
188 }
189
[da1bafb]190 irq_spinlock_unlock(&CPU->lock, false);
191 CPU->tlb_active = true;
[f761f1eb]192}
[d1e414c]193
[5f85c91]194#endif /* CONFIG_SMP */
[b45c443]195
[cc73a8a1]196/** @}
[b45c443]197 */
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