[0d107f31] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Jakub Jermar
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[0d107f31] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[7dcf22a] | 29 | /** @addtogroup genericddi
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[0d107f31] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #ifndef KERN_IRQ_H_
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| 36 | #define KERN_IRQ_H_
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| 37 |
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[da1bafb] | 38 | #ifdef KERNEL
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| 39 |
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| 40 | #include <typedefs.h>
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| 41 | #include <adt/list.h>
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| 42 | #include <adt/hash_table.h>
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| 43 | #include <synch/spinlock.h>
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| 44 | #include <proc/task.h>
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| 45 | #include <ipc/ipc.h>
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| 46 |
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| 47 | #endif /* KERNEL */
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| 48 |
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[b3f8fb7] | 49 | typedef enum {
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[22af3af] | 50 | /** Read 1 byte from the I/O space. */
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[cecb0789] | 51 | CMD_PIO_READ_8 = 1,
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[22af3af] | 52 | /** Read 2 bytes from the I/O space. */
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[cecb0789] | 53 | CMD_PIO_READ_16,
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[22af3af] | 54 | /** Read 4 bytes from the I/O space. */
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[cecb0789] | 55 | CMD_PIO_READ_32,
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[9cdac5a] | 56 |
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[22af3af] | 57 | /** Write 1 byte to the I/O space. */
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[cecb0789] | 58 | CMD_PIO_WRITE_8,
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[22af3af] | 59 | /** Write 2 bytes to the I/O space. */
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[cecb0789] | 60 | CMD_PIO_WRITE_16,
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[22af3af] | 61 | /** Write 4 bytes to the I/O space. */
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[cecb0789] | 62 | CMD_PIO_WRITE_32,
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[da1bafb] | 63 |
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[22af3af] | 64 | /**
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[9cdac5a] | 65 | * Write 1 byte from the source argument
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| 66 | * to the I/O space.
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| 67 | */
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| 68 | CMD_PIO_WRITE_A_8,
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| 69 | /**
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| 70 | * Write 2 bytes from the source argument
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| 71 | * to the I/O space.
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| 72 | */
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| 73 | CMD_PIO_WRITE_A_16,
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| 74 | /**
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| 75 | * Write 4 bytes from the source argument
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| 76 | * to the I/O space.
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| 77 | */
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| 78 | CMD_PIO_WRITE_A_32,
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| 79 |
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| 80 | /**
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| 81 | * Perform a bit masking on the source argument
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| 82 | * and store the result into the destination argument.
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[22af3af] | 83 | */
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[cecb0789] | 84 | CMD_BTEST,
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[da1bafb] | 85 |
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[22af3af] | 86 | /**
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[9cdac5a] | 87 | * Predicate the execution of the following
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| 88 | * N commands by the boolean value of the source
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| 89 | * argument.
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[22af3af] | 90 | */
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[cecb0789] | 91 | CMD_PREDICATE,
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[da1bafb] | 92 |
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[22af3af] | 93 | /** Accept the interrupt. */
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[cecb0789] | 94 | CMD_ACCEPT,
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[9cdac5a] | 95 |
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[22af3af] | 96 | /** Decline the interrupt. */
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[cecb0789] | 97 | CMD_DECLINE,
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[b3f8fb7] | 98 | CMD_LAST
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| 99 | } irq_cmd_type;
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| 100 |
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| 101 | typedef struct {
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| 102 | irq_cmd_type cmd;
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| 103 | void *addr;
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[da1bafb] | 104 | uint32_t value;
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| 105 | uintptr_t srcarg;
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| 106 | uintptr_t dstarg;
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[b3f8fb7] | 107 | } irq_cmd_t;
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| 108 |
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| 109 | typedef struct {
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[da1bafb] | 110 | size_t cmdcount;
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[b3f8fb7] | 111 | irq_cmd_t *cmds;
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| 112 | } irq_code_t;
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| 113 |
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| 114 | #ifdef KERNEL
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| 115 |
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[0d107f31] | 116 | typedef enum {
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[da1bafb] | 117 | IRQ_DECLINE, /**< Decline to service. */
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| 118 | IRQ_ACCEPT /**< Accept to service. */
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[0d107f31] | 119 | } irq_ownership_t;
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| 120 |
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| 121 | typedef enum {
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| 122 | IRQ_TRIGGER_LEVEL = 1,
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| 123 | IRQ_TRIGGER_EDGE
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| 124 | } irq_trigger_t;
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| 125 |
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[b3f8fb7] | 126 | struct irq;
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[6cd9aa6] | 127 | typedef void (* irq_handler_t)(struct irq *);
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[b3f8fb7] | 128 |
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[8d2760f] | 129 | /** Type for function used to clear the interrupt. */
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[6cd9aa6] | 130 | typedef void (* cir_t)(void *, inr_t);
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[8d2760f] | 131 |
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[b3f8fb7] | 132 | /** IPC notification config structure.
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| 133 | *
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| 134 | * Primarily, this structure is encapsulated in the irq_t structure.
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| 135 | * It is protected by irq_t::lock.
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[da1bafb] | 136 | *
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[b3f8fb7] | 137 | */
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| 138 | typedef struct {
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[80bcaed] | 139 | /** When false, notifications are not sent. */
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| 140 | bool notify;
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| 141 | /** Answerbox for notifications. */
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| 142 | answerbox_t *answerbox;
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[228e490] | 143 | /** Interface and method to be used for the notification. */
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| 144 | sysarg_t imethod;
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[cecb0789] | 145 | /** Arguments that will be sent if the IRQ is claimed. */
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[da1bafb] | 146 | uint32_t scratch[IPC_CALL_LEN];
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[80bcaed] | 147 | /** Top-half pseudocode. */
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| 148 | irq_code_t *code;
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| 149 | /** Counter. */
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[98000fb] | 150 | size_t counter;
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[da1bafb] | 151 |
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[80bcaed] | 152 | /**
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| 153 | * Link between IRQs that are notifying the same answerbox. The list is
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| 154 | * protected by the answerbox irq_lock.
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| 155 | */
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| 156 | link_t link;
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[b3f8fb7] | 157 | } ipc_notif_cfg_t;
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[0d107f31] | 158 |
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| 159 | /** Structure representing one device IRQ.
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| 160 | *
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[80bcaed] | 161 | * If one device has multiple interrupts, there will be multiple irq_t
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| 162 | * instantions with the same devno.
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[da1bafb] | 163 | *
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[0d107f31] | 164 | */
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[b3f8fb7] | 165 | typedef struct irq {
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[0d107f31] | 166 | /** Hash table link. */
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| 167 | link_t link;
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[da1bafb] | 168 |
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[63530c62] | 169 | /** Lock protecting everything in this structure
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| 170 | * except the link member. When both the IRQ
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| 171 | * hash table lock and this lock are to be acquired,
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| 172 | * this lock must not be taken first.
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| 173 | */
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[da1bafb] | 174 | IRQ_SPINLOCK_DECLARE(lock);
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[7bcfbbc] | 175 |
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| 176 | /** Send EOI before processing the interrupt.
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| 177 | * This is essential for timer interrupt which
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| 178 | * has to be acknowledged before doing preemption
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| 179 | * to make sure another timer interrupt will
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| 180 | * be eventually generated.
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| 181 | */
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| 182 | bool preack;
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[da1bafb] | 183 |
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[0d107f31] | 184 | /** Unique device number. -1 if not yet assigned. */
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| 185 | devno_t devno;
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[da1bafb] | 186 |
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[0d107f31] | 187 | /** Actual IRQ number. -1 if not yet assigned. */
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| 188 | inr_t inr;
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[7bcfbbc] | 189 | /** Trigger level of the IRQ. */
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[0d107f31] | 190 | irq_trigger_t trigger;
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| 191 | /** Claim ownership of the IRQ. */
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[c9b550b] | 192 | irq_ownership_t (* claim)(struct irq *);
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[0d107f31] | 193 | /** Handler for this IRQ and device. */
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| 194 | irq_handler_t handler;
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[6cd9aa6] | 195 | /** Instance argument for the handler and the claim function. */
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| 196 | void *instance;
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[da1bafb] | 197 |
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[8d2760f] | 198 | /** Clear interrupt routine. */
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| 199 | cir_t cir;
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| 200 | /** First argument to the clear interrupt routine. */
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| 201 | void *cir_arg;
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[da1bafb] | 202 |
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[2b017ba] | 203 | /** Notification configuration structure. */
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| 204 | ipc_notif_cfg_t notif_cfg;
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[b3f8fb7] | 205 | } irq_t;
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[0d107f31] | 206 |
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[da1bafb] | 207 | IRQ_SPINLOCK_EXTERN(irq_uspace_hash_table_lock);
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[cecb0789] | 208 | extern hash_table_t irq_uspace_hash_table;
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| 209 |
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[78ffb70] | 210 | extern inr_t last_inr;
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| 211 |
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[98000fb] | 212 | extern void irq_init(size_t, size_t);
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[6cd9aa6] | 213 | extern void irq_initialize(irq_t *);
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| 214 | extern void irq_register(irq_t *);
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| 215 | extern irq_t *irq_dispatch_and_lock(inr_t);
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[0d107f31] | 216 |
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[da1bafb] | 217 | #endif /* KERNEL */
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[0d107f31] | 218 |
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[b3f8fb7] | 219 | #endif
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| 220 |
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[0d107f31] | 221 | /** @}
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| 222 | */
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