source: mainline/kernel/generic/include/ddi/irq.h@ 97186929

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 97186929 was 9cdac5a, checked in by martin@…>, 15 years ago

add CMD_PIO_WRITE_A_x commands which store values from scratch space to I/O space

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File size: 5.5 KB
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[0d107f31]1/*
[df4ed85]2 * Copyright (c) 2006 Jakub Jermar
[0d107f31]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[7dcf22a]29/** @addtogroup genericddi
[0d107f31]30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_IRQ_H_
36#define KERN_IRQ_H_
37
[da1bafb]38#ifdef KERNEL
39
40#include <typedefs.h>
41#include <adt/list.h>
42#include <adt/hash_table.h>
43#include <synch/spinlock.h>
44#include <proc/task.h>
45#include <ipc/ipc.h>
46
47#endif /* KERNEL */
48
[b3f8fb7]49typedef enum {
[22af3af]50 /** Read 1 byte from the I/O space. */
[cecb0789]51 CMD_PIO_READ_8 = 1,
[22af3af]52 /** Read 2 bytes from the I/O space. */
[cecb0789]53 CMD_PIO_READ_16,
[22af3af]54 /** Read 4 bytes from the I/O space. */
[cecb0789]55 CMD_PIO_READ_32,
[9cdac5a]56
[22af3af]57 /** Write 1 byte to the I/O space. */
[cecb0789]58 CMD_PIO_WRITE_8,
[22af3af]59 /** Write 2 bytes to the I/O space. */
[cecb0789]60 CMD_PIO_WRITE_16,
[22af3af]61 /** Write 4 bytes to the I/O space. */
[cecb0789]62 CMD_PIO_WRITE_32,
[da1bafb]63
[22af3af]64 /**
[9cdac5a]65 * Write 1 byte from the source argument
66 * to the I/O space.
67 */
68 CMD_PIO_WRITE_A_8,
69 /**
70 * Write 2 bytes from the source argument
71 * to the I/O space.
72 */
73 CMD_PIO_WRITE_A_16,
74 /**
75 * Write 4 bytes from the source argument
76 * to the I/O space.
77 */
78 CMD_PIO_WRITE_A_32,
79
80 /**
81 * Perform a bit masking on the source argument
82 * and store the result into the destination argument.
[22af3af]83 */
[cecb0789]84 CMD_BTEST,
[da1bafb]85
[22af3af]86 /**
[9cdac5a]87 * Predicate the execution of the following
88 * N commands by the boolean value of the source
89 * argument.
[22af3af]90 */
[cecb0789]91 CMD_PREDICATE,
[da1bafb]92
[22af3af]93 /** Accept the interrupt. */
[cecb0789]94 CMD_ACCEPT,
[9cdac5a]95
[22af3af]96 /** Decline the interrupt. */
[cecb0789]97 CMD_DECLINE,
[b3f8fb7]98 CMD_LAST
99} irq_cmd_type;
100
101typedef struct {
102 irq_cmd_type cmd;
103 void *addr;
[da1bafb]104 uint32_t value;
105 uintptr_t srcarg;
106 uintptr_t dstarg;
[b3f8fb7]107} irq_cmd_t;
108
109typedef struct {
[da1bafb]110 size_t cmdcount;
[b3f8fb7]111 irq_cmd_t *cmds;
112} irq_code_t;
113
114#ifdef KERNEL
115
[0d107f31]116typedef enum {
[da1bafb]117 IRQ_DECLINE, /**< Decline to service. */
118 IRQ_ACCEPT /**< Accept to service. */
[0d107f31]119} irq_ownership_t;
120
121typedef enum {
122 IRQ_TRIGGER_LEVEL = 1,
123 IRQ_TRIGGER_EDGE
124} irq_trigger_t;
125
[b3f8fb7]126struct irq;
[6cd9aa6]127typedef void (* irq_handler_t)(struct irq *);
[b3f8fb7]128
[8d2760f]129/** Type for function used to clear the interrupt. */
[6cd9aa6]130typedef void (* cir_t)(void *, inr_t);
[8d2760f]131
[b3f8fb7]132/** IPC notification config structure.
133 *
134 * Primarily, this structure is encapsulated in the irq_t structure.
135 * It is protected by irq_t::lock.
[da1bafb]136 *
[b3f8fb7]137 */
138typedef struct {
[80bcaed]139 /** When false, notifications are not sent. */
140 bool notify;
141 /** Answerbox for notifications. */
142 answerbox_t *answerbox;
[228e490]143 /** Interface and method to be used for the notification. */
144 sysarg_t imethod;
[cecb0789]145 /** Arguments that will be sent if the IRQ is claimed. */
[da1bafb]146 uint32_t scratch[IPC_CALL_LEN];
[80bcaed]147 /** Top-half pseudocode. */
148 irq_code_t *code;
149 /** Counter. */
[98000fb]150 size_t counter;
[da1bafb]151
[80bcaed]152 /**
153 * Link between IRQs that are notifying the same answerbox. The list is
154 * protected by the answerbox irq_lock.
155 */
156 link_t link;
[b3f8fb7]157} ipc_notif_cfg_t;
[0d107f31]158
159/** Structure representing one device IRQ.
160 *
[80bcaed]161 * If one device has multiple interrupts, there will be multiple irq_t
162 * instantions with the same devno.
[da1bafb]163 *
[0d107f31]164 */
[b3f8fb7]165typedef struct irq {
[0d107f31]166 /** Hash table link. */
167 link_t link;
[da1bafb]168
[63530c62]169 /** Lock protecting everything in this structure
170 * except the link member. When both the IRQ
171 * hash table lock and this lock are to be acquired,
172 * this lock must not be taken first.
173 */
[da1bafb]174 IRQ_SPINLOCK_DECLARE(lock);
[7bcfbbc]175
176 /** Send EOI before processing the interrupt.
177 * This is essential for timer interrupt which
178 * has to be acknowledged before doing preemption
179 * to make sure another timer interrupt will
180 * be eventually generated.
181 */
182 bool preack;
[da1bafb]183
[0d107f31]184 /** Unique device number. -1 if not yet assigned. */
185 devno_t devno;
[da1bafb]186
[0d107f31]187 /** Actual IRQ number. -1 if not yet assigned. */
188 inr_t inr;
[7bcfbbc]189 /** Trigger level of the IRQ. */
[0d107f31]190 irq_trigger_t trigger;
191 /** Claim ownership of the IRQ. */
[c9b550b]192 irq_ownership_t (* claim)(struct irq *);
[0d107f31]193 /** Handler for this IRQ and device. */
194 irq_handler_t handler;
[6cd9aa6]195 /** Instance argument for the handler and the claim function. */
196 void *instance;
[da1bafb]197
[8d2760f]198 /** Clear interrupt routine. */
199 cir_t cir;
200 /** First argument to the clear interrupt routine. */
201 void *cir_arg;
[da1bafb]202
[2b017ba]203 /** Notification configuration structure. */
204 ipc_notif_cfg_t notif_cfg;
[b3f8fb7]205} irq_t;
[0d107f31]206
[da1bafb]207IRQ_SPINLOCK_EXTERN(irq_uspace_hash_table_lock);
[cecb0789]208extern hash_table_t irq_uspace_hash_table;
209
[78ffb70]210extern inr_t last_inr;
211
[98000fb]212extern void irq_init(size_t, size_t);
[6cd9aa6]213extern void irq_initialize(irq_t *);
214extern void irq_register(irq_t *);
215extern irq_t *irq_dispatch_and_lock(inr_t);
[0d107f31]216
[da1bafb]217#endif /* KERNEL */
[0d107f31]218
[b3f8fb7]219#endif
220
[0d107f31]221/** @}
222 */
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