source: mainline/kernel/generic/include/ddi/irq.h@ 3b543d5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3b543d5 was 180255f, checked in by Jan Vesely <jano.vesely@…>, 15 years ago

Implement access to memory mapped register in irq pseudocode.

  • Property mode set to 100644
File size: 6.2 KB
RevLine 
[0d107f31]1/*
[df4ed85]2 * Copyright (c) 2006 Jakub Jermar
[0d107f31]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[7dcf22a]29/** @addtogroup genericddi
[0d107f31]30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_IRQ_H_
36#define KERN_IRQ_H_
37
[da1bafb]38#ifdef KERNEL
39
40#include <typedefs.h>
41#include <adt/list.h>
42#include <adt/hash_table.h>
43#include <synch/spinlock.h>
44#include <proc/task.h>
45#include <ipc/ipc.h>
46
47#endif /* KERNEL */
48
[b3f8fb7]49typedef enum {
[22af3af]50 /** Read 1 byte from the I/O space. */
[cecb0789]51 CMD_PIO_READ_8 = 1,
[22af3af]52 /** Read 2 bytes from the I/O space. */
[cecb0789]53 CMD_PIO_READ_16,
[22af3af]54 /** Read 4 bytes from the I/O space. */
[cecb0789]55 CMD_PIO_READ_32,
[9cdac5a]56
[22af3af]57 /** Write 1 byte to the I/O space. */
[cecb0789]58 CMD_PIO_WRITE_8,
[22af3af]59 /** Write 2 bytes to the I/O space. */
[cecb0789]60 CMD_PIO_WRITE_16,
[22af3af]61 /** Write 4 bytes to the I/O space. */
[cecb0789]62 CMD_PIO_WRITE_32,
[da1bafb]63
[22af3af]64 /**
[9cdac5a]65 * Write 1 byte from the source argument
66 * to the I/O space.
67 */
68 CMD_PIO_WRITE_A_8,
69 /**
70 * Write 2 bytes from the source argument
71 * to the I/O space.
72 */
73 CMD_PIO_WRITE_A_16,
74 /**
75 * Write 4 bytes from the source argument
76 * to the I/O space.
77 */
78 CMD_PIO_WRITE_A_32,
[f7ccf46]79
80 /** Read 1 byte from the memory space. */
81 CMD_MEM_READ_8,
82 /** Read 2 bytes from the memory space. */
83 CMD_MEM_READ_16,
84 /** Read 4 bytes from the memory space. */
85 CMD_MEM_READ_32,
86
87 /** Write 1 byte to the memory space. */
88 CMD_MEM_WRITE_8,
89 /** Write 2 bytes to the memory space. */
90 CMD_MEM_WRITE_16,
91 /** Write 4 bytes to the memory space. */
92 CMD_MEM_WRITE_32,
93
94 /** Write 1 byte from the source argument to the memory space. */
95 CMD_MEM_WRITE_A_8,
96 /** Write 2 bytes from the source argument to the memory space. */
97 CMD_MEM_WRITE_A_16,
98 /** Write 4 bytes from the source argument to the memory space. */
99 CMD_MEM_WRITE_A_32,
100
[9cdac5a]101 /**
102 * Perform a bit masking on the source argument
103 * and store the result into the destination argument.
[22af3af]104 */
[cecb0789]105 CMD_BTEST,
[da1bafb]106
[22af3af]107 /**
[9cdac5a]108 * Predicate the execution of the following
109 * N commands by the boolean value of the source
110 * argument.
[22af3af]111 */
[cecb0789]112 CMD_PREDICATE,
[da1bafb]113
[22af3af]114 /** Accept the interrupt. */
[cecb0789]115 CMD_ACCEPT,
[9cdac5a]116
[22af3af]117 /** Decline the interrupt. */
[cecb0789]118 CMD_DECLINE,
[b3f8fb7]119 CMD_LAST
120} irq_cmd_type;
121
122typedef struct {
123 irq_cmd_type cmd;
124 void *addr;
[da1bafb]125 uint32_t value;
126 uintptr_t srcarg;
127 uintptr_t dstarg;
[b3f8fb7]128} irq_cmd_t;
129
130typedef struct {
[da1bafb]131 size_t cmdcount;
[b3f8fb7]132 irq_cmd_t *cmds;
133} irq_code_t;
134
135#ifdef KERNEL
136
[0d107f31]137typedef enum {
[da1bafb]138 IRQ_DECLINE, /**< Decline to service. */
139 IRQ_ACCEPT /**< Accept to service. */
[0d107f31]140} irq_ownership_t;
141
142typedef enum {
143 IRQ_TRIGGER_LEVEL = 1,
144 IRQ_TRIGGER_EDGE
145} irq_trigger_t;
146
[b3f8fb7]147struct irq;
[6cd9aa6]148typedef void (* irq_handler_t)(struct irq *);
[b3f8fb7]149
[8d2760f]150/** Type for function used to clear the interrupt. */
[6cd9aa6]151typedef void (* cir_t)(void *, inr_t);
[8d2760f]152
[b3f8fb7]153/** IPC notification config structure.
154 *
155 * Primarily, this structure is encapsulated in the irq_t structure.
156 * It is protected by irq_t::lock.
[da1bafb]157 *
[b3f8fb7]158 */
159typedef struct {
[80bcaed]160 /** When false, notifications are not sent. */
161 bool notify;
162 /** Answerbox for notifications. */
163 answerbox_t *answerbox;
[228e490]164 /** Interface and method to be used for the notification. */
165 sysarg_t imethod;
[cecb0789]166 /** Arguments that will be sent if the IRQ is claimed. */
[da1bafb]167 uint32_t scratch[IPC_CALL_LEN];
[80bcaed]168 /** Top-half pseudocode. */
169 irq_code_t *code;
170 /** Counter. */
[98000fb]171 size_t counter;
[da1bafb]172
[80bcaed]173 /**
174 * Link between IRQs that are notifying the same answerbox. The list is
175 * protected by the answerbox irq_lock.
176 */
177 link_t link;
[b3f8fb7]178} ipc_notif_cfg_t;
[0d107f31]179
180/** Structure representing one device IRQ.
181 *
[80bcaed]182 * If one device has multiple interrupts, there will be multiple irq_t
183 * instantions with the same devno.
[da1bafb]184 *
[0d107f31]185 */
[b3f8fb7]186typedef struct irq {
[0d107f31]187 /** Hash table link. */
188 link_t link;
[da1bafb]189
[63530c62]190 /** Lock protecting everything in this structure
191 * except the link member. When both the IRQ
192 * hash table lock and this lock are to be acquired,
193 * this lock must not be taken first.
194 */
[da1bafb]195 IRQ_SPINLOCK_DECLARE(lock);
[7bcfbbc]196
197 /** Send EOI before processing the interrupt.
198 * This is essential for timer interrupt which
199 * has to be acknowledged before doing preemption
200 * to make sure another timer interrupt will
201 * be eventually generated.
202 */
203 bool preack;
[da1bafb]204
[0d107f31]205 /** Unique device number. -1 if not yet assigned. */
206 devno_t devno;
[da1bafb]207
[0d107f31]208 /** Actual IRQ number. -1 if not yet assigned. */
209 inr_t inr;
[7bcfbbc]210 /** Trigger level of the IRQ. */
[0d107f31]211 irq_trigger_t trigger;
212 /** Claim ownership of the IRQ. */
[c9b550b]213 irq_ownership_t (* claim)(struct irq *);
[0d107f31]214 /** Handler for this IRQ and device. */
215 irq_handler_t handler;
[6cd9aa6]216 /** Instance argument for the handler and the claim function. */
217 void *instance;
[da1bafb]218
[8d2760f]219 /** Clear interrupt routine. */
220 cir_t cir;
221 /** First argument to the clear interrupt routine. */
222 void *cir_arg;
[da1bafb]223
[2b017ba]224 /** Notification configuration structure. */
225 ipc_notif_cfg_t notif_cfg;
[180255f]226
227 as_t *driver_as;
[b3f8fb7]228} irq_t;
[0d107f31]229
[da1bafb]230IRQ_SPINLOCK_EXTERN(irq_uspace_hash_table_lock);
[cecb0789]231extern hash_table_t irq_uspace_hash_table;
232
[78ffb70]233extern inr_t last_inr;
234
[98000fb]235extern void irq_init(size_t, size_t);
[6cd9aa6]236extern void irq_initialize(irq_t *);
237extern void irq_register(irq_t *);
238extern irq_t *irq_dispatch_and_lock(inr_t);
[0d107f31]239
[da1bafb]240#endif /* KERNEL */
[0d107f31]241
[b3f8fb7]242#endif
243
[0d107f31]244/** @}
245 */
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