[b38c079] | 1 | /*
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| 2 | * Copyright (c) 2012 Jan Vesely
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| 3 | * Copyright (c) 2013 Maurizio Lombardi
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 | /** @addtogroup genarch
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| 30 | * @{
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| 31 | */
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| 32 | /**
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| 33 | * @file
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| 34 | * @brief Texas Instruments OMAP on-chip uart serial line driver.
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| 35 | */
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| 36 |
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[63e27ef] | 37 | #include <assert.h>
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[b38c079] | 38 | #include <genarch/drivers/omap/uart.h>
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| 39 | #include <ddi/device.h>
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| 40 | #include <str.h>
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| 41 | #include <mm/km.h>
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| 42 |
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| 43 | static void omap_uart_txb(omap_uart_t *uart, uint8_t b)
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| 44 | {
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| 45 | /* Wait for buffer */
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| 46 | while (uart->regs->ssr & OMAP_UART_SSR_TX_FIFO_FULL_FLAG);
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| 47 | /* Write to the outgoing fifo */
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| 48 | uart->regs->thr = b;
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| 49 | }
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| 50 |
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| 51 | static void omap_uart_putchar(outdev_t *dev, wchar_t ch)
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| 52 | {
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| 53 | omap_uart_t *uart = dev->data;
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| 54 | if (!ascii_check(ch)) {
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| 55 | omap_uart_txb(uart, U_SPECIAL);
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| 56 | } else {
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| 57 | if (ch == '\n')
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| 58 | omap_uart_txb(uart, '\r');
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| 59 | omap_uart_txb(uart, ch);
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| 60 | }
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| 61 | }
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| 62 |
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| 63 | static outdev_operations_t omap_uart_ops = {
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| 64 | .write = omap_uart_putchar,
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[7ddc2c7] | 65 | .redraw = NULL,
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| 66 | .scroll_up = NULL,
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| 67 | .scroll_down = NULL
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[b38c079] | 68 | };
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| 69 |
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| 70 | static irq_ownership_t omap_uart_claim(irq_t *irq)
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| 71 | {
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| 72 | return IRQ_ACCEPT;
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| 73 | }
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| 74 |
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| 75 | static void omap_uart_handler(irq_t *irq)
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| 76 | {
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| 77 | omap_uart_t *uart = irq->instance;
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| 78 | while ((uart->regs->rx_fifo_lvl)) {
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| 79 | const uint8_t val = uart->regs->rhr;
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| 80 | if (uart->indev && val) {
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| 81 | indev_push_character(uart->indev, val);
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| 82 | }
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| 83 | }
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| 84 | }
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| 85 |
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| 86 | bool omap_uart_init(
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| 87 | omap_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
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| 88 | {
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[63e27ef] | 89 | assert(uart);
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[b38c079] | 90 | uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
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| 91 |
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[63e27ef] | 92 | assert(uart->regs);
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[b38c079] | 93 |
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| 94 | /* Soft reset the port */
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| 95 | uart->regs->sysc = OMAP_UART_SYSC_SOFTRESET_FLAG;
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| 96 | while (!(uart->regs->syss & OMAP_UART_SYSS_RESETDONE_FLAG));
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| 97 |
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| 98 | /* Disable the UART module */
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| 99 | uart->regs->mdr1 |= OMAP_UART_MDR_MS_DISABLE;
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| 100 |
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| 101 | /* Enable access to EFR register */
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| 102 | uart->regs->lcr = 0xbf; /* Sets config mode B */
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| 103 |
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| 104 | /* Enable access to TCL_TLR register */
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| 105 | const bool enhanced = uart->regs->efr & OMAP_UART_EFR_ENH_FLAG;
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| 106 | uart->regs->efr |= OMAP_UART_EFR_ENH_FLAG; /* Turn on enh. */
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| 107 | uart->regs->lcr = 0x80; /* Config mode A */
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| 108 |
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| 109 | /* Set default (val 0) triggers, disable DMA enable FIFOs */
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| 110 | const bool tcl_tlr = uart->regs->mcr & OMAP_UART_MCR_TCR_TLR_FLAG;
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| 111 | /* Enable access to tcr and tlr registers */
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| 112 | uart->regs->mcr |= OMAP_UART_MCR_TCR_TLR_FLAG;
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| 113 |
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| 114 | /* Enable FIFOs */
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| 115 | uart->regs->fcr = OMAP_UART_FCR_FIFO_EN_FLAG;
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| 116 |
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| 117 | /* Enable fine granularity for RX FIFO and set trigger level to 1,
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| 118 | * TX FIFO, trigger level is irrelevant*/
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| 119 | uart->regs->lcr = 0xBF; /* Sets config mode B */
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| 120 | uart->regs->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_FLAG;
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| 121 | uart->regs->tlr = 1 << OMAP_UART_TLR_RX_FIFO_TRIG_SHIFT;
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| 122 |
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| 123 | /* Sets config mode A */
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| 124 | uart->regs->lcr = 0x80;
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| 125 | /* Restore tcl_tlr access flag */
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| 126 | if (!tcl_tlr)
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| 127 | uart->regs->mcr &= ~OMAP_UART_MCR_TCR_TLR_FLAG;
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| 128 | /* Sets config mode B */
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| 129 | uart->regs->lcr = 0xBF;
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| 130 |
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| 131 | /* Set the divisor value to get a baud rate of 115200 bps */
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| 132 | uart->regs->dll = 0x1A;
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| 133 | uart->regs->dlh = 0x00;
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| 134 |
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| 135 | /* Restore enhanced */
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| 136 | if (!enhanced)
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| 137 | uart->regs->efr &= ~OMAP_UART_EFR_ENH_FLAG;
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| 138 |
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| 139 | /* Set the DIV_EN bit to 0 */
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| 140 | uart->regs->lcr &= ~OMAP_UART_LCR_DIV_EN_FLAG;
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| 141 | /* Set the BREAK_EN bit to 0 */
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| 142 | uart->regs->lcr &= ~OMAP_UART_LCR_BREAK_EN_FLAG;
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| 143 | /* No parity */
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| 144 | uart->regs->lcr &= ~OMAP_UART_LCR_PARITY_EN_FLAG;
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| 145 | /* Stop = 1 bit */
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| 146 | uart->regs->lcr &= ~OMAP_UART_LCR_NB_STOP_FLAG;
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| 147 | /* Char length = 8 bits */
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| 148 | uart->regs->lcr |= OMAP_UART_LCR_CHAR_LENGTH_8BITS;
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| 149 |
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| 150 | /* Enable the UART module */
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| 151 | uart->regs->mdr1 &= (OMAP_UART_MDR_MS_UART16 &
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| 152 | ~OMAP_UART_MDR_MS_MASK);
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| 153 |
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| 154 | /* Disable interrupts */
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| 155 | uart->regs->ier = 0;
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| 156 |
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| 157 | /* Setup outdev */
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| 158 | outdev_initialize("omap_uart_dev", &uart->outdev, &omap_uart_ops);
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| 159 | uart->outdev.data = uart;
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| 160 |
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| 161 | /* Initialize IRQ */
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| 162 | irq_initialize(&uart->irq);
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| 163 | uart->irq.devno = device_assign_devno();
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| 164 | uart->irq.inr = interrupt;
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| 165 | uart->irq.claim = omap_uart_claim;
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| 166 | uart->irq.handler = omap_uart_handler;
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| 167 | uart->irq.instance = uart;
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| 168 |
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| 169 | return true;
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| 170 | }
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| 171 |
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| 172 | void omap_uart_input_wire(omap_uart_t *uart, indev_t *indev)
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| 173 | {
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[63e27ef] | 174 | assert(uart);
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[b38c079] | 175 | /* Set indev */
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| 176 | uart->indev = indev;
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| 177 | /* Register interrupt. */
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| 178 | irq_register(&uart->irq);
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| 179 | /* Enable interrupt on receive */
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| 180 | uart->regs->ier |= OMAP_UART_IER_RHR_IRQ_FLAG;
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| 181 | }
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| 182 |
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| 183 | /**
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| 184 | * @}
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| 185 | */
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| 186 |
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