source: mainline/kernel/arch/sparc64/src/trap/trap_table.S@ e0b241f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e0b241f was beb3926a, checked in by Jakub Jermar <jakub@…>, 19 years ago

sparc64 work.
Handle situation when there are more valid windows than NWINDOW - 2 during
the return to userspace in preemtpible_handler().

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File size: 18.1 KB
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1#
2# Copyright (C) 2005 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29/**
30 * This file contains kernel trap table.
31 */
32
33.register %g2, #scratch
34.register %g3, #scratch
35
36.text
37
38#include <arch/trap/trap_table.h>
39#include <arch/trap/regwin.h>
40#include <arch/trap/interrupt.h>
41#include <arch/trap/exception.h>
42#include <arch/trap/mmu.h>
43#include <arch/mm/page.h>
44#include <arch/stack.h>
45#include <arch/regdef.h>
46
47#define TABLE_SIZE TRAP_TABLE_SIZE
48#define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE
49
50/*
51 * Kernel trap table.
52 */
53.align TABLE_SIZE
54.global trap_table
55trap_table:
56
57/* TT = 0x08, TL = 0, instruction_access_exception */
58.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
59.global instruction_access_exception
60instruction_access_exception:
61 SIMPLE_HANDLER do_instruction_access_exc
62
63/* TT = 0x10, TL = 0, illegal_instruction */
64.org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
65.global illegal_instruction
66illegal_instruction:
67 SIMPLE_HANDLER do_illegal_instruction
68
69/* TT = 0x24, TL = 0, clean_window handler */
70.org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
71.global clean_window_handler
72clean_window_handler:
73 CLEAN_WINDOW_HANDLER
74
75/* TT = 0x32, TL = 0, data_access_error */
76.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
77.global data_access_error
78data_access_error:
79 SIMPLE_HANDLER do_data_access_error
80
81/* TT = 0x34, TL = 0, mem_address_not_aligned */
82.org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
83.global mem_address_not_aligned
84mem_address_not_aligned:
85 SIMPLE_HANDLER do_mem_address_not_aligned
86
87/* TT = 0x41, TL = 0, interrupt_level_1 handler */
88.org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE
89.global interrupt_level_1_handler
90interrupt_level_1_handler:
91 INTERRUPT_LEVEL_N_HANDLER 1
92
93/* TT = 0x42, TL = 0, interrupt_level_2 handler */
94.org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE
95.global interrupt_level_2_handler
96interrupt_level_2_handler:
97 INTERRUPT_LEVEL_N_HANDLER 2
98
99/* TT = 0x43, TL = 0, interrupt_level_3 handler */
100.org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE
101.global interrupt_level_3_handler
102interrupt_level_3_handler:
103 INTERRUPT_LEVEL_N_HANDLER 3
104
105/* TT = 0x44, TL = 0, interrupt_level_4 handler */
106.org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE
107.global interrupt_level_4_handler
108interrupt_level_4_handler:
109 INTERRUPT_LEVEL_N_HANDLER 4
110
111/* TT = 0x45, TL = 0, interrupt_level_5 handler */
112.org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE
113.global interrupt_level_5_handler
114interrupt_level_5_handler:
115 INTERRUPT_LEVEL_N_HANDLER 5
116
117/* TT = 0x46, TL = 0, interrupt_level_6 handler */
118.org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE
119.global interrupt_level_6_handler
120interrupt_level_6_handler:
121 INTERRUPT_LEVEL_N_HANDLER 6
122
123/* TT = 0x47, TL = 0, interrupt_level_7 handler */
124.org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE
125.global interrupt_level_7_handler
126interrupt_level_7_handler:
127 INTERRUPT_LEVEL_N_HANDLER 7
128
129/* TT = 0x48, TL = 0, interrupt_level_8 handler */
130.org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE
131.global interrupt_level_8_handler
132interrupt_level_8_handler:
133 INTERRUPT_LEVEL_N_HANDLER 8
134
135/* TT = 0x49, TL = 0, interrupt_level_9 handler */
136.org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE
137.global interrupt_level_9_handler
138interrupt_level_9_handler:
139 INTERRUPT_LEVEL_N_HANDLER 9
140
141/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
142.org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE
143.global interrupt_level_10_handler
144interrupt_level_10_handler:
145 INTERRUPT_LEVEL_N_HANDLER 10
146
147/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
148.org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE
149.global interrupt_level_11_handler
150interrupt_level_11_handler:
151 INTERRUPT_LEVEL_N_HANDLER 11
152
153/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
154.org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE
155.global interrupt_level_12_handler
156interrupt_level_12_handler:
157 INTERRUPT_LEVEL_N_HANDLER 12
158
159/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
160.org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE
161.global interrupt_level_13_handler
162interrupt_level_13_handler:
163 INTERRUPT_LEVEL_N_HANDLER 13
164
165/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
166.org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE
167.global interrupt_level_14_handler
168interrupt_level_14_handler:
169 INTERRUPT_LEVEL_N_HANDLER 14
170
171/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
172.org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE
173.global interrupt_level_15_handler
174interrupt_level_15_handler:
175 INTERRUPT_LEVEL_N_HANDLER 15
176
177/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
178.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
179.global interrupt_vector_trap_handler
180interrupt_vector_trap_handler:
181 INTERRUPT_VECTOR_TRAP_HANDLER
182
183/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
184.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
185.global fast_instruction_access_mmu_miss_handler
186fast_instruction_access_mmu_miss_handler:
187 FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
188
189/* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
190.org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
191.global fast_data_access_mmu_miss_handler
192fast_data_access_mmu_miss_handler:
193 FAST_DATA_ACCESS_MMU_MISS_HANDLER
194
195/* TT = 0x6c, TL = 0, fast_data_access_protection */
196.org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
197.global fast_data_access_protection_handler
198fast_data_access_protection_handler:
199 FAST_DATA_ACCESS_PROTECTION_HANDLER
200
201/* TT = 0x80, TL = 0, spill_0_normal handler */
202.org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
203.global spill_0_normal
204spill_0_normal:
205 SPILL_NORMAL_HANDLER_KERNEL
206
207/* TT = 0x84, TL = 0, spill_1_normal handler */
208.org trap_table + TT_SPILL_1_NORMAL*ENTRY_SIZE
209.global spill_1_normal
210spill_1_normal:
211 SPILL_NORMAL_HANDLER_USERSPACE
212
213/* TT = 0x88, TL = 0, spill_2_normal handler */
214.org trap_table + TT_SPILL_2_NORMAL*ENTRY_SIZE
215.global spill_2_normal
216spill_2_normal:
217 SPILL_TO_USPACE_WINDOW_BUFFER
218
219/* TT = 0xc0, TL = 0, fill_0_normal handler */
220.org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE
221.global fill_0_normal
222fill_0_normal:
223 FILL_NORMAL_HANDLER_KERNEL
224
225/* TT = 0xc4, TL = 0, fill_1_normal handler */
226.org trap_table + TT_FILL_1_NORMAL*ENTRY_SIZE
227.global fill_1_normal
228fill_1_normal:
229 FILL_NORMAL_HANDLER_USERSPACE
230
231/*
232 * Handlers for TL>0.
233 */
234
235/* TT = 0x08, TL > 0, instruction_access_exception */
236.org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
237.global instruction_access_exception_high
238instruction_access_exception_high:
239 SIMPLE_HANDLER do_instruction_access_exc
240
241/* TT = 0x10, TL > 0, illegal_instruction */
242.org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
243.global illegal_instruction_high
244illegal_instruction_high:
245 SIMPLE_HANDLER do_illegal_instruction
246
247/* TT = 0x24, TL > 0, clean_window handler */
248.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
249.global clean_window_handler_high
250clean_window_handler_high:
251 CLEAN_WINDOW_HANDLER
252
253/* TT = 0x32, TL > 0, data_access_error */
254.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
255.global data_access_error_high
256data_access_error_high:
257 SIMPLE_HANDLER do_data_access_error
258
259/* TT = 0x34, TL > 0, mem_address_not_aligned */
260.org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE
261.global mem_address_not_aligned_high
262mem_address_not_aligned_high:
263 SIMPLE_HANDLER do_mem_address_not_aligned
264
265/* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */
266.org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
267.global fast_instruction_access_mmu_miss_handler_high
268fast_instruction_access_mmu_miss_handler_high:
269 FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
270
271/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
272.org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
273.global fast_data_access_mmu_miss_handler_high
274fast_data_access_mmu_miss_handler_high:
275 FAST_DATA_ACCESS_MMU_MISS_HANDLER
276
277/* TT = 0x6c, TL > 0, fast_data_access_protection */
278.org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
279.global fast_data_access_protection_handler_high
280fast_data_access_protection_handler_high:
281 FAST_DATA_ACCESS_PROTECTION_HANDLER
282
283/* TT = 0x80, TL > 0, spill_0_normal handler */
284.org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE
285.global spill_0_normal_high
286spill_0_normal_high:
287 SPILL_NORMAL_HANDLER_KERNEL
288
289/* TT = 0x88, TL > 0, spill_2_normal handler */
290.org trap_table + (TT_SPILL_2_NORMAL+512)*ENTRY_SIZE
291.global spill_2_normal_high
292spill_2_normal_high:
293 SPILL_TO_USPACE_WINDOW_BUFFER
294
295/* TT = 0xa0, TL > 0, spill_0_other handler */
296.org trap_table + (TT_SPILL_0_OTHER+512)*ENTRY_SIZE
297.global spill_0_other_high
298spill_0_other_high:
299 SPILL_TO_USPACE_WINDOW_BUFFER
300
301/* TT = 0xc0, TL > 0, fill_0_normal handler */
302.org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE
303.global fill_0_normal_high
304fill_0_normal_high:
305 FILL_NORMAL_HANDLER_KERNEL
306
307
308/* Preemptible trap handler for TL=1.
309 *
310 * This trap handler makes arrangements to make calling of scheduler() from
311 * within a trap context possible. It is called from several other trap
312 * handlers.
313 *
314 * This function can be entered either with interrupt globals or alternate globals.
315 * Memory management trap handlers are obliged to switch to one of those global sets
316 * prior to calling this function. Register window management functions are not
317 * allowed to modify the alternate global registers.
318 *
319 * Input registers:
320 * %g1 Address of function to call.
321 * %g2 Argument for the function.
322 * %g6 Pre-set as kernel stack base if trap from userspace.
323 * %g7 Pre-set as address of the userspace window buffer.
324 */
325.global preemptible_handler
326preemptible_handler:
327 rdpr %tstate, %g3
328 andcc %g3, TSTATE_PRIV_BIT, %g0 ! if this trap came from the privileged mode...
329 bnz 0f ! ...skip setting of kernel stack and primary context
330 nop
331
332 /*
333 * Normal window spills will go to the userspace window buffer.
334 */
335 wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(2), %wstate
336
337 /*
338 * Switch to kernel stack. The old stack is
339 * automatically saved in the old window's %sp
340 * and the new window's %fp.
341 */
342 save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
343
344 /*
345 * Mark the CANSAVE windows as OTHER windows.
346 * Set CLEANWIN to NWINDOW-1 so that clean_window traps do not occur.
347 */
348 rdpr %cansave, %l0
349 wrpr %l0, %otherwin
350 wrpr %g0, %cansave
351 wrpr %g0, NWINDOW-1, %cleanwin
352
353 /*
354 * Switch to primary context 0.
355 */
356 mov VA_PRIMARY_CONTEXT_REG, %l0
357 stxa %g0, [%l0] ASI_DMMU
358 set kernel_image_start, %l0
359 flush %l0
360
361 ba 1f
362 nop
363
3640:
365 save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
366
367 /*
368 * At this moment, we are using the kernel stack
369 * and have successfully allocated a register window.
370 */
3711:
372
373 /*
374 * Other window spills will go to the userspace window buffer
375 * and normal spills will go to the kernel stack.
376 */
377 wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
378
379 /*
380 * Copy arguments.
381 */
382 mov %g1, %l0
383 mov %g2, %o0
384
385 /*
386 * Save TSTATE, TPC and TNPC aside.
387 */
388 rdpr %tstate, %g1
389 rdpr %tpc, %g2
390 rdpr %tnpc, %g3
391
392 /*
393 * The following memory accesses will not fault
394 * because special provisions are made to have
395 * the kernel stack of THREAD locked in DTLB.
396 */
397 stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
398 stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
399 stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
400
401 wrpr %g0, 0, %tl
402 wrpr %g0, PSTATE_PRIV_BIT, %pstate
403 SAVE_GLOBALS
404
405 /*
406 * Call the higher-level handler and pass istate as second parameter.
407 */
408 call %l0
409 add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
410
411 RESTORE_GLOBALS
412 wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
413 wrpr %g0, 1, %tl
414
415 /*
416 * Read TSTATE, TPC and TNPC from saved copy.
417 */
418 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
419 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
420 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
421
422 /*
423 * Restore TSTATE, TPC and TNPC from saved copies.
424 */
425 wrpr %g1, 0, %tstate
426 wrpr %g2, 0, %tpc
427 wrpr %g3, 0, %tnpc
428
429 /*
430 * If OTHERWIN is zero, then all the userspace windows have been
431 * spilled to kernel memory (i.e. register window buffer). If
432 * OTHERWIN is non-zero, then some userspace windows are still
433 * valid. Others might have been spilled. However, the CWP pointer
434 * needs no fixing because the scheduler had not been called.
435 */
436 rdpr %otherwin, %l0
437 brnz %l0, 0f
438 nop
439
440 /*
441 * OTHERWIN == 0
442 */
443
444 /*
445 * If TSTATE.CWP + 1 == CWP, then we still do not have to fix CWP.
446 */
447 and %g1, TSTATE_CWP_MASK, %l0
448 inc %l0
449 and %l0, TSTATE_CWP_MASK, %l0 ! %l0 mod NWINDOW
450 rdpr %cwp, %l1
451 cmp %l0, %l1
452 bz 0f ! CWP is ok
453 nop
454
455 /*
456 * Fix CWP.
457 * Just for reminder, the input registers in the current window
458 * are the output registers of the window to which we want to
459 * restore. Because the fill trap fills only input and local
460 * registers of a window, we need to preserve those output
461 * registers manually.
462 */
463 flushw
464 mov %sp, %g2
465 stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
466 stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
467 stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
468 stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
469 stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
470 stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
471 stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
472 stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
473 wrpr %l0, 0, %cwp
474 mov %g2, %sp
475 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
476 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
477 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
478 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
479 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
480 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
481 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
482 ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
483
484 /*
485 * OTHERWIN != 0 or fall-through from the OTHERWIN == 0 case.
486 * The CWP has already been restored to the value it had prior to the SAVE
487 * at the beginning of this function.
488 */
4890:
490 rdpr %tstate, %g1
491 andcc %g1, TSTATE_PRIV_BIT, %g0 ! if we are not returning to userspace...,
492 bnz 1f ! ...skip restoring userspace windows
493 nop
494
495 /*
496 * Spills and fills will be processed by the {spill,fill}_1_normal
497 * handlers.
498 */
499 wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate
500
501 rdpr %cwp, %g1
502 rdpr %otherwin, %g2
503
504 /*
505 * Skip all OTHERWIN windows and descend to the first window
506 * in the userspace window buffer.
507 */
508 sub %g1, %g2, %g3
509 dec %g3
510 and %g3, NWINDOW - 1, %g3
511 wrpr %g3, 0, %cwp
512
513 /*
514 * CWP is now in the window last saved in the userspace window buffer.
515 * Fill all windows stored in the buffer.
516 */
517 clr %g4
5180: andcc %g7, PAGE_WIDTH - 1, %g0 ! PAGE_SIZE alignment check
519 bz 0f ! %g7 is page-aligned, no more windows to refill
520 nop
521
522 add %g7, -STACK_WINDOW_SAVE_AREA_SIZE, %g7
523 ldx [%g7 + L0_OFFSET], %l0
524 ldx [%g7 + L1_OFFSET], %l1
525 ldx [%g7 + L2_OFFSET], %l2
526 ldx [%g7 + L3_OFFSET], %l3
527 ldx [%g7 + L4_OFFSET], %l4
528 ldx [%g7 + L5_OFFSET], %l5
529 ldx [%g7 + L6_OFFSET], %l6
530 ldx [%g7 + L7_OFFSET], %l7
531 ldx [%g7 + I0_OFFSET], %i0
532 ldx [%g7 + I1_OFFSET], %i1
533 ldx [%g7 + I2_OFFSET], %i2
534 ldx [%g7 + I3_OFFSET], %i3
535 ldx [%g7 + I4_OFFSET], %i4
536 ldx [%g7 + I5_OFFSET], %i5
537 ldx [%g7 + I6_OFFSET], %i6
538 ldx [%g7 + I7_OFFSET], %i7
539
540 dec %g3
541 and %g3, NWINDOW - 1, %g3
542 wrpr %g3, 0, %cwp ! switch to the preceeding window
543
544 ba 0b
545 inc %g4
546
5470:
548 /*
549 * Switch back to the proper current window and adjust
550 * OTHERWIN, CANRESTORE, CANSAVE and CLEANWIN.
551 */
552 wrpr %g1, 0, %cwp
553 add %g4, %g2, %g2
554 cmp %g2, NWINDOW - 2
555 bg 2f ! fix the CANRESTORE=NWINDOW-1 anomaly
556 mov NWINDOW - 2, %g1 ! use dealy slot for both cases
557 sub %g1, %g2, %g1
558
559 wrpr %g0, 0, %otherwin
560 wrpr %g1, 0, %cansave ! NWINDOW - 2 - CANRESTORE
561 wrpr %g2, 0, %canrestore ! OTHERWIN + windows in the buffer
562 wrpr %g2, 0, %cleanwin ! avoid information leak
563
5641:
565 restore
566 retry
567
568 /*
569 * We got here in order to avoid inconsistency of the window state registers.
570 * If the:
571 *
572 * save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
573 *
574 * instruction trapped and spilled a register window into the userspace
575 * window buffer, we have just restored NWINDOW - 1 register windows.
576 * However, CANRESTORE can be only NWINDOW - 2 at most.
577 *
578 * The solution is to manually switch to (CWP - 1) mod NWINDOW
579 * and set the window state registers so that:
580 *
581 * CANRESTORE = NWINDOW - 2
582 * CLEANWIN = NWINDOW - 2
583 * CANSAVE = 0
584 * OTHERWIN = 0
585 *
586 * The RESTORE isntruction is therfore to be skipped.
587 */
5882:
589 wrpr %g0, 0, %otherwin
590 wrpr %g0, 0, %cansave
591 wrpr %g1, 0, %canrestore
592 wrpr %g1, 0, %cleanwin
593
594 rdpr %cwp, %g1
595 dec %g1
596 and %g1, NWINDOW - 1, %g1
597 wrpr %g1, 0, %cwp ! CWP--
598
599 retry
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